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Commit | Line | Data |
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1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/slab.h> | |
15 | #include <linux/errno.h> | |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
20 | ||
23759dc6 | 21 | #include <asm/memory.h> |
43377453 | 22 | #include <asm/highmem.h> |
1da177e4 | 23 | #include <asm/cacheflush.h> |
1da177e4 | 24 | #include <asm/tlbflush.h> |
37134cd5 KH |
25 | #include <asm/sizes.h> |
26 | ||
27 | /* Sanity check size */ | |
28 | #if (CONSISTENT_DMA_SIZE % SZ_2M) | |
29 | #error "CONSISTENT_DMA_SIZE must be multiple of 2MiB" | |
30 | #endif | |
1da177e4 | 31 | |
1da177e4 | 32 | #define CONSISTENT_END (0xffe00000) |
37134cd5 KH |
33 | #define CONSISTENT_BASE (CONSISTENT_END - CONSISTENT_DMA_SIZE) |
34 | ||
1da177e4 | 35 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PAGE_SHIFT) |
37134cd5 KH |
36 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> PGDIR_SHIFT) |
37 | #define NUM_CONSISTENT_PTES (CONSISTENT_DMA_SIZE >> PGDIR_SHIFT) | |
38 | ||
ab6494f0 CM |
39 | static u64 get_coherent_dma_mask(struct device *dev) |
40 | { | |
41 | u64 mask = ISA_DMA_THRESHOLD; | |
42 | ||
43 | if (dev) { | |
44 | mask = dev->coherent_dma_mask; | |
45 | ||
46 | /* | |
47 | * Sanity check the DMA mask - it must be non-zero, and | |
48 | * must be able to be satisfied by a DMA allocation. | |
49 | */ | |
50 | if (mask == 0) { | |
51 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
52 | return 0; | |
53 | } | |
54 | ||
55 | if ((~mask) & ISA_DMA_THRESHOLD) { | |
56 | dev_warn(dev, "coherent DMA mask %#llx is smaller " | |
57 | "than system GFP_DMA mask %#llx\n", | |
58 | mask, (unsigned long long)ISA_DMA_THRESHOLD); | |
59 | return 0; | |
60 | } | |
61 | } | |
1da177e4 | 62 | |
ab6494f0 CM |
63 | return mask; |
64 | } | |
65 | ||
7a9a32a9 RK |
66 | /* |
67 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
68 | * specified gfp mask. Note that 'size' must be page aligned. | |
69 | */ | |
70 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
71 | { | |
72 | unsigned long order = get_order(size); | |
73 | struct page *page, *p, *e; | |
74 | void *ptr; | |
75 | u64 mask = get_coherent_dma_mask(dev); | |
76 | ||
77 | #ifdef CONFIG_DMA_API_DEBUG | |
78 | u64 limit = (mask + 1) & ~mask; | |
79 | if (limit && size >= limit) { | |
80 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
81 | size, mask); | |
82 | return NULL; | |
83 | } | |
84 | #endif | |
85 | ||
86 | if (!mask) | |
87 | return NULL; | |
88 | ||
89 | if (mask < 0xffffffffULL) | |
90 | gfp |= GFP_DMA; | |
91 | ||
92 | page = alloc_pages(gfp, order); | |
93 | if (!page) | |
94 | return NULL; | |
95 | ||
96 | /* | |
97 | * Now split the huge page and free the excess pages | |
98 | */ | |
99 | split_page(page, order); | |
100 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
101 | __free_page(p); | |
102 | ||
103 | /* | |
104 | * Ensure that the allocated pages are zeroed, and that any data | |
105 | * lurking in the kernel direct-mapped region is invalidated. | |
106 | */ | |
107 | ptr = page_address(page); | |
108 | memset(ptr, 0, size); | |
109 | dmac_flush_range(ptr, ptr + size); | |
110 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
111 | ||
112 | return page; | |
113 | } | |
114 | ||
115 | /* | |
116 | * Free a DMA buffer. 'size' must be page aligned. | |
117 | */ | |
118 | static void __dma_free_buffer(struct page *page, size_t size) | |
119 | { | |
120 | struct page *e = page + (size >> PAGE_SHIFT); | |
121 | ||
122 | while (page < e) { | |
123 | __free_page(page); | |
124 | page++; | |
125 | } | |
126 | } | |
127 | ||
ab6494f0 | 128 | #ifdef CONFIG_MMU |
1da177e4 | 129 | /* |
37134cd5 | 130 | * These are the page tables (2MB each) covering uncached, DMA consistent allocations |
1da177e4 | 131 | */ |
37134cd5 | 132 | static pte_t *consistent_pte[NUM_CONSISTENT_PTES]; |
1da177e4 | 133 | |
13ccf3ad | 134 | #include "vmregion.h" |
1da177e4 | 135 | |
13ccf3ad RK |
136 | static struct arm_vmregion_head consistent_head = { |
137 | .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock), | |
1da177e4 LT |
138 | .vm_list = LIST_HEAD_INIT(consistent_head.vm_list), |
139 | .vm_start = CONSISTENT_BASE, | |
140 | .vm_end = CONSISTENT_END, | |
141 | }; | |
142 | ||
1da177e4 LT |
143 | #ifdef CONFIG_HUGETLB_PAGE |
144 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
145 | #endif | |
146 | ||
147 | static void * | |
f9e3214a | 148 | __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, |
1da177e4 LT |
149 | pgprot_t prot) |
150 | { | |
151 | struct page *page; | |
13ccf3ad | 152 | struct arm_vmregion *c; |
1da177e4 | 153 | |
37134cd5 | 154 | if (!consistent_pte[0]) { |
1da177e4 LT |
155 | printk(KERN_ERR "%s: not initialised\n", __func__); |
156 | dump_stack(); | |
157 | return NULL; | |
158 | } | |
159 | ||
1da177e4 | 160 | size = PAGE_ALIGN(size); |
1da177e4 | 161 | |
7a9a32a9 | 162 | page = __dma_alloc_buffer(dev, size, gfp); |
1da177e4 LT |
163 | if (!page) |
164 | goto no_page; | |
165 | ||
1da177e4 LT |
166 | /* |
167 | * Allocate a virtual address in the consistent mapping region. | |
168 | */ | |
13ccf3ad | 169 | c = arm_vmregion_alloc(&consistent_head, size, |
1da177e4 LT |
170 | gfp & ~(__GFP_DMA | __GFP_HIGHMEM)); |
171 | if (c) { | |
37134cd5 | 172 | pte_t *pte; |
37134cd5 KH |
173 | int idx = CONSISTENT_PTE_INDEX(c->vm_start); |
174 | u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
1da177e4 | 175 | |
37134cd5 | 176 | pte = consistent_pte[idx] + off; |
1da177e4 LT |
177 | c->vm_pages = page; |
178 | ||
179 | /* | |
180 | * Set the "dma handle" | |
181 | */ | |
182 | *handle = page_to_dma(dev, page); | |
183 | ||
184 | do { | |
185 | BUG_ON(!pte_none(*pte)); | |
186 | ||
1da177e4 LT |
187 | /* |
188 | * x86 does not mark the pages reserved... | |
189 | */ | |
190 | SetPageReserved(page); | |
ad1ae2fe | 191 | set_pte_ext(pte, mk_pte(page, prot), 0); |
1da177e4 LT |
192 | page++; |
193 | pte++; | |
37134cd5 KH |
194 | off++; |
195 | if (off >= PTRS_PER_PTE) { | |
196 | off = 0; | |
197 | pte = consistent_pte[++idx]; | |
198 | } | |
1da177e4 LT |
199 | } while (size -= PAGE_SIZE); |
200 | ||
1da177e4 LT |
201 | return (void *)c->vm_start; |
202 | } | |
203 | ||
204 | if (page) | |
7a9a32a9 | 205 | __dma_free_buffer(page, size); |
1da177e4 LT |
206 | no_page: |
207 | *handle = ~0; | |
208 | return NULL; | |
209 | } | |
ab6494f0 CM |
210 | #else /* !CONFIG_MMU */ |
211 | static void * | |
212 | __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, | |
213 | pgprot_t prot) | |
214 | { | |
04da5694 | 215 | struct page *page; |
ab6494f0 | 216 | |
04da5694 RK |
217 | *handle = ~0; |
218 | size = PAGE_ALIGN(size); | |
ab6494f0 | 219 | |
04da5694 RK |
220 | page = __dma_alloc_buffer(dev, size, gfp); |
221 | if (!page) | |
222 | return NULL; | |
ab6494f0 | 223 | |
04da5694 RK |
224 | *handle = page_to_dma(dev, page); |
225 | return page_address(page); | |
ab6494f0 CM |
226 | } |
227 | #endif /* CONFIG_MMU */ | |
1da177e4 LT |
228 | |
229 | /* | |
230 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
231 | * virtual and bus address for that space. | |
232 | */ | |
233 | void * | |
f9e3214a | 234 | dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 | 235 | { |
1fe53268 DB |
236 | void *memory; |
237 | ||
238 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
239 | return memory; | |
240 | ||
23759dc6 | 241 | if (arch_is_coherent()) { |
3e82d012 | 242 | struct page *page; |
23759dc6 | 243 | |
3e82d012 RK |
244 | page = __dma_alloc_buffer(dev, PAGE_ALIGN(size), gfp); |
245 | if (!page) { | |
246 | *handle = ~0; | |
23759dc6 | 247 | return NULL; |
3e82d012 | 248 | } |
23759dc6 | 249 | |
3e82d012 RK |
250 | *handle = page_to_dma(dev, page); |
251 | return page_address(page); | |
23759dc6 LB |
252 | } |
253 | ||
1da177e4 LT |
254 | return __dma_alloc(dev, size, handle, gfp, |
255 | pgprot_noncached(pgprot_kernel)); | |
256 | } | |
257 | EXPORT_SYMBOL(dma_alloc_coherent); | |
258 | ||
259 | /* | |
260 | * Allocate a writecombining region, in much the same way as | |
261 | * dma_alloc_coherent above. | |
262 | */ | |
263 | void * | |
f9e3214a | 264 | dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 LT |
265 | { |
266 | return __dma_alloc(dev, size, handle, gfp, | |
267 | pgprot_writecombine(pgprot_kernel)); | |
268 | } | |
269 | EXPORT_SYMBOL(dma_alloc_writecombine); | |
270 | ||
271 | static int dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
272 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
273 | { | |
ab6494f0 CM |
274 | int ret = -ENXIO; |
275 | #ifdef CONFIG_MMU | |
13ccf3ad RK |
276 | unsigned long user_size, kern_size; |
277 | struct arm_vmregion *c; | |
1da177e4 LT |
278 | |
279 | user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; | |
280 | ||
13ccf3ad | 281 | c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr); |
1da177e4 LT |
282 | if (c) { |
283 | unsigned long off = vma->vm_pgoff; | |
284 | ||
285 | kern_size = (c->vm_end - c->vm_start) >> PAGE_SHIFT; | |
286 | ||
287 | if (off < kern_size && | |
288 | user_size <= (kern_size - off)) { | |
1da177e4 LT |
289 | ret = remap_pfn_range(vma, vma->vm_start, |
290 | page_to_pfn(c->vm_pages) + off, | |
291 | user_size << PAGE_SHIFT, | |
292 | vma->vm_page_prot); | |
293 | } | |
294 | } | |
ab6494f0 | 295 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
296 | |
297 | return ret; | |
298 | } | |
299 | ||
300 | int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, | |
301 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
302 | { | |
303 | vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot); | |
304 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); | |
305 | } | |
306 | EXPORT_SYMBOL(dma_mmap_coherent); | |
307 | ||
308 | int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma, | |
309 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
310 | { | |
311 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
312 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); | |
313 | } | |
314 | EXPORT_SYMBOL(dma_mmap_writecombine); | |
315 | ||
316 | /* | |
317 | * free a page as defined by the above mapping. | |
5edf71ae | 318 | * Must not be called with IRQs disabled. |
1da177e4 | 319 | */ |
ab6494f0 | 320 | #ifdef CONFIG_MMU |
1da177e4 LT |
321 | void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle) |
322 | { | |
13ccf3ad RK |
323 | struct arm_vmregion *c; |
324 | unsigned long addr; | |
1da177e4 | 325 | pte_t *ptep; |
37134cd5 KH |
326 | int idx; |
327 | u32 off; | |
1da177e4 | 328 | |
5edf71ae RK |
329 | WARN_ON(irqs_disabled()); |
330 | ||
1fe53268 DB |
331 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
332 | return; | |
333 | ||
3e82d012 RK |
334 | size = PAGE_ALIGN(size); |
335 | ||
23759dc6 | 336 | if (arch_is_coherent()) { |
3e82d012 | 337 | __dma_free_buffer(dma_to_page(dev, handle), size); |
23759dc6 LB |
338 | return; |
339 | } | |
340 | ||
13ccf3ad | 341 | c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr); |
1da177e4 LT |
342 | if (!c) |
343 | goto no_area; | |
344 | ||
345 | if ((c->vm_end - c->vm_start) != size) { | |
346 | printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n", | |
347 | __func__, c->vm_end - c->vm_start, size); | |
348 | dump_stack(); | |
349 | size = c->vm_end - c->vm_start; | |
350 | } | |
351 | ||
37134cd5 KH |
352 | idx = CONSISTENT_PTE_INDEX(c->vm_start); |
353 | off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
354 | ptep = consistent_pte[idx] + off; | |
1da177e4 LT |
355 | addr = c->vm_start; |
356 | do { | |
357 | pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep); | |
358 | unsigned long pfn; | |
359 | ||
360 | ptep++; | |
361 | addr += PAGE_SIZE; | |
37134cd5 KH |
362 | off++; |
363 | if (off >= PTRS_PER_PTE) { | |
364 | off = 0; | |
365 | ptep = consistent_pte[++idx]; | |
366 | } | |
1da177e4 LT |
367 | |
368 | if (!pte_none(pte) && pte_present(pte)) { | |
369 | pfn = pte_pfn(pte); | |
370 | ||
371 | if (pfn_valid(pfn)) { | |
372 | struct page *page = pfn_to_page(pfn); | |
373 | ||
374 | /* | |
375 | * x86 does not mark the pages reserved... | |
376 | */ | |
377 | ClearPageReserved(page); | |
1da177e4 LT |
378 | continue; |
379 | } | |
380 | } | |
1da177e4 LT |
381 | printk(KERN_CRIT "%s: bad page in kernel page table\n", |
382 | __func__); | |
383 | } while (size -= PAGE_SIZE); | |
384 | ||
385 | flush_tlb_kernel_range(c->vm_start, c->vm_end); | |
386 | ||
13ccf3ad | 387 | arm_vmregion_free(&consistent_head, c); |
7a9a32a9 RK |
388 | |
389 | __dma_free_buffer(dma_to_page(dev, handle), size); | |
1da177e4 LT |
390 | return; |
391 | ||
392 | no_area: | |
1da177e4 LT |
393 | printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n", |
394 | __func__, cpu_addr); | |
395 | dump_stack(); | |
396 | } | |
ab6494f0 CM |
397 | #else /* !CONFIG_MMU */ |
398 | void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle) | |
399 | { | |
400 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) | |
401 | return; | |
04da5694 | 402 | __dma_free_buffer(dma_to_page(dev, handle), PAGE_ALIGN(size)); |
ab6494f0 CM |
403 | } |
404 | #endif /* CONFIG_MMU */ | |
1da177e4 LT |
405 | EXPORT_SYMBOL(dma_free_coherent); |
406 | ||
407 | /* | |
408 | * Initialise the consistent memory allocation. | |
409 | */ | |
410 | static int __init consistent_init(void) | |
411 | { | |
ab6494f0 CM |
412 | int ret = 0; |
413 | #ifdef CONFIG_MMU | |
1da177e4 LT |
414 | pgd_t *pgd; |
415 | pmd_t *pmd; | |
416 | pte_t *pte; | |
ab6494f0 | 417 | int i = 0; |
37134cd5 | 418 | u32 base = CONSISTENT_BASE; |
1da177e4 | 419 | |
1da177e4 | 420 | do { |
37134cd5 KH |
421 | pgd = pgd_offset(&init_mm, base); |
422 | pmd = pmd_alloc(&init_mm, pgd, base); | |
1da177e4 LT |
423 | if (!pmd) { |
424 | printk(KERN_ERR "%s: no pmd tables\n", __func__); | |
425 | ret = -ENOMEM; | |
426 | break; | |
427 | } | |
428 | WARN_ON(!pmd_none(*pmd)); | |
429 | ||
37134cd5 | 430 | pte = pte_alloc_kernel(pmd, base); |
1da177e4 LT |
431 | if (!pte) { |
432 | printk(KERN_ERR "%s: no pte tables\n", __func__); | |
433 | ret = -ENOMEM; | |
434 | break; | |
435 | } | |
436 | ||
37134cd5 KH |
437 | consistent_pte[i++] = pte; |
438 | base += (1 << PGDIR_SHIFT); | |
439 | } while (base < CONSISTENT_END); | |
ab6494f0 | 440 | #endif /* !CONFIG_MMU */ |
1da177e4 | 441 | |
1da177e4 LT |
442 | return ret; |
443 | } | |
444 | ||
445 | core_initcall(consistent_init); | |
446 | ||
447 | /* | |
448 | * Make an area consistent for devices. | |
105ef9a0 DW |
449 | * Note: Drivers should NOT use this function directly, as it will break |
450 | * platforms with CONFIG_DMABOUNCE. | |
451 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
1da177e4 | 452 | */ |
84aa462e | 453 | void dma_cache_maint(const void *start, size_t size, int direction) |
1da177e4 | 454 | { |
1522ac3e RK |
455 | void (*inner_op)(const void *, const void *); |
456 | void (*outer_op)(unsigned long, unsigned long); | |
1da177e4 | 457 | |
1522ac3e | 458 | BUG_ON(!virt_addr_valid(start) || !virt_addr_valid(start + size - 1)); |
953233dc | 459 | |
1da177e4 LT |
460 | switch (direction) { |
461 | case DMA_FROM_DEVICE: /* invalidate only */ | |
1522ac3e RK |
462 | inner_op = dmac_inv_range; |
463 | outer_op = outer_inv_range; | |
1da177e4 LT |
464 | break; |
465 | case DMA_TO_DEVICE: /* writeback only */ | |
1522ac3e RK |
466 | inner_op = dmac_clean_range; |
467 | outer_op = outer_clean_range; | |
1da177e4 LT |
468 | break; |
469 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | |
1522ac3e RK |
470 | inner_op = dmac_flush_range; |
471 | outer_op = outer_flush_range; | |
1da177e4 LT |
472 | break; |
473 | default: | |
474 | BUG(); | |
475 | } | |
1522ac3e RK |
476 | |
477 | inner_op(start, start + size); | |
478 | outer_op(__pa(start), __pa(start) + size); | |
1da177e4 | 479 | } |
84aa462e | 480 | EXPORT_SYMBOL(dma_cache_maint); |
afd1a321 | 481 | |
43377453 NP |
482 | static void dma_cache_maint_contiguous(struct page *page, unsigned long offset, |
483 | size_t size, int direction) | |
484 | { | |
485 | void *vaddr; | |
486 | unsigned long paddr; | |
487 | void (*inner_op)(const void *, const void *); | |
488 | void (*outer_op)(unsigned long, unsigned long); | |
489 | ||
490 | switch (direction) { | |
491 | case DMA_FROM_DEVICE: /* invalidate only */ | |
492 | inner_op = dmac_inv_range; | |
493 | outer_op = outer_inv_range; | |
494 | break; | |
495 | case DMA_TO_DEVICE: /* writeback only */ | |
496 | inner_op = dmac_clean_range; | |
497 | outer_op = outer_clean_range; | |
498 | break; | |
499 | case DMA_BIDIRECTIONAL: /* writeback and invalidate */ | |
500 | inner_op = dmac_flush_range; | |
501 | outer_op = outer_flush_range; | |
502 | break; | |
503 | default: | |
504 | BUG(); | |
505 | } | |
506 | ||
507 | if (!PageHighMem(page)) { | |
508 | vaddr = page_address(page) + offset; | |
509 | inner_op(vaddr, vaddr + size); | |
510 | } else { | |
511 | vaddr = kmap_high_get(page); | |
512 | if (vaddr) { | |
513 | vaddr += offset; | |
514 | inner_op(vaddr, vaddr + size); | |
515 | kunmap_high(page); | |
516 | } | |
517 | } | |
518 | ||
519 | paddr = page_to_phys(page) + offset; | |
520 | outer_op(paddr, paddr + size); | |
521 | } | |
522 | ||
523 | void dma_cache_maint_page(struct page *page, unsigned long offset, | |
524 | size_t size, int dir) | |
525 | { | |
526 | /* | |
527 | * A single sg entry may refer to multiple physically contiguous | |
528 | * pages. But we still need to process highmem pages individually. | |
529 | * If highmem is not configured then the bulk of this loop gets | |
530 | * optimized out. | |
531 | */ | |
532 | size_t left = size; | |
533 | do { | |
534 | size_t len = left; | |
535 | if (PageHighMem(page) && len + offset > PAGE_SIZE) { | |
536 | if (offset >= PAGE_SIZE) { | |
537 | page += offset / PAGE_SIZE; | |
538 | offset %= PAGE_SIZE; | |
539 | } | |
540 | len = PAGE_SIZE - offset; | |
541 | } | |
542 | dma_cache_maint_contiguous(page, offset, len, dir); | |
543 | offset = 0; | |
544 | page++; | |
545 | left -= len; | |
546 | } while (left); | |
547 | } | |
548 | EXPORT_SYMBOL(dma_cache_maint_page); | |
549 | ||
afd1a321 RK |
550 | /** |
551 | * dma_map_sg - map a set of SG buffers for streaming mode DMA | |
552 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
553 | * @sg: list of buffers | |
554 | * @nents: number of buffers to map | |
555 | * @dir: DMA transfer direction | |
556 | * | |
557 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
558 | * This is the scatter-gather version of the dma_map_single interface. | |
559 | * Here the scatter gather list elements are each tagged with the | |
560 | * appropriate dma address and length. They are obtained via | |
561 | * sg_dma_{address,length}. | |
562 | * | |
563 | * Device ownership issues as mentioned for dma_map_single are the same | |
564 | * here. | |
565 | */ | |
566 | int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
567 | enum dma_data_direction dir) | |
568 | { | |
569 | struct scatterlist *s; | |
01135d92 | 570 | int i, j; |
afd1a321 RK |
571 | |
572 | for_each_sg(sg, s, nents, i) { | |
01135d92 RK |
573 | s->dma_address = dma_map_page(dev, sg_page(s), s->offset, |
574 | s->length, dir); | |
575 | if (dma_mapping_error(dev, s->dma_address)) | |
576 | goto bad_mapping; | |
afd1a321 | 577 | } |
afd1a321 | 578 | return nents; |
01135d92 RK |
579 | |
580 | bad_mapping: | |
581 | for_each_sg(sg, s, i, j) | |
582 | dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); | |
583 | return 0; | |
afd1a321 RK |
584 | } |
585 | EXPORT_SYMBOL(dma_map_sg); | |
586 | ||
587 | /** | |
588 | * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
589 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
590 | * @sg: list of buffers | |
591 | * @nents: number of buffers to unmap (returned from dma_map_sg) | |
592 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
593 | * | |
594 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
595 | * rules concerning calls here are the same as for dma_unmap_single(). | |
596 | */ | |
597 | void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
598 | enum dma_data_direction dir) | |
599 | { | |
01135d92 RK |
600 | struct scatterlist *s; |
601 | int i; | |
602 | ||
603 | for_each_sg(sg, s, nents, i) | |
604 | dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); | |
afd1a321 RK |
605 | } |
606 | EXPORT_SYMBOL(dma_unmap_sg); | |
607 | ||
608 | /** | |
609 | * dma_sync_sg_for_cpu | |
610 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
611 | * @sg: list of buffers | |
612 | * @nents: number of buffers to map (returned from dma_map_sg) | |
613 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
614 | */ | |
615 | void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
616 | int nents, enum dma_data_direction dir) | |
617 | { | |
618 | struct scatterlist *s; | |
619 | int i; | |
620 | ||
621 | for_each_sg(sg, s, nents, i) { | |
309dbbab RK |
622 | dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0, |
623 | sg_dma_len(s), dir); | |
afd1a321 RK |
624 | } |
625 | } | |
626 | EXPORT_SYMBOL(dma_sync_sg_for_cpu); | |
627 | ||
628 | /** | |
629 | * dma_sync_sg_for_device | |
630 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
631 | * @sg: list of buffers | |
632 | * @nents: number of buffers to map (returned from dma_map_sg) | |
633 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
634 | */ | |
635 | void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
636 | int nents, enum dma_data_direction dir) | |
637 | { | |
638 | struct scatterlist *s; | |
639 | int i; | |
640 | ||
641 | for_each_sg(sg, s, nents, i) { | |
2638b4db RK |
642 | if (!dmabounce_sync_for_device(dev, sg_dma_address(s), 0, |
643 | sg_dma_len(s), dir)) | |
644 | continue; | |
645 | ||
afd1a321 | 646 | if (!arch_is_coherent()) |
43377453 NP |
647 | dma_cache_maint_page(sg_page(s), s->offset, |
648 | s->length, dir); | |
afd1a321 RK |
649 | } |
650 | } | |
651 | EXPORT_SYMBOL(dma_sync_sg_for_device); |