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Commit | Line | Data |
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1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
1da177e4 LT |
15 | #include <linux/errno.h> |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
39af22a7 | 20 | #include <linux/highmem.h> |
99d1717d | 21 | #include <linux/slab.h> |
1da177e4 | 22 | |
23759dc6 | 23 | #include <asm/memory.h> |
43377453 | 24 | #include <asm/highmem.h> |
1da177e4 | 25 | #include <asm/cacheflush.h> |
1da177e4 | 26 | #include <asm/tlbflush.h> |
37134cd5 | 27 | #include <asm/sizes.h> |
99d1717d | 28 | #include <asm/mach/arch.h> |
37134cd5 | 29 | |
022ae537 RK |
30 | #include "mm.h" |
31 | ||
15237e1f MS |
32 | /* |
33 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
34 | * is either exclusively owned by the CPU (and therefore may be accessed | |
35 | * by it) or exclusively owned by the DMA device. These helper functions | |
36 | * represent the transitions between these two ownership states. | |
37 | * | |
38 | * Note, however, that on later ARMs, this notion does not work due to | |
39 | * speculative prefetches. We model our approach on the assumption that | |
40 | * the CPU does do speculative prefetches, which means we clean caches | |
41 | * before transfers and delay cache invalidation until transfer completion. | |
42 | * | |
43 | * Private support functions: these are not part of the API and are | |
44 | * liable to change. Drivers must not use these. | |
45 | */ | |
46 | static inline void __dma_single_cpu_to_dev(const void *kaddr, size_t size, | |
47 | enum dma_data_direction dir) | |
48 | { | |
49 | extern void ___dma_single_cpu_to_dev(const void *, size_t, | |
50 | enum dma_data_direction); | |
51 | ||
52 | if (!arch_is_coherent()) | |
53 | ___dma_single_cpu_to_dev(kaddr, size, dir); | |
54 | } | |
55 | ||
56 | static inline void __dma_single_dev_to_cpu(const void *kaddr, size_t size, | |
57 | enum dma_data_direction dir) | |
58 | { | |
59 | extern void ___dma_single_dev_to_cpu(const void *, size_t, | |
60 | enum dma_data_direction); | |
61 | ||
62 | if (!arch_is_coherent()) | |
63 | ___dma_single_dev_to_cpu(kaddr, size, dir); | |
64 | } | |
65 | ||
66 | static inline void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
67 | size_t size, enum dma_data_direction dir) | |
68 | { | |
69 | extern void ___dma_page_cpu_to_dev(struct page *, unsigned long, | |
70 | size_t, enum dma_data_direction); | |
71 | ||
72 | if (!arch_is_coherent()) | |
73 | ___dma_page_cpu_to_dev(page, off, size, dir); | |
74 | } | |
75 | ||
76 | static inline void __dma_page_dev_to_cpu(struct page *page, unsigned long off, | |
77 | size_t size, enum dma_data_direction dir) | |
78 | { | |
79 | extern void ___dma_page_dev_to_cpu(struct page *, unsigned long, | |
80 | size_t, enum dma_data_direction); | |
81 | ||
82 | if (!arch_is_coherent()) | |
83 | ___dma_page_dev_to_cpu(page, off, size, dir); | |
84 | } | |
85 | ||
86 | ||
87 | static inline dma_addr_t __dma_map_page(struct device *dev, struct page *page, | |
88 | unsigned long offset, size_t size, enum dma_data_direction dir) | |
89 | { | |
90 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
91 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
92 | } | |
93 | ||
94 | static inline void __dma_unmap_page(struct device *dev, dma_addr_t handle, | |
95 | size_t size, enum dma_data_direction dir) | |
96 | { | |
97 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), | |
98 | handle & ~PAGE_MASK, size, dir); | |
99 | } | |
100 | ||
2dc6a016 MS |
101 | /** |
102 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
103 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
104 | * @page: page that buffer resides in | |
105 | * @offset: offset into page for start of buffer | |
106 | * @size: size of buffer to map | |
107 | * @dir: DMA transfer direction | |
108 | * | |
109 | * Ensure that any data held in the cache is appropriately discarded | |
110 | * or written back. | |
111 | * | |
112 | * The device owns this memory once this call has completed. The CPU | |
113 | * can regain ownership by calling dma_unmap_page(). | |
114 | */ | |
115 | static inline dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, | |
116 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
117 | struct dma_attrs *attrs) | |
118 | { | |
119 | return __dma_map_page(dev, page, offset, size, dir); | |
120 | } | |
121 | ||
122 | /** | |
123 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
124 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
125 | * @handle: DMA address of buffer | |
126 | * @size: size of buffer (same as passed to dma_map_page) | |
127 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
128 | * | |
129 | * Unmap a page streaming mode DMA translation. The handle and size | |
130 | * must match what was provided in the previous dma_map_page() call. | |
131 | * All other usages are undefined. | |
132 | * | |
133 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
134 | * whatever the device wrote there. | |
135 | */ | |
136 | static inline void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, | |
137 | size_t size, enum dma_data_direction dir, | |
138 | struct dma_attrs *attrs) | |
139 | { | |
140 | __dma_unmap_page(dev, handle, size, dir); | |
141 | } | |
142 | ||
143 | static inline void arm_dma_sync_single_for_cpu(struct device *dev, | |
144 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
145 | { | |
146 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
147 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
2dc6a016 MS |
148 | __dma_page_dev_to_cpu(page, offset, size, dir); |
149 | } | |
150 | ||
151 | static inline void arm_dma_sync_single_for_device(struct device *dev, | |
152 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
153 | { | |
154 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
155 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
2dc6a016 MS |
156 | __dma_page_cpu_to_dev(page, offset, size, dir); |
157 | } | |
158 | ||
159 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask); | |
160 | ||
161 | struct dma_map_ops arm_dma_ops = { | |
162 | .map_page = arm_dma_map_page, | |
163 | .unmap_page = arm_dma_unmap_page, | |
164 | .map_sg = arm_dma_map_sg, | |
165 | .unmap_sg = arm_dma_unmap_sg, | |
166 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
167 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
168 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
169 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
170 | .set_dma_mask = arm_dma_set_mask, | |
171 | }; | |
172 | EXPORT_SYMBOL(arm_dma_ops); | |
173 | ||
ab6494f0 CM |
174 | static u64 get_coherent_dma_mask(struct device *dev) |
175 | { | |
022ae537 | 176 | u64 mask = (u64)arm_dma_limit; |
ab6494f0 CM |
177 | |
178 | if (dev) { | |
179 | mask = dev->coherent_dma_mask; | |
180 | ||
181 | /* | |
182 | * Sanity check the DMA mask - it must be non-zero, and | |
183 | * must be able to be satisfied by a DMA allocation. | |
184 | */ | |
185 | if (mask == 0) { | |
186 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
187 | return 0; | |
188 | } | |
189 | ||
022ae537 | 190 | if ((~mask) & (u64)arm_dma_limit) { |
ab6494f0 CM |
191 | dev_warn(dev, "coherent DMA mask %#llx is smaller " |
192 | "than system GFP_DMA mask %#llx\n", | |
022ae537 | 193 | mask, (u64)arm_dma_limit); |
ab6494f0 CM |
194 | return 0; |
195 | } | |
196 | } | |
1da177e4 | 197 | |
ab6494f0 CM |
198 | return mask; |
199 | } | |
200 | ||
7a9a32a9 RK |
201 | /* |
202 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
203 | * specified gfp mask. Note that 'size' must be page aligned. | |
204 | */ | |
205 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
206 | { | |
207 | unsigned long order = get_order(size); | |
208 | struct page *page, *p, *e; | |
209 | void *ptr; | |
210 | u64 mask = get_coherent_dma_mask(dev); | |
211 | ||
212 | #ifdef CONFIG_DMA_API_DEBUG | |
213 | u64 limit = (mask + 1) & ~mask; | |
214 | if (limit && size >= limit) { | |
215 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
216 | size, mask); | |
217 | return NULL; | |
218 | } | |
219 | #endif | |
220 | ||
221 | if (!mask) | |
222 | return NULL; | |
223 | ||
224 | if (mask < 0xffffffffULL) | |
225 | gfp |= GFP_DMA; | |
226 | ||
227 | page = alloc_pages(gfp, order); | |
228 | if (!page) | |
229 | return NULL; | |
230 | ||
231 | /* | |
232 | * Now split the huge page and free the excess pages | |
233 | */ | |
234 | split_page(page, order); | |
235 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
236 | __free_page(p); | |
237 | ||
238 | /* | |
239 | * Ensure that the allocated pages are zeroed, and that any data | |
240 | * lurking in the kernel direct-mapped region is invalidated. | |
241 | */ | |
242 | ptr = page_address(page); | |
243 | memset(ptr, 0, size); | |
244 | dmac_flush_range(ptr, ptr + size); | |
245 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
246 | ||
247 | return page; | |
248 | } | |
249 | ||
250 | /* | |
251 | * Free a DMA buffer. 'size' must be page aligned. | |
252 | */ | |
253 | static void __dma_free_buffer(struct page *page, size_t size) | |
254 | { | |
255 | struct page *e = page + (size >> PAGE_SHIFT); | |
256 | ||
257 | while (page < e) { | |
258 | __free_page(page); | |
259 | page++; | |
260 | } | |
261 | } | |
262 | ||
ab6494f0 | 263 | #ifdef CONFIG_MMU |
a5e9d38b | 264 | |
99d1717d | 265 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT) |
1fdb24e9 | 266 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PMD_SHIFT) |
a5e9d38b | 267 | |
1da177e4 | 268 | /* |
37134cd5 | 269 | * These are the page tables (2MB each) covering uncached, DMA consistent allocations |
1da177e4 | 270 | */ |
99d1717d JM |
271 | static pte_t **consistent_pte; |
272 | ||
99d1717d | 273 | #define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M |
99d1717d JM |
274 | |
275 | unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE; | |
276 | ||
277 | void __init init_consistent_dma_size(unsigned long size) | |
278 | { | |
279 | unsigned long base = CONSISTENT_END - ALIGN(size, SZ_2M); | |
280 | ||
281 | BUG_ON(consistent_pte); /* Check we're called before DMA region init */ | |
282 | BUG_ON(base < VMALLOC_END); | |
283 | ||
284 | /* Grow region to accommodate specified size */ | |
285 | if (base < consistent_base) | |
286 | consistent_base = base; | |
287 | } | |
1da177e4 | 288 | |
13ccf3ad | 289 | #include "vmregion.h" |
1da177e4 | 290 | |
13ccf3ad RK |
291 | static struct arm_vmregion_head consistent_head = { |
292 | .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock), | |
1da177e4 | 293 | .vm_list = LIST_HEAD_INIT(consistent_head.vm_list), |
1da177e4 LT |
294 | .vm_end = CONSISTENT_END, |
295 | }; | |
296 | ||
1da177e4 LT |
297 | #ifdef CONFIG_HUGETLB_PAGE |
298 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
299 | #endif | |
300 | ||
88c58f3b RK |
301 | /* |
302 | * Initialise the consistent memory allocation. | |
303 | */ | |
304 | static int __init consistent_init(void) | |
305 | { | |
306 | int ret = 0; | |
307 | pgd_t *pgd; | |
516295e5 | 308 | pud_t *pud; |
88c58f3b RK |
309 | pmd_t *pmd; |
310 | pte_t *pte; | |
311 | int i = 0; | |
99d1717d | 312 | unsigned long base = consistent_base; |
53cbcbcf | 313 | unsigned long num_ptes = (CONSISTENT_END - base) >> PMD_SHIFT; |
99d1717d JM |
314 | |
315 | consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL); | |
316 | if (!consistent_pte) { | |
317 | pr_err("%s: no memory\n", __func__); | |
318 | return -ENOMEM; | |
319 | } | |
320 | ||
321 | pr_debug("DMA memory: 0x%08lx - 0x%08lx:\n", base, CONSISTENT_END); | |
322 | consistent_head.vm_start = base; | |
88c58f3b RK |
323 | |
324 | do { | |
325 | pgd = pgd_offset(&init_mm, base); | |
516295e5 RK |
326 | |
327 | pud = pud_alloc(&init_mm, pgd, base); | |
328 | if (!pud) { | |
6b6f770b | 329 | pr_err("%s: no pud tables\n", __func__); |
516295e5 RK |
330 | ret = -ENOMEM; |
331 | break; | |
332 | } | |
333 | ||
334 | pmd = pmd_alloc(&init_mm, pud, base); | |
88c58f3b | 335 | if (!pmd) { |
6b6f770b | 336 | pr_err("%s: no pmd tables\n", __func__); |
88c58f3b RK |
337 | ret = -ENOMEM; |
338 | break; | |
339 | } | |
340 | WARN_ON(!pmd_none(*pmd)); | |
341 | ||
342 | pte = pte_alloc_kernel(pmd, base); | |
343 | if (!pte) { | |
6b6f770b | 344 | pr_err("%s: no pte tables\n", __func__); |
88c58f3b RK |
345 | ret = -ENOMEM; |
346 | break; | |
347 | } | |
348 | ||
349 | consistent_pte[i++] = pte; | |
e73fc88e | 350 | base += PMD_SIZE; |
88c58f3b RK |
351 | } while (base < CONSISTENT_END); |
352 | ||
353 | return ret; | |
354 | } | |
355 | ||
356 | core_initcall(consistent_init); | |
357 | ||
1da177e4 | 358 | static void * |
45cd5290 RK |
359 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, |
360 | const void *caller) | |
1da177e4 | 361 | { |
13ccf3ad | 362 | struct arm_vmregion *c; |
5bc23d32 RK |
363 | size_t align; |
364 | int bit; | |
1da177e4 | 365 | |
99d1717d | 366 | if (!consistent_pte) { |
6b6f770b | 367 | pr_err("%s: not initialised\n", __func__); |
ebd7a845 | 368 | dump_stack(); |
ebd7a845 RK |
369 | return NULL; |
370 | } | |
371 | ||
5bc23d32 RK |
372 | /* |
373 | * Align the virtual region allocation - maximum alignment is | |
374 | * a section size, minimum is a page size. This helps reduce | |
375 | * fragmentation of the DMA space, and also prevents allocations | |
376 | * smaller than a section from crossing a section boundary. | |
377 | */ | |
c947f69f | 378 | bit = fls(size - 1); |
5bc23d32 RK |
379 | if (bit > SECTION_SHIFT) |
380 | bit = SECTION_SHIFT; | |
381 | align = 1 << bit; | |
382 | ||
1da177e4 LT |
383 | /* |
384 | * Allocate a virtual address in the consistent mapping region. | |
385 | */ | |
5bc23d32 | 386 | c = arm_vmregion_alloc(&consistent_head, align, size, |
45cd5290 | 387 | gfp & ~(__GFP_DMA | __GFP_HIGHMEM), caller); |
1da177e4 | 388 | if (c) { |
37134cd5 | 389 | pte_t *pte; |
37134cd5 KH |
390 | int idx = CONSISTENT_PTE_INDEX(c->vm_start); |
391 | u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
1da177e4 | 392 | |
37134cd5 | 393 | pte = consistent_pte[idx] + off; |
1da177e4 LT |
394 | c->vm_pages = page; |
395 | ||
1da177e4 LT |
396 | do { |
397 | BUG_ON(!pte_none(*pte)); | |
398 | ||
ad1ae2fe | 399 | set_pte_ext(pte, mk_pte(page, prot), 0); |
1da177e4 LT |
400 | page++; |
401 | pte++; | |
37134cd5 KH |
402 | off++; |
403 | if (off >= PTRS_PER_PTE) { | |
404 | off = 0; | |
405 | pte = consistent_pte[++idx]; | |
406 | } | |
1da177e4 LT |
407 | } while (size -= PAGE_SIZE); |
408 | ||
2be23c47 RK |
409 | dsb(); |
410 | ||
1da177e4 LT |
411 | return (void *)c->vm_start; |
412 | } | |
1da177e4 LT |
413 | return NULL; |
414 | } | |
695ae0af RK |
415 | |
416 | static void __dma_free_remap(void *cpu_addr, size_t size) | |
417 | { | |
418 | struct arm_vmregion *c; | |
419 | unsigned long addr; | |
420 | pte_t *ptep; | |
421 | int idx; | |
422 | u32 off; | |
423 | ||
424 | c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr); | |
425 | if (!c) { | |
6b6f770b | 426 | pr_err("%s: trying to free invalid coherent area: %p\n", |
695ae0af RK |
427 | __func__, cpu_addr); |
428 | dump_stack(); | |
429 | return; | |
430 | } | |
431 | ||
432 | if ((c->vm_end - c->vm_start) != size) { | |
6b6f770b | 433 | pr_err("%s: freeing wrong coherent size (%ld != %d)\n", |
695ae0af RK |
434 | __func__, c->vm_end - c->vm_start, size); |
435 | dump_stack(); | |
436 | size = c->vm_end - c->vm_start; | |
437 | } | |
438 | ||
439 | idx = CONSISTENT_PTE_INDEX(c->vm_start); | |
440 | off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
441 | ptep = consistent_pte[idx] + off; | |
442 | addr = c->vm_start; | |
443 | do { | |
444 | pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep); | |
695ae0af RK |
445 | |
446 | ptep++; | |
447 | addr += PAGE_SIZE; | |
448 | off++; | |
449 | if (off >= PTRS_PER_PTE) { | |
450 | off = 0; | |
451 | ptep = consistent_pte[++idx]; | |
452 | } | |
453 | ||
acaac256 | 454 | if (pte_none(pte) || !pte_present(pte)) |
6b6f770b MS |
455 | pr_crit("%s: bad page in kernel page table\n", |
456 | __func__); | |
695ae0af RK |
457 | } while (size -= PAGE_SIZE); |
458 | ||
459 | flush_tlb_kernel_range(c->vm_start, c->vm_end); | |
460 | ||
461 | arm_vmregion_free(&consistent_head, c); | |
462 | } | |
463 | ||
ab6494f0 | 464 | #else /* !CONFIG_MMU */ |
695ae0af | 465 | |
45cd5290 | 466 | #define __dma_alloc_remap(page, size, gfp, prot, c) page_address(page) |
31ebf944 RK |
467 | #define __dma_free_remap(addr, size) do { } while (0) |
468 | ||
469 | #endif /* CONFIG_MMU */ | |
470 | ||
ab6494f0 CM |
471 | static void * |
472 | __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, | |
45cd5290 | 473 | pgprot_t prot, const void *caller) |
ab6494f0 | 474 | { |
04da5694 | 475 | struct page *page; |
31ebf944 | 476 | void *addr; |
ab6494f0 | 477 | |
ea2e7057 SB |
478 | /* |
479 | * Following is a work-around (a.k.a. hack) to prevent pages | |
480 | * with __GFP_COMP being passed to split_page() which cannot | |
481 | * handle them. The real problem is that this flag probably | |
482 | * should be 0 on ARM as it is not supported on this | |
483 | * platform; see CONFIG_HUGETLBFS. | |
484 | */ | |
485 | gfp &= ~(__GFP_COMP); | |
486 | ||
553ac788 | 487 | *handle = DMA_ERROR_CODE; |
04da5694 | 488 | size = PAGE_ALIGN(size); |
ab6494f0 | 489 | |
04da5694 RK |
490 | page = __dma_alloc_buffer(dev, size, gfp); |
491 | if (!page) | |
492 | return NULL; | |
ab6494f0 | 493 | |
31ebf944 | 494 | if (!arch_is_coherent()) |
45cd5290 | 495 | addr = __dma_alloc_remap(page, size, gfp, prot, caller); |
31ebf944 RK |
496 | else |
497 | addr = page_address(page); | |
695ae0af | 498 | |
31ebf944 | 499 | if (addr) |
9eedd963 | 500 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
d8e89b47 RK |
501 | else |
502 | __dma_free_buffer(page, size); | |
695ae0af | 503 | |
31ebf944 RK |
504 | return addr; |
505 | } | |
1da177e4 LT |
506 | |
507 | /* | |
508 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
509 | * virtual and bus address for that space. | |
510 | */ | |
511 | void * | |
f9e3214a | 512 | dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 | 513 | { |
1fe53268 DES |
514 | void *memory; |
515 | ||
516 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
517 | return memory; | |
518 | ||
1da177e4 | 519 | return __dma_alloc(dev, size, handle, gfp, |
45cd5290 RK |
520 | pgprot_dmacoherent(pgprot_kernel), |
521 | __builtin_return_address(0)); | |
1da177e4 LT |
522 | } |
523 | EXPORT_SYMBOL(dma_alloc_coherent); | |
524 | ||
525 | /* | |
526 | * Allocate a writecombining region, in much the same way as | |
527 | * dma_alloc_coherent above. | |
528 | */ | |
529 | void * | |
f9e3214a | 530 | dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 LT |
531 | { |
532 | return __dma_alloc(dev, size, handle, gfp, | |
45cd5290 RK |
533 | pgprot_writecombine(pgprot_kernel), |
534 | __builtin_return_address(0)); | |
1da177e4 LT |
535 | } |
536 | EXPORT_SYMBOL(dma_alloc_writecombine); | |
537 | ||
538 | static int dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
539 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
540 | { | |
ab6494f0 CM |
541 | int ret = -ENXIO; |
542 | #ifdef CONFIG_MMU | |
13ccf3ad RK |
543 | unsigned long user_size, kern_size; |
544 | struct arm_vmregion *c; | |
1da177e4 | 545 | |
47142f07 MS |
546 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
547 | return ret; | |
548 | ||
1da177e4 LT |
549 | user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
550 | ||
13ccf3ad | 551 | c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr); |
1da177e4 LT |
552 | if (c) { |
553 | unsigned long off = vma->vm_pgoff; | |
554 | ||
555 | kern_size = (c->vm_end - c->vm_start) >> PAGE_SHIFT; | |
556 | ||
557 | if (off < kern_size && | |
558 | user_size <= (kern_size - off)) { | |
1da177e4 LT |
559 | ret = remap_pfn_range(vma, vma->vm_start, |
560 | page_to_pfn(c->vm_pages) + off, | |
561 | user_size << PAGE_SHIFT, | |
562 | vma->vm_page_prot); | |
563 | } | |
564 | } | |
ab6494f0 | 565 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
566 | |
567 | return ret; | |
568 | } | |
569 | ||
570 | int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, | |
571 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
572 | { | |
26a26d32 | 573 | vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot); |
1da177e4 LT |
574 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); |
575 | } | |
576 | EXPORT_SYMBOL(dma_mmap_coherent); | |
577 | ||
578 | int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma, | |
579 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
580 | { | |
581 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
582 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); | |
583 | } | |
584 | EXPORT_SYMBOL(dma_mmap_writecombine); | |
585 | ||
586 | /* | |
587 | * free a page as defined by the above mapping. | |
5edf71ae | 588 | * Must not be called with IRQs disabled. |
1da177e4 LT |
589 | */ |
590 | void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle) | |
591 | { | |
5edf71ae RK |
592 | WARN_ON(irqs_disabled()); |
593 | ||
1fe53268 DES |
594 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
595 | return; | |
596 | ||
3e82d012 RK |
597 | size = PAGE_ALIGN(size); |
598 | ||
695ae0af RK |
599 | if (!arch_is_coherent()) |
600 | __dma_free_remap(cpu_addr, size); | |
7a9a32a9 | 601 | |
9eedd963 | 602 | __dma_free_buffer(pfn_to_page(dma_to_pfn(dev, handle)), size); |
1da177e4 LT |
603 | } |
604 | EXPORT_SYMBOL(dma_free_coherent); | |
605 | ||
4ea0d737 | 606 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
607 | size_t size, enum dma_data_direction dir, |
608 | void (*op)(const void *, size_t, int)) | |
43377453 NP |
609 | { |
610 | /* | |
611 | * A single sg entry may refer to multiple physically contiguous | |
612 | * pages. But we still need to process highmem pages individually. | |
613 | * If highmem is not configured then the bulk of this loop gets | |
614 | * optimized out. | |
615 | */ | |
616 | size_t left = size; | |
617 | do { | |
618 | size_t len = left; | |
93f1d629 RK |
619 | void *vaddr; |
620 | ||
621 | if (PageHighMem(page)) { | |
622 | if (len + offset > PAGE_SIZE) { | |
623 | if (offset >= PAGE_SIZE) { | |
624 | page += offset / PAGE_SIZE; | |
625 | offset %= PAGE_SIZE; | |
626 | } | |
627 | len = PAGE_SIZE - offset; | |
628 | } | |
629 | vaddr = kmap_high_get(page); | |
630 | if (vaddr) { | |
631 | vaddr += offset; | |
a9c9147e | 632 | op(vaddr, len, dir); |
93f1d629 | 633 | kunmap_high(page); |
7e5a69e8 | 634 | } else if (cache_is_vipt()) { |
39af22a7 NP |
635 | /* unmapped pages might still be cached */ |
636 | vaddr = kmap_atomic(page); | |
7e5a69e8 | 637 | op(vaddr + offset, len, dir); |
39af22a7 | 638 | kunmap_atomic(vaddr); |
43377453 | 639 | } |
93f1d629 RK |
640 | } else { |
641 | vaddr = page_address(page) + offset; | |
a9c9147e | 642 | op(vaddr, len, dir); |
43377453 | 643 | } |
43377453 NP |
644 | offset = 0; |
645 | page++; | |
646 | left -= len; | |
647 | } while (left); | |
648 | } | |
4ea0d737 RK |
649 | |
650 | void ___dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
651 | size_t size, enum dma_data_direction dir) | |
652 | { | |
65af191a | 653 | unsigned long paddr; |
65af191a | 654 | |
a9c9147e | 655 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
656 | |
657 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
658 | if (dir == DMA_FROM_DEVICE) { |
659 | outer_inv_range(paddr, paddr + size); | |
660 | } else { | |
661 | outer_clean_range(paddr, paddr + size); | |
662 | } | |
663 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 664 | } |
4ea0d737 RK |
665 | |
666 | void ___dma_page_dev_to_cpu(struct page *page, unsigned long off, | |
667 | size_t size, enum dma_data_direction dir) | |
668 | { | |
2ffe2da3 RK |
669 | unsigned long paddr = page_to_phys(page) + off; |
670 | ||
671 | /* FIXME: non-speculating: not required */ | |
672 | /* don't bother invalidating if DMA to device */ | |
673 | if (dir != DMA_TO_DEVICE) | |
674 | outer_inv_range(paddr, paddr + size); | |
675 | ||
a9c9147e | 676 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
c0177800 CM |
677 | |
678 | /* | |
679 | * Mark the D-cache clean for this page to avoid extra flushing. | |
680 | */ | |
681 | if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE) | |
682 | set_bit(PG_dcache_clean, &page->flags); | |
4ea0d737 | 683 | } |
43377453 | 684 | |
afd1a321 | 685 | /** |
2a550e73 | 686 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
687 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
688 | * @sg: list of buffers | |
689 | * @nents: number of buffers to map | |
690 | * @dir: DMA transfer direction | |
691 | * | |
692 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
693 | * This is the scatter-gather version of the dma_map_single interface. | |
694 | * Here the scatter gather list elements are each tagged with the | |
695 | * appropriate dma address and length. They are obtained via | |
696 | * sg_dma_{address,length}. | |
697 | * | |
698 | * Device ownership issues as mentioned for dma_map_single are the same | |
699 | * here. | |
700 | */ | |
2dc6a016 MS |
701 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
702 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 703 | { |
2a550e73 | 704 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 705 | struct scatterlist *s; |
01135d92 | 706 | int i, j; |
afd1a321 RK |
707 | |
708 | for_each_sg(sg, s, nents, i) { | |
2a550e73 MS |
709 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
710 | s->length, dir, attrs); | |
01135d92 RK |
711 | if (dma_mapping_error(dev, s->dma_address)) |
712 | goto bad_mapping; | |
afd1a321 | 713 | } |
afd1a321 | 714 | return nents; |
01135d92 RK |
715 | |
716 | bad_mapping: | |
717 | for_each_sg(sg, s, i, j) | |
2a550e73 | 718 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 719 | return 0; |
afd1a321 | 720 | } |
afd1a321 RK |
721 | |
722 | /** | |
2a550e73 | 723 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
724 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
725 | * @sg: list of buffers | |
0adfca6f | 726 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
727 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
728 | * | |
729 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
730 | * rules concerning calls here are the same as for dma_unmap_single(). | |
731 | */ | |
2dc6a016 MS |
732 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
733 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 734 | { |
2a550e73 | 735 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 736 | struct scatterlist *s; |
2a550e73 | 737 | |
01135d92 RK |
738 | int i; |
739 | ||
740 | for_each_sg(sg, s, nents, i) | |
2a550e73 | 741 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 742 | } |
afd1a321 RK |
743 | |
744 | /** | |
2a550e73 | 745 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
746 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
747 | * @sg: list of buffers | |
748 | * @nents: number of buffers to map (returned from dma_map_sg) | |
749 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
750 | */ | |
2dc6a016 | 751 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
752 | int nents, enum dma_data_direction dir) |
753 | { | |
2a550e73 | 754 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
755 | struct scatterlist *s; |
756 | int i; | |
757 | ||
2a550e73 MS |
758 | for_each_sg(sg, s, nents, i) |
759 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
760 | dir); | |
afd1a321 | 761 | } |
afd1a321 RK |
762 | |
763 | /** | |
2a550e73 | 764 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
765 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
766 | * @sg: list of buffers | |
767 | * @nents: number of buffers to map (returned from dma_map_sg) | |
768 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
769 | */ | |
2dc6a016 | 770 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
771 | int nents, enum dma_data_direction dir) |
772 | { | |
2a550e73 | 773 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
774 | struct scatterlist *s; |
775 | int i; | |
776 | ||
2a550e73 MS |
777 | for_each_sg(sg, s, nents, i) |
778 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
779 | dir); | |
afd1a321 | 780 | } |
24056f52 | 781 | |
022ae537 RK |
782 | /* |
783 | * Return whether the given device DMA address mask can be supported | |
784 | * properly. For example, if your device can only drive the low 24-bits | |
785 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
786 | * to this function. | |
787 | */ | |
788 | int dma_supported(struct device *dev, u64 mask) | |
789 | { | |
790 | if (mask < (u64)arm_dma_limit) | |
791 | return 0; | |
792 | return 1; | |
793 | } | |
794 | EXPORT_SYMBOL(dma_supported); | |
795 | ||
2dc6a016 | 796 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
797 | { |
798 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
799 | return -EIO; | |
800 | ||
022ae537 | 801 | *dev->dma_mask = dma_mask; |
022ae537 RK |
802 | |
803 | return 0; | |
804 | } | |
022ae537 | 805 | |
24056f52 RK |
806 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
807 | ||
808 | static int __init dma_debug_do_init(void) | |
809 | { | |
45cd5290 RK |
810 | #ifdef CONFIG_MMU |
811 | arm_vmregion_create_proc("dma-mappings", &consistent_head); | |
812 | #endif | |
24056f52 RK |
813 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); |
814 | return 0; | |
815 | } | |
816 | fs_initcall(dma_debug_do_init); |