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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 | 2 | /* |
0ddbccd1 | 3 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
4 | * |
5 | * Copyright (C) 2000-2004 Russell King | |
6 | * | |
1da177e4 LT |
7 | * DMA uncached mapping support. |
8 | */ | |
9 | #include <linux/module.h> | |
10 | #include <linux/mm.h> | |
36d0fd21 | 11 | #include <linux/genalloc.h> |
5a0e3ad6 | 12 | #include <linux/gfp.h> |
1da177e4 LT |
13 | #include <linux/errno.h> |
14 | #include <linux/list.h> | |
15 | #include <linux/init.h> | |
16 | #include <linux/device.h> | |
249baa54 | 17 | #include <linux/dma-direct.h> |
1da177e4 | 18 | #include <linux/dma-mapping.h> |
ad3c7b18 | 19 | #include <linux/dma-noncoherent.h> |
c7909509 | 20 | #include <linux/dma-contiguous.h> |
39af22a7 | 21 | #include <linux/highmem.h> |
c7909509 | 22 | #include <linux/memblock.h> |
99d1717d | 23 | #include <linux/slab.h> |
4ce63fcd | 24 | #include <linux/iommu.h> |
e9da6e99 | 25 | #include <linux/io.h> |
4ce63fcd | 26 | #include <linux/vmalloc.h> |
158e8bfe | 27 | #include <linux/sizes.h> |
a254129e | 28 | #include <linux/cma.h> |
1da177e4 | 29 | |
23759dc6 | 30 | #include <asm/memory.h> |
43377453 | 31 | #include <asm/highmem.h> |
1da177e4 | 32 | #include <asm/cacheflush.h> |
1da177e4 | 33 | #include <asm/tlbflush.h> |
99d1717d | 34 | #include <asm/mach/arch.h> |
4ce63fcd | 35 | #include <asm/dma-iommu.h> |
c7909509 MS |
36 | #include <asm/mach/map.h> |
37 | #include <asm/system_info.h> | |
38 | #include <asm/dma-contiguous.h> | |
0e0d26e7 | 39 | #include <xen/swiotlb-xen.h> |
37134cd5 | 40 | |
1234e3fd | 41 | #include "dma.h" |
022ae537 RK |
42 | #include "mm.h" |
43 | ||
b4268676 RV |
44 | struct arm_dma_alloc_args { |
45 | struct device *dev; | |
46 | size_t size; | |
47 | gfp_t gfp; | |
48 | pgprot_t prot; | |
49 | const void *caller; | |
50 | bool want_vaddr; | |
f1270896 | 51 | int coherent_flag; |
b4268676 RV |
52 | }; |
53 | ||
54 | struct arm_dma_free_args { | |
55 | struct device *dev; | |
56 | size_t size; | |
57 | void *cpu_addr; | |
58 | struct page *page; | |
59 | bool want_vaddr; | |
60 | }; | |
61 | ||
f1270896 GC |
62 | #define NORMAL 0 |
63 | #define COHERENT 1 | |
64 | ||
b4268676 RV |
65 | struct arm_dma_allocator { |
66 | void *(*alloc)(struct arm_dma_alloc_args *args, | |
67 | struct page **ret_page); | |
68 | void (*free)(struct arm_dma_free_args *args); | |
69 | }; | |
70 | ||
19e6e5e5 RV |
71 | struct arm_dma_buffer { |
72 | struct list_head list; | |
73 | void *virt; | |
b4268676 | 74 | struct arm_dma_allocator *allocator; |
19e6e5e5 RV |
75 | }; |
76 | ||
77 | static LIST_HEAD(arm_dma_bufs); | |
78 | static DEFINE_SPINLOCK(arm_dma_bufs_lock); | |
79 | ||
80 | static struct arm_dma_buffer *arm_dma_buffer_find(void *virt) | |
81 | { | |
82 | struct arm_dma_buffer *buf, *found = NULL; | |
83 | unsigned long flags; | |
84 | ||
85 | spin_lock_irqsave(&arm_dma_bufs_lock, flags); | |
86 | list_for_each_entry(buf, &arm_dma_bufs, list) { | |
87 | if (buf->virt == virt) { | |
88 | list_del(&buf->list); | |
89 | found = buf; | |
90 | break; | |
91 | } | |
92 | } | |
93 | spin_unlock_irqrestore(&arm_dma_bufs_lock, flags); | |
94 | return found; | |
95 | } | |
96 | ||
15237e1f MS |
97 | /* |
98 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
99 | * is either exclusively owned by the CPU (and therefore may be accessed | |
100 | * by it) or exclusively owned by the DMA device. These helper functions | |
101 | * represent the transitions between these two ownership states. | |
102 | * | |
103 | * Note, however, that on later ARMs, this notion does not work due to | |
104 | * speculative prefetches. We model our approach on the assumption that | |
105 | * the CPU does do speculative prefetches, which means we clean caches | |
106 | * before transfers and delay cache invalidation until transfer completion. | |
107 | * | |
15237e1f | 108 | */ |
51fde349 | 109 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 110 | size_t, enum dma_data_direction); |
51fde349 | 111 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
112 | size_t, enum dma_data_direction); |
113 | ||
2dc6a016 MS |
114 | /** |
115 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
116 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
117 | * @page: page that buffer resides in | |
118 | * @offset: offset into page for start of buffer | |
119 | * @size: size of buffer to map | |
120 | * @dir: DMA transfer direction | |
121 | * | |
122 | * Ensure that any data held in the cache is appropriately discarded | |
123 | * or written back. | |
124 | * | |
125 | * The device owns this memory once this call has completed. The CPU | |
126 | * can regain ownership by calling dma_unmap_page(). | |
127 | */ | |
51fde349 | 128 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 | 129 | unsigned long offset, size_t size, enum dma_data_direction dir, |
00085f1e | 130 | unsigned long attrs) |
2dc6a016 | 131 | { |
00085f1e | 132 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
51fde349 MS |
133 | __dma_page_cpu_to_dev(page, offset, size, dir); |
134 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
135 | } |
136 | ||
dd37e940 RH |
137 | static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page, |
138 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
00085f1e | 139 | unsigned long attrs) |
dd37e940 RH |
140 | { |
141 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
142 | } | |
143 | ||
2dc6a016 MS |
144 | /** |
145 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
146 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
147 | * @handle: DMA address of buffer | |
148 | * @size: size of buffer (same as passed to dma_map_page) | |
149 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
150 | * | |
151 | * Unmap a page streaming mode DMA translation. The handle and size | |
152 | * must match what was provided in the previous dma_map_page() call. | |
153 | * All other usages are undefined. | |
154 | * | |
155 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
156 | * whatever the device wrote there. | |
157 | */ | |
51fde349 | 158 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
00085f1e | 159 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
2dc6a016 | 160 | { |
00085f1e | 161 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
51fde349 MS |
162 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
163 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
164 | } |
165 | ||
51fde349 | 166 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
167 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
168 | { | |
169 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
170 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 171 | __dma_page_dev_to_cpu(page, offset, size, dir); |
2dc6a016 MS |
172 | } |
173 | ||
51fde349 | 174 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
175 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
176 | { | |
177 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
178 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 179 | __dma_page_cpu_to_dev(page, offset, size, dir); |
2dc6a016 MS |
180 | } |
181 | ||
5299709d | 182 | const struct dma_map_ops arm_dma_ops = { |
f99d6034 MS |
183 | .alloc = arm_dma_alloc, |
184 | .free = arm_dma_free, | |
185 | .mmap = arm_dma_mmap, | |
dc2832e1 | 186 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
187 | .map_page = arm_dma_map_page, |
188 | .unmap_page = arm_dma_unmap_page, | |
189 | .map_sg = arm_dma_map_sg, | |
190 | .unmap_sg = arm_dma_unmap_sg, | |
cfced786 | 191 | .map_resource = dma_direct_map_resource, |
2dc6a016 MS |
192 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, |
193 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
194 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
195 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
418a7a7e | 196 | .dma_supported = arm_dma_supported, |
249baa54 | 197 | .get_required_mask = dma_direct_get_required_mask, |
2dc6a016 MS |
198 | }; |
199 | EXPORT_SYMBOL(arm_dma_ops); | |
200 | ||
dd37e940 | 201 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, |
00085f1e | 202 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs); |
dd37e940 | 203 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 204 | dma_addr_t handle, unsigned long attrs); |
55af8a91 ML |
205 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
206 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
00085f1e | 207 | unsigned long attrs); |
dd37e940 | 208 | |
5299709d | 209 | const struct dma_map_ops arm_coherent_dma_ops = { |
dd37e940 RH |
210 | .alloc = arm_coherent_dma_alloc, |
211 | .free = arm_coherent_dma_free, | |
55af8a91 | 212 | .mmap = arm_coherent_dma_mmap, |
dd37e940 RH |
213 | .get_sgtable = arm_dma_get_sgtable, |
214 | .map_page = arm_coherent_dma_map_page, | |
215 | .map_sg = arm_dma_map_sg, | |
cfced786 | 216 | .map_resource = dma_direct_map_resource, |
418a7a7e | 217 | .dma_supported = arm_dma_supported, |
249baa54 | 218 | .get_required_mask = dma_direct_get_required_mask, |
dd37e940 RH |
219 | }; |
220 | EXPORT_SYMBOL(arm_coherent_dma_ops); | |
221 | ||
9f28cde0 RK |
222 | static int __dma_supported(struct device *dev, u64 mask, bool warn) |
223 | { | |
ab746573 | 224 | unsigned long max_dma_pfn = min(max_pfn, arm_dma_pfn_limit); |
9f28cde0 RK |
225 | |
226 | /* | |
227 | * Translate the device's DMA mask to a PFN limit. This | |
228 | * PFN number includes the page which we can DMA to. | |
229 | */ | |
230 | if (dma_to_pfn(dev, mask) < max_dma_pfn) { | |
231 | if (warn) | |
232 | dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", | |
233 | mask, | |
234 | dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, | |
235 | max_dma_pfn + 1); | |
236 | return 0; | |
237 | } | |
238 | ||
239 | return 1; | |
240 | } | |
241 | ||
ab6494f0 CM |
242 | static u64 get_coherent_dma_mask(struct device *dev) |
243 | { | |
4dcfa600 | 244 | u64 mask = (u64)DMA_BIT_MASK(32); |
ab6494f0 CM |
245 | |
246 | if (dev) { | |
247 | mask = dev->coherent_dma_mask; | |
248 | ||
249 | /* | |
250 | * Sanity check the DMA mask - it must be non-zero, and | |
251 | * must be able to be satisfied by a DMA allocation. | |
252 | */ | |
253 | if (mask == 0) { | |
254 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
255 | return 0; | |
256 | } | |
257 | ||
9f28cde0 | 258 | if (!__dma_supported(dev, mask, true)) |
ab6494f0 | 259 | return 0; |
ab6494f0 | 260 | } |
1da177e4 | 261 | |
ab6494f0 CM |
262 | return mask; |
263 | } | |
264 | ||
f1270896 | 265 | static void __dma_clear_buffer(struct page *page, size_t size, int coherent_flag) |
c7909509 | 266 | { |
c7909509 MS |
267 | /* |
268 | * Ensure that the allocated pages are zeroed, and that any data | |
269 | * lurking in the kernel direct-mapped region is invalidated. | |
270 | */ | |
9848e48f MS |
271 | if (PageHighMem(page)) { |
272 | phys_addr_t base = __pfn_to_phys(page_to_pfn(page)); | |
273 | phys_addr_t end = base + size; | |
274 | while (size > 0) { | |
275 | void *ptr = kmap_atomic(page); | |
276 | memset(ptr, 0, PAGE_SIZE); | |
f1270896 GC |
277 | if (coherent_flag != COHERENT) |
278 | dmac_flush_range(ptr, ptr + PAGE_SIZE); | |
9848e48f MS |
279 | kunmap_atomic(ptr); |
280 | page++; | |
281 | size -= PAGE_SIZE; | |
282 | } | |
f1270896 GC |
283 | if (coherent_flag != COHERENT) |
284 | outer_flush_range(base, end); | |
9848e48f MS |
285 | } else { |
286 | void *ptr = page_address(page); | |
4ce63fcd | 287 | memset(ptr, 0, size); |
f1270896 GC |
288 | if (coherent_flag != COHERENT) { |
289 | dmac_flush_range(ptr, ptr + size); | |
290 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
291 | } | |
4ce63fcd | 292 | } |
c7909509 MS |
293 | } |
294 | ||
7a9a32a9 RK |
295 | /* |
296 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
297 | * specified gfp mask. Note that 'size' must be page aligned. | |
298 | */ | |
f1270896 GC |
299 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, |
300 | gfp_t gfp, int coherent_flag) | |
7a9a32a9 RK |
301 | { |
302 | unsigned long order = get_order(size); | |
303 | struct page *page, *p, *e; | |
7a9a32a9 RK |
304 | |
305 | page = alloc_pages(gfp, order); | |
306 | if (!page) | |
307 | return NULL; | |
308 | ||
309 | /* | |
310 | * Now split the huge page and free the excess pages | |
311 | */ | |
312 | split_page(page, order); | |
313 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
314 | __free_page(p); | |
315 | ||
f1270896 | 316 | __dma_clear_buffer(page, size, coherent_flag); |
7a9a32a9 RK |
317 | |
318 | return page; | |
319 | } | |
320 | ||
321 | /* | |
322 | * Free a DMA buffer. 'size' must be page aligned. | |
323 | */ | |
324 | static void __dma_free_buffer(struct page *page, size_t size) | |
325 | { | |
326 | struct page *e = page + (size >> PAGE_SHIFT); | |
327 | ||
328 | while (page < e) { | |
329 | __free_page(page); | |
330 | page++; | |
331 | } | |
332 | } | |
333 | ||
e9da6e99 | 334 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
9848e48f | 335 | pgprot_t prot, struct page **ret_page, |
f1270896 | 336 | const void *caller, bool want_vaddr, |
712c604d | 337 | int coherent_flag, gfp_t gfp); |
99d1717d | 338 | |
e9da6e99 MS |
339 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
340 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 341 | const void *caller, bool want_vaddr); |
99d1717d | 342 | |
6e5267aa | 343 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
b337e1c4 | 344 | static struct gen_pool *atomic_pool __ro_after_init; |
6e5267aa | 345 | |
b337e1c4 | 346 | static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE; |
c7909509 MS |
347 | |
348 | static int __init early_coherent_pool(char *p) | |
349 | { | |
36d0fd21 | 350 | atomic_pool_size = memparse(p, &p); |
c7909509 MS |
351 | return 0; |
352 | } | |
353 | early_param("coherent_pool", early_coherent_pool); | |
354 | ||
355 | /* | |
356 | * Initialise the coherent pool for atomic allocations. | |
357 | */ | |
e9da6e99 | 358 | static int __init atomic_pool_init(void) |
c7909509 | 359 | { |
71b55663 | 360 | pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); |
9d1400cf | 361 | gfp_t gfp = GFP_KERNEL | GFP_DMA; |
c7909509 MS |
362 | struct page *page; |
363 | void *ptr; | |
c7909509 | 364 | |
36d0fd21 LA |
365 | atomic_pool = gen_pool_create(PAGE_SHIFT, -1); |
366 | if (!atomic_pool) | |
367 | goto out; | |
f1270896 GC |
368 | /* |
369 | * The atomic pool is only used for non-coherent allocations | |
370 | * so we must pass NORMAL for coherent_flag. | |
371 | */ | |
e464ef16 | 372 | if (dev_get_cma_area(NULL)) |
36d0fd21 | 373 | ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot, |
712c604d LS |
374 | &page, atomic_pool_init, true, NORMAL, |
375 | GFP_KERNEL); | |
e9da6e99 | 376 | else |
36d0fd21 | 377 | ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot, |
6e8266e3 | 378 | &page, atomic_pool_init, true); |
c7909509 | 379 | if (ptr) { |
36d0fd21 LA |
380 | int ret; |
381 | ||
382 | ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr, | |
383 | page_to_phys(page), | |
384 | atomic_pool_size, -1); | |
385 | if (ret) | |
386 | goto destroy_genpool; | |
387 | ||
388 | gen_pool_set_algo(atomic_pool, | |
389 | gen_pool_first_fit_order_align, | |
acb62448 | 390 | NULL); |
bf31c5e0 | 391 | pr_info("DMA: preallocated %zu KiB pool for atomic coherent allocations\n", |
36d0fd21 | 392 | atomic_pool_size / 1024); |
c7909509 MS |
393 | return 0; |
394 | } | |
ec10665c | 395 | |
36d0fd21 LA |
396 | destroy_genpool: |
397 | gen_pool_destroy(atomic_pool); | |
398 | atomic_pool = NULL; | |
399 | out: | |
bf31c5e0 | 400 | pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n", |
36d0fd21 | 401 | atomic_pool_size / 1024); |
c7909509 MS |
402 | return -ENOMEM; |
403 | } | |
404 | /* | |
405 | * CMA is activated by core_initcall, so we must be called after it. | |
406 | */ | |
e9da6e99 | 407 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
408 | |
409 | struct dma_contig_early_reserve { | |
410 | phys_addr_t base; | |
411 | unsigned long size; | |
412 | }; | |
413 | ||
414 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
415 | ||
416 | static int dma_mmu_remap_num __initdata; | |
417 | ||
418 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
419 | { | |
420 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
421 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
422 | dma_mmu_remap_num++; | |
423 | } | |
424 | ||
425 | void __init dma_contiguous_remap(void) | |
426 | { | |
427 | int i; | |
428 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
429 | phys_addr_t start = dma_mmu_remap[i].base; | |
430 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
431 | struct map_desc map; | |
432 | unsigned long addr; | |
433 | ||
434 | if (end > arm_lowmem_limit) | |
435 | end = arm_lowmem_limit; | |
436 | if (start >= end) | |
39f78e70 | 437 | continue; |
c7909509 MS |
438 | |
439 | map.pfn = __phys_to_pfn(start); | |
440 | map.virtual = __phys_to_virt(start); | |
441 | map.length = end - start; | |
442 | map.type = MT_MEMORY_DMA_READY; | |
443 | ||
444 | /* | |
6b076991 RK |
445 | * Clear previous low-memory mapping to ensure that the |
446 | * TLB does not see any conflicting entries, then flush | |
447 | * the TLB of the old entries before creating new mappings. | |
448 | * | |
449 | * This ensures that any speculatively loaded TLB entries | |
450 | * (even though they may be rare) can not cause any problems, | |
451 | * and ensures that this code is architecturally compliant. | |
c7909509 MS |
452 | */ |
453 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 454 | addr += PMD_SIZE) |
c7909509 MS |
455 | pmd_clear(pmd_off_k(addr)); |
456 | ||
6b076991 RK |
457 | flush_tlb_kernel_range(__phys_to_virt(start), |
458 | __phys_to_virt(end)); | |
459 | ||
d883c6cf | 460 | iotable_init(&map, 1); |
c7909509 MS |
461 | } |
462 | } | |
463 | ||
8b1e0f81 | 464 | static int __dma_update_pte(pte_t *pte, unsigned long addr, void *data) |
c7909509 MS |
465 | { |
466 | struct page *page = virt_to_page(addr); | |
467 | pgprot_t prot = *(pgprot_t *)data; | |
468 | ||
469 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
470 | return 0; | |
471 | } | |
472 | ||
473 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
474 | { | |
475 | unsigned long start = (unsigned long) page_address(page); | |
476 | unsigned end = start + size; | |
477 | ||
478 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
c7909509 MS |
479 | flush_tlb_kernel_range(start, end); |
480 | } | |
481 | ||
482 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
483 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 484 | const void *caller, bool want_vaddr) |
c7909509 MS |
485 | { |
486 | struct page *page; | |
6e8266e3 | 487 | void *ptr = NULL; |
f1270896 GC |
488 | /* |
489 | * __alloc_remap_buffer is only called when the device is | |
490 | * non-coherent | |
491 | */ | |
492 | page = __dma_alloc_buffer(dev, size, gfp, NORMAL); | |
c7909509 MS |
493 | if (!page) |
494 | return NULL; | |
6e8266e3 CC |
495 | if (!want_vaddr) |
496 | goto out; | |
c7909509 | 497 | |
78406ff5 | 498 | ptr = dma_common_contiguous_remap(page, size, prot, caller); |
c7909509 MS |
499 | if (!ptr) { |
500 | __dma_free_buffer(page, size); | |
501 | return NULL; | |
502 | } | |
503 | ||
6e8266e3 | 504 | out: |
c7909509 MS |
505 | *ret_page = page; |
506 | return ptr; | |
507 | } | |
508 | ||
e9da6e99 | 509 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 510 | { |
36d0fd21 | 511 | unsigned long val; |
e9da6e99 | 512 | void *ptr = NULL; |
c7909509 | 513 | |
36d0fd21 | 514 | if (!atomic_pool) { |
e9da6e99 | 515 | WARN(1, "coherent pool not initialised!\n"); |
c7909509 MS |
516 | return NULL; |
517 | } | |
518 | ||
36d0fd21 LA |
519 | val = gen_pool_alloc(atomic_pool, size); |
520 | if (val) { | |
521 | phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val); | |
522 | ||
523 | *ret_page = phys_to_page(phys); | |
524 | ptr = (void *)val; | |
c7909509 | 525 | } |
e9da6e99 MS |
526 | |
527 | return ptr; | |
c7909509 MS |
528 | } |
529 | ||
21d0a759 HD |
530 | static bool __in_atomic_pool(void *start, size_t size) |
531 | { | |
36d0fd21 | 532 | return addr_in_gen_pool(atomic_pool, (unsigned long)start, size); |
21d0a759 HD |
533 | } |
534 | ||
e9da6e99 | 535 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 536 | { |
21d0a759 | 537 | if (!__in_atomic_pool(start, size)) |
c7909509 MS |
538 | return 0; |
539 | ||
36d0fd21 | 540 | gen_pool_free(atomic_pool, (unsigned long)start, size); |
e9da6e99 | 541 | |
c7909509 MS |
542 | return 1; |
543 | } | |
544 | ||
545 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
9848e48f | 546 | pgprot_t prot, struct page **ret_page, |
f1270896 | 547 | const void *caller, bool want_vaddr, |
712c604d | 548 | int coherent_flag, gfp_t gfp) |
c7909509 MS |
549 | { |
550 | unsigned long order = get_order(size); | |
551 | size_t count = size >> PAGE_SHIFT; | |
552 | struct page *page; | |
6e8266e3 | 553 | void *ptr = NULL; |
c7909509 | 554 | |
d834c5ab | 555 | page = dma_alloc_from_contiguous(dev, count, order, gfp & __GFP_NOWARN); |
c7909509 MS |
556 | if (!page) |
557 | return NULL; | |
558 | ||
f1270896 | 559 | __dma_clear_buffer(page, size, coherent_flag); |
c7909509 | 560 | |
6e8266e3 CC |
561 | if (!want_vaddr) |
562 | goto out; | |
563 | ||
9848e48f | 564 | if (PageHighMem(page)) { |
78406ff5 | 565 | ptr = dma_common_contiguous_remap(page, size, prot, caller); |
9848e48f MS |
566 | if (!ptr) { |
567 | dma_release_from_contiguous(dev, page, count); | |
568 | return NULL; | |
569 | } | |
570 | } else { | |
571 | __dma_remap(page, size, prot); | |
572 | ptr = page_address(page); | |
573 | } | |
6e8266e3 CC |
574 | |
575 | out: | |
c7909509 | 576 | *ret_page = page; |
9848e48f | 577 | return ptr; |
c7909509 MS |
578 | } |
579 | ||
580 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
6e8266e3 | 581 | void *cpu_addr, size_t size, bool want_vaddr) |
c7909509 | 582 | { |
6e8266e3 CC |
583 | if (want_vaddr) { |
584 | if (PageHighMem(page)) | |
78406ff5 | 585 | dma_common_free_remap(cpu_addr, size); |
6e8266e3 CC |
586 | else |
587 | __dma_remap(page, size, PAGE_KERNEL); | |
588 | } | |
c7909509 MS |
589 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); |
590 | } | |
591 | ||
00085f1e | 592 | static inline pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot) |
f99d6034 | 593 | { |
00085f1e KK |
594 | prot = (attrs & DMA_ATTR_WRITE_COMBINE) ? |
595 | pgprot_writecombine(prot) : | |
596 | pgprot_dmacoherent(prot); | |
f99d6034 MS |
597 | return prot; |
598 | } | |
599 | ||
c7909509 MS |
600 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
601 | struct page **ret_page) | |
ab6494f0 | 602 | { |
c7909509 | 603 | struct page *page; |
f1270896 GC |
604 | /* __alloc_simple_buffer is only called when the device is coherent */ |
605 | page = __dma_alloc_buffer(dev, size, gfp, COHERENT); | |
c7909509 MS |
606 | if (!page) |
607 | return NULL; | |
608 | ||
609 | *ret_page = page; | |
610 | return page_address(page); | |
611 | } | |
612 | ||
b4268676 RV |
613 | static void *simple_allocator_alloc(struct arm_dma_alloc_args *args, |
614 | struct page **ret_page) | |
615 | { | |
616 | return __alloc_simple_buffer(args->dev, args->size, args->gfp, | |
617 | ret_page); | |
618 | } | |
c7909509 | 619 | |
b4268676 RV |
620 | static void simple_allocator_free(struct arm_dma_free_args *args) |
621 | { | |
622 | __dma_free_buffer(args->page, args->size); | |
623 | } | |
624 | ||
625 | static struct arm_dma_allocator simple_allocator = { | |
626 | .alloc = simple_allocator_alloc, | |
627 | .free = simple_allocator_free, | |
628 | }; | |
629 | ||
630 | static void *cma_allocator_alloc(struct arm_dma_alloc_args *args, | |
631 | struct page **ret_page) | |
632 | { | |
633 | return __alloc_from_contiguous(args->dev, args->size, args->prot, | |
634 | ret_page, args->caller, | |
712c604d LS |
635 | args->want_vaddr, args->coherent_flag, |
636 | args->gfp); | |
b4268676 RV |
637 | } |
638 | ||
639 | static void cma_allocator_free(struct arm_dma_free_args *args) | |
640 | { | |
641 | __free_from_contiguous(args->dev, args->page, args->cpu_addr, | |
642 | args->size, args->want_vaddr); | |
643 | } | |
644 | ||
645 | static struct arm_dma_allocator cma_allocator = { | |
646 | .alloc = cma_allocator_alloc, | |
647 | .free = cma_allocator_free, | |
648 | }; | |
649 | ||
650 | static void *pool_allocator_alloc(struct arm_dma_alloc_args *args, | |
651 | struct page **ret_page) | |
652 | { | |
653 | return __alloc_from_pool(args->size, ret_page); | |
654 | } | |
655 | ||
656 | static void pool_allocator_free(struct arm_dma_free_args *args) | |
657 | { | |
658 | __free_from_pool(args->cpu_addr, args->size); | |
659 | } | |
660 | ||
661 | static struct arm_dma_allocator pool_allocator = { | |
662 | .alloc = pool_allocator_alloc, | |
663 | .free = pool_allocator_free, | |
664 | }; | |
665 | ||
666 | static void *remap_allocator_alloc(struct arm_dma_alloc_args *args, | |
667 | struct page **ret_page) | |
668 | { | |
669 | return __alloc_remap_buffer(args->dev, args->size, args->gfp, | |
670 | args->prot, ret_page, args->caller, | |
671 | args->want_vaddr); | |
672 | } | |
673 | ||
674 | static void remap_allocator_free(struct arm_dma_free_args *args) | |
675 | { | |
676 | if (args->want_vaddr) | |
78406ff5 | 677 | dma_common_free_remap(args->cpu_addr, args->size); |
b4268676 RV |
678 | |
679 | __dma_free_buffer(args->page, args->size); | |
680 | } | |
681 | ||
682 | static struct arm_dma_allocator remap_allocator = { | |
683 | .alloc = remap_allocator_alloc, | |
684 | .free = remap_allocator_free, | |
685 | }; | |
c7909509 MS |
686 | |
687 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
6e8266e3 | 688 | gfp_t gfp, pgprot_t prot, bool is_coherent, |
00085f1e | 689 | unsigned long attrs, const void *caller) |
c7909509 MS |
690 | { |
691 | u64 mask = get_coherent_dma_mask(dev); | |
3dd7ea92 | 692 | struct page *page = NULL; |
31ebf944 | 693 | void *addr; |
b4268676 | 694 | bool allowblock, cma; |
19e6e5e5 | 695 | struct arm_dma_buffer *buf; |
b4268676 RV |
696 | struct arm_dma_alloc_args args = { |
697 | .dev = dev, | |
698 | .size = PAGE_ALIGN(size), | |
699 | .gfp = gfp, | |
700 | .prot = prot, | |
701 | .caller = caller, | |
00085f1e | 702 | .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0), |
f1270896 | 703 | .coherent_flag = is_coherent ? COHERENT : NORMAL, |
b4268676 | 704 | }; |
ab6494f0 | 705 | |
c7909509 MS |
706 | #ifdef CONFIG_DMA_API_DEBUG |
707 | u64 limit = (mask + 1) & ~mask; | |
708 | if (limit && size >= limit) { | |
709 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
710 | size, mask); | |
711 | return NULL; | |
712 | } | |
713 | #endif | |
714 | ||
715 | if (!mask) | |
716 | return NULL; | |
717 | ||
9c18fcf7 AC |
718 | buf = kzalloc(sizeof(*buf), |
719 | gfp & ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM)); | |
19e6e5e5 RV |
720 | if (!buf) |
721 | return NULL; | |
722 | ||
c7909509 MS |
723 | if (mask < 0xffffffffULL) |
724 | gfp |= GFP_DMA; | |
725 | ||
ea2e7057 SB |
726 | /* |
727 | * Following is a work-around (a.k.a. hack) to prevent pages | |
728 | * with __GFP_COMP being passed to split_page() which cannot | |
729 | * handle them. The real problem is that this flag probably | |
730 | * should be 0 on ARM as it is not supported on this | |
731 | * platform; see CONFIG_HUGETLBFS. | |
732 | */ | |
733 | gfp &= ~(__GFP_COMP); | |
b4268676 | 734 | args.gfp = gfp; |
ea2e7057 | 735 | |
72fd97bf | 736 | *handle = DMA_MAPPING_ERROR; |
b4268676 RV |
737 | allowblock = gfpflags_allow_blocking(gfp); |
738 | cma = allowblock ? dev_get_cma_area(dev) : false; | |
739 | ||
740 | if (cma) | |
741 | buf->allocator = &cma_allocator; | |
1655cf88 | 742 | else if (is_coherent) |
b4268676 RV |
743 | buf->allocator = &simple_allocator; |
744 | else if (allowblock) | |
745 | buf->allocator = &remap_allocator; | |
31ebf944 | 746 | else |
b4268676 RV |
747 | buf->allocator = &pool_allocator; |
748 | ||
749 | addr = buf->allocator->alloc(&args, &page); | |
695ae0af | 750 | |
19e6e5e5 RV |
751 | if (page) { |
752 | unsigned long flags; | |
753 | ||
9eedd963 | 754 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
b4268676 | 755 | buf->virt = args.want_vaddr ? addr : page; |
19e6e5e5 RV |
756 | |
757 | spin_lock_irqsave(&arm_dma_bufs_lock, flags); | |
758 | list_add(&buf->list, &arm_dma_bufs); | |
759 | spin_unlock_irqrestore(&arm_dma_bufs_lock, flags); | |
760 | } else { | |
761 | kfree(buf); | |
762 | } | |
695ae0af | 763 | |
b4268676 | 764 | return args.want_vaddr ? addr : page; |
31ebf944 | 765 | } |
1da177e4 LT |
766 | |
767 | /* | |
768 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
769 | * virtual and bus address for that space. | |
770 | */ | |
f99d6034 | 771 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
00085f1e | 772 | gfp_t gfp, unsigned long attrs) |
1da177e4 | 773 | { |
0ea1ec71 | 774 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
1fe53268 | 775 | |
dd37e940 | 776 | return __dma_alloc(dev, size, handle, gfp, prot, false, |
6e8266e3 | 777 | attrs, __builtin_return_address(0)); |
dd37e940 RH |
778 | } |
779 | ||
780 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, | |
00085f1e | 781 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs) |
dd37e940 | 782 | { |
21caf3a7 | 783 | return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true, |
6e8266e3 | 784 | attrs, __builtin_return_address(0)); |
1da177e4 | 785 | } |
1da177e4 | 786 | |
55af8a91 | 787 | static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
f99d6034 | 788 | void *cpu_addr, dma_addr_t dma_addr, size_t size, |
00085f1e | 789 | unsigned long attrs) |
1da177e4 | 790 | { |
c2a3831d | 791 | int ret = -ENXIO; |
a70c3ee3 | 792 | unsigned long nr_vma_pages = vma_pages(vma); |
50262a4b | 793 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
c7909509 | 794 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
795 | unsigned long off = vma->vm_pgoff; |
796 | ||
43fc509c | 797 | if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) |
47142f07 MS |
798 | return ret; |
799 | ||
50262a4b MS |
800 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
801 | ret = remap_pfn_range(vma, vma->vm_start, | |
802 | pfn + off, | |
803 | vma->vm_end - vma->vm_start, | |
804 | vma->vm_page_prot); | |
805 | } | |
1da177e4 LT |
806 | |
807 | return ret; | |
808 | } | |
809 | ||
55af8a91 ML |
810 | /* |
811 | * Create userspace mapping for the DMA-coherent memory. | |
812 | */ | |
813 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
814 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
00085f1e | 815 | unsigned long attrs) |
55af8a91 ML |
816 | { |
817 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
818 | } | |
819 | ||
820 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
821 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
00085f1e | 822 | unsigned long attrs) |
55af8a91 | 823 | { |
55af8a91 | 824 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
55af8a91 ML |
825 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); |
826 | } | |
827 | ||
1da177e4 | 828 | /* |
c7909509 | 829 | * Free a buffer as defined by the above mapping. |
1da177e4 | 830 | */ |
dd37e940 | 831 | static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 832 | dma_addr_t handle, unsigned long attrs, |
dd37e940 | 833 | bool is_coherent) |
1da177e4 | 834 | { |
c7909509 | 835 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
19e6e5e5 | 836 | struct arm_dma_buffer *buf; |
b4268676 RV |
837 | struct arm_dma_free_args args = { |
838 | .dev = dev, | |
839 | .size = PAGE_ALIGN(size), | |
840 | .cpu_addr = cpu_addr, | |
841 | .page = page, | |
00085f1e | 842 | .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0), |
b4268676 | 843 | }; |
19e6e5e5 RV |
844 | |
845 | buf = arm_dma_buffer_find(cpu_addr); | |
846 | if (WARN(!buf, "Freeing invalid buffer %p\n", cpu_addr)) | |
847 | return; | |
5edf71ae | 848 | |
b4268676 | 849 | buf->allocator->free(&args); |
19e6e5e5 | 850 | kfree(buf); |
1da177e4 | 851 | } |
afd1a321 | 852 | |
dd37e940 | 853 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 854 | dma_addr_t handle, unsigned long attrs) |
dd37e940 RH |
855 | { |
856 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, false); | |
857 | } | |
858 | ||
859 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
00085f1e | 860 | dma_addr_t handle, unsigned long attrs) |
dd37e940 RH |
861 | { |
862 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, true); | |
863 | } | |
864 | ||
dc2832e1 MS |
865 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
866 | void *cpu_addr, dma_addr_t handle, size_t size, | |
00085f1e | 867 | unsigned long attrs) |
dc2832e1 | 868 | { |
916a008b RK |
869 | unsigned long pfn = dma_to_pfn(dev, handle); |
870 | struct page *page; | |
dc2832e1 MS |
871 | int ret; |
872 | ||
916a008b RK |
873 | /* If the PFN is not valid, we do not have a struct page */ |
874 | if (!pfn_valid(pfn)) | |
875 | return -ENXIO; | |
876 | ||
877 | page = pfn_to_page(pfn); | |
878 | ||
dc2832e1 MS |
879 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); |
880 | if (unlikely(ret)) | |
881 | return ret; | |
882 | ||
883 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
884 | return 0; | |
885 | } | |
886 | ||
4ea0d737 | 887 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
888 | size_t size, enum dma_data_direction dir, |
889 | void (*op)(const void *, size_t, int)) | |
43377453 | 890 | { |
15653371 RK |
891 | unsigned long pfn; |
892 | size_t left = size; | |
893 | ||
894 | pfn = page_to_pfn(page) + offset / PAGE_SIZE; | |
895 | offset %= PAGE_SIZE; | |
896 | ||
43377453 NP |
897 | /* |
898 | * A single sg entry may refer to multiple physically contiguous | |
899 | * pages. But we still need to process highmem pages individually. | |
900 | * If highmem is not configured then the bulk of this loop gets | |
901 | * optimized out. | |
902 | */ | |
43377453 NP |
903 | do { |
904 | size_t len = left; | |
93f1d629 RK |
905 | void *vaddr; |
906 | ||
15653371 RK |
907 | page = pfn_to_page(pfn); |
908 | ||
93f1d629 | 909 | if (PageHighMem(page)) { |
15653371 | 910 | if (len + offset > PAGE_SIZE) |
93f1d629 | 911 | len = PAGE_SIZE - offset; |
dd0f67f4 JK |
912 | |
913 | if (cache_is_vipt_nonaliasing()) { | |
39af22a7 | 914 | vaddr = kmap_atomic(page); |
7e5a69e8 | 915 | op(vaddr + offset, len, dir); |
39af22a7 | 916 | kunmap_atomic(vaddr); |
dd0f67f4 JK |
917 | } else { |
918 | vaddr = kmap_high_get(page); | |
919 | if (vaddr) { | |
920 | op(vaddr + offset, len, dir); | |
921 | kunmap_high(page); | |
922 | } | |
43377453 | 923 | } |
93f1d629 RK |
924 | } else { |
925 | vaddr = page_address(page) + offset; | |
a9c9147e | 926 | op(vaddr, len, dir); |
43377453 | 927 | } |
43377453 | 928 | offset = 0; |
15653371 | 929 | pfn++; |
43377453 NP |
930 | left -= len; |
931 | } while (left); | |
932 | } | |
4ea0d737 | 933 | |
51fde349 MS |
934 | /* |
935 | * Make an area consistent for devices. | |
936 | * Note: Drivers should NOT use this function directly, as it will break | |
937 | * platforms with CONFIG_DMABOUNCE. | |
938 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
939 | */ | |
940 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
941 | size_t size, enum dma_data_direction dir) |
942 | { | |
2161c248 | 943 | phys_addr_t paddr; |
65af191a | 944 | |
a9c9147e | 945 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
946 | |
947 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
948 | if (dir == DMA_FROM_DEVICE) { |
949 | outer_inv_range(paddr, paddr + size); | |
950 | } else { | |
951 | outer_clean_range(paddr, paddr + size); | |
952 | } | |
953 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 954 | } |
4ea0d737 | 955 | |
51fde349 | 956 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
957 | size_t size, enum dma_data_direction dir) |
958 | { | |
2161c248 | 959 | phys_addr_t paddr = page_to_phys(page) + off; |
2ffe2da3 RK |
960 | |
961 | /* FIXME: non-speculating: not required */ | |
deace4a6 RK |
962 | /* in any case, don't bother invalidating if DMA to device */ |
963 | if (dir != DMA_TO_DEVICE) { | |
2ffe2da3 RK |
964 | outer_inv_range(paddr, paddr + size); |
965 | ||
deace4a6 RK |
966 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
967 | } | |
c0177800 CM |
968 | |
969 | /* | |
b2a234ed | 970 | * Mark the D-cache clean for these pages to avoid extra flushing. |
c0177800 | 971 | */ |
b2a234ed ML |
972 | if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) { |
973 | unsigned long pfn; | |
974 | size_t left = size; | |
975 | ||
976 | pfn = page_to_pfn(page) + off / PAGE_SIZE; | |
977 | off %= PAGE_SIZE; | |
978 | if (off) { | |
979 | pfn++; | |
980 | left -= PAGE_SIZE - off; | |
981 | } | |
982 | while (left >= PAGE_SIZE) { | |
983 | page = pfn_to_page(pfn++); | |
984 | set_bit(PG_dcache_clean, &page->flags); | |
985 | left -= PAGE_SIZE; | |
986 | } | |
987 | } | |
4ea0d737 | 988 | } |
43377453 | 989 | |
afd1a321 | 990 | /** |
2a550e73 | 991 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
992 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
993 | * @sg: list of buffers | |
994 | * @nents: number of buffers to map | |
995 | * @dir: DMA transfer direction | |
996 | * | |
997 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
998 | * This is the scatter-gather version of the dma_map_single interface. | |
999 | * Here the scatter gather list elements are each tagged with the | |
1000 | * appropriate dma address and length. They are obtained via | |
1001 | * sg_dma_{address,length}. | |
1002 | * | |
1003 | * Device ownership issues as mentioned for dma_map_single are the same | |
1004 | * here. | |
1005 | */ | |
2dc6a016 | 1006 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
00085f1e | 1007 | enum dma_data_direction dir, unsigned long attrs) |
afd1a321 | 1008 | { |
5299709d | 1009 | const struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 1010 | struct scatterlist *s; |
01135d92 | 1011 | int i, j; |
afd1a321 RK |
1012 | |
1013 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
1014 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
1015 | s->dma_length = s->length; | |
1016 | #endif | |
2a550e73 MS |
1017 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
1018 | s->length, dir, attrs); | |
01135d92 RK |
1019 | if (dma_mapping_error(dev, s->dma_address)) |
1020 | goto bad_mapping; | |
afd1a321 | 1021 | } |
afd1a321 | 1022 | return nents; |
01135d92 RK |
1023 | |
1024 | bad_mapping: | |
1025 | for_each_sg(sg, s, i, j) | |
2a550e73 | 1026 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 1027 | return 0; |
afd1a321 | 1028 | } |
afd1a321 RK |
1029 | |
1030 | /** | |
2a550e73 | 1031 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
1032 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1033 | * @sg: list of buffers | |
0adfca6f | 1034 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
1035 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
1036 | * | |
1037 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1038 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1039 | */ | |
2dc6a016 | 1040 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
00085f1e | 1041 | enum dma_data_direction dir, unsigned long attrs) |
afd1a321 | 1042 | { |
5299709d | 1043 | const struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 1044 | struct scatterlist *s; |
01135d92 | 1045 | |
01135d92 | 1046 | int i; |
24056f52 | 1047 | |
01135d92 | 1048 | for_each_sg(sg, s, nents, i) |
2a550e73 | 1049 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 1050 | } |
afd1a321 RK |
1051 | |
1052 | /** | |
2a550e73 | 1053 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
1054 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1055 | * @sg: list of buffers | |
1056 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1057 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1058 | */ | |
2dc6a016 | 1059 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1060 | int nents, enum dma_data_direction dir) |
1061 | { | |
5299709d | 1062 | const struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1063 | struct scatterlist *s; |
1064 | int i; | |
1065 | ||
2a550e73 MS |
1066 | for_each_sg(sg, s, nents, i) |
1067 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
1068 | dir); | |
afd1a321 | 1069 | } |
afd1a321 RK |
1070 | |
1071 | /** | |
2a550e73 | 1072 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
1073 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1074 | * @sg: list of buffers | |
1075 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1076 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1077 | */ | |
2dc6a016 | 1078 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1079 | int nents, enum dma_data_direction dir) |
1080 | { | |
5299709d | 1081 | const struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1082 | struct scatterlist *s; |
1083 | int i; | |
1084 | ||
2a550e73 MS |
1085 | for_each_sg(sg, s, nents, i) |
1086 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
1087 | dir); | |
afd1a321 | 1088 | } |
24056f52 | 1089 | |
022ae537 RK |
1090 | /* |
1091 | * Return whether the given device DMA address mask can be supported | |
1092 | * properly. For example, if your device can only drive the low 24-bits | |
1093 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
1094 | * to this function. | |
1095 | */ | |
418a7a7e | 1096 | int arm_dma_supported(struct device *dev, u64 mask) |
022ae537 | 1097 | { |
9f28cde0 | 1098 | return __dma_supported(dev, mask, false); |
022ae537 | 1099 | } |
022ae537 | 1100 | |
1874619a TR |
1101 | static const struct dma_map_ops *arm_get_dma_map_ops(bool coherent) |
1102 | { | |
ad3c7b18 CH |
1103 | /* |
1104 | * When CONFIG_ARM_LPAE is set, physical address can extend above | |
1105 | * 32-bits, which then can't be addressed by devices that only support | |
1106 | * 32-bit DMA. | |
1107 | * Use the generic dma-direct / swiotlb ops code in that case, as that | |
1108 | * handles bounce buffering for us. | |
ad3c7b18 CH |
1109 | */ |
1110 | if (IS_ENABLED(CONFIG_ARM_LPAE)) | |
1111 | return NULL; | |
1874619a TR |
1112 | return coherent ? &arm_coherent_dma_ops : &arm_dma_ops; |
1113 | } | |
1114 | ||
4ce63fcd MS |
1115 | #ifdef CONFIG_ARM_DMA_USE_IOMMU |
1116 | ||
7d2822df S |
1117 | static int __dma_info_to_prot(enum dma_data_direction dir, unsigned long attrs) |
1118 | { | |
1119 | int prot = 0; | |
1120 | ||
1121 | if (attrs & DMA_ATTR_PRIVILEGED) | |
1122 | prot |= IOMMU_PRIV; | |
1123 | ||
1124 | switch (dir) { | |
1125 | case DMA_BIDIRECTIONAL: | |
1126 | return prot | IOMMU_READ | IOMMU_WRITE; | |
1127 | case DMA_TO_DEVICE: | |
1128 | return prot | IOMMU_READ; | |
1129 | case DMA_FROM_DEVICE: | |
1130 | return prot | IOMMU_WRITE; | |
1131 | default: | |
1132 | return prot; | |
1133 | } | |
1134 | } | |
1135 | ||
4ce63fcd MS |
1136 | /* IOMMU */ |
1137 | ||
4d852ef8 AH |
1138 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping); |
1139 | ||
4ce63fcd MS |
1140 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, |
1141 | size_t size) | |
1142 | { | |
1143 | unsigned int order = get_order(size); | |
1144 | unsigned int align = 0; | |
1145 | unsigned int count, start; | |
006f841d | 1146 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1147 | unsigned long flags; |
4d852ef8 AH |
1148 | dma_addr_t iova; |
1149 | int i; | |
4ce63fcd | 1150 | |
60460abf SWK |
1151 | if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT) |
1152 | order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT; | |
1153 | ||
68efd7d2 MS |
1154 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1155 | align = (1 << order) - 1; | |
4ce63fcd MS |
1156 | |
1157 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 AH |
1158 | for (i = 0; i < mapping->nr_bitmaps; i++) { |
1159 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1160 | mapping->bits, 0, count, align); | |
1161 | ||
1162 | if (start > mapping->bits) | |
1163 | continue; | |
1164 | ||
1165 | bitmap_set(mapping->bitmaps[i], start, count); | |
1166 | break; | |
4ce63fcd MS |
1167 | } |
1168 | ||
4d852ef8 AH |
1169 | /* |
1170 | * No unused range found. Try to extend the existing mapping | |
1171 | * and perform a second attempt to reserve an IO virtual | |
1172 | * address range of size bytes. | |
1173 | */ | |
1174 | if (i == mapping->nr_bitmaps) { | |
1175 | if (extend_iommu_mapping(mapping)) { | |
1176 | spin_unlock_irqrestore(&mapping->lock, flags); | |
72fd97bf | 1177 | return DMA_MAPPING_ERROR; |
4d852ef8 AH |
1178 | } |
1179 | ||
1180 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1181 | mapping->bits, 0, count, align); | |
1182 | ||
1183 | if (start > mapping->bits) { | |
1184 | spin_unlock_irqrestore(&mapping->lock, flags); | |
72fd97bf | 1185 | return DMA_MAPPING_ERROR; |
4d852ef8 AH |
1186 | } |
1187 | ||
1188 | bitmap_set(mapping->bitmaps[i], start, count); | |
1189 | } | |
4ce63fcd MS |
1190 | spin_unlock_irqrestore(&mapping->lock, flags); |
1191 | ||
006f841d | 1192 | iova = mapping->base + (mapping_size * i); |
68efd7d2 | 1193 | iova += start << PAGE_SHIFT; |
4d852ef8 AH |
1194 | |
1195 | return iova; | |
4ce63fcd MS |
1196 | } |
1197 | ||
1198 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
1199 | dma_addr_t addr, size_t size) | |
1200 | { | |
4d852ef8 | 1201 | unsigned int start, count; |
006f841d | 1202 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1203 | unsigned long flags; |
4d852ef8 AH |
1204 | dma_addr_t bitmap_base; |
1205 | u32 bitmap_index; | |
1206 | ||
1207 | if (!size) | |
1208 | return; | |
1209 | ||
006f841d | 1210 | bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size; |
4d852ef8 AH |
1211 | BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions); |
1212 | ||
006f841d | 1213 | bitmap_base = mapping->base + mapping_size * bitmap_index; |
4d852ef8 | 1214 | |
68efd7d2 | 1215 | start = (addr - bitmap_base) >> PAGE_SHIFT; |
4d852ef8 | 1216 | |
006f841d | 1217 | if (addr + size > bitmap_base + mapping_size) { |
4d852ef8 AH |
1218 | /* |
1219 | * The address range to be freed reaches into the iova | |
1220 | * range of the next bitmap. This should not happen as | |
1221 | * we don't allow this in __alloc_iova (at the | |
1222 | * moment). | |
1223 | */ | |
1224 | BUG(); | |
1225 | } else | |
68efd7d2 | 1226 | count = size >> PAGE_SHIFT; |
4ce63fcd MS |
1227 | |
1228 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 | 1229 | bitmap_clear(mapping->bitmaps[bitmap_index], start, count); |
4ce63fcd MS |
1230 | spin_unlock_irqrestore(&mapping->lock, flags); |
1231 | } | |
1232 | ||
33298ef6 DA |
1233 | /* We'll try 2M, 1M, 64K, and finally 4K; array must end with 0! */ |
1234 | static const int iommu_order_array[] = { 9, 8, 4, 0 }; | |
1235 | ||
549a17e4 | 1236 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, |
00085f1e | 1237 | gfp_t gfp, unsigned long attrs, |
f1270896 | 1238 | int coherent_flag) |
4ce63fcd MS |
1239 | { |
1240 | struct page **pages; | |
1241 | int count = size >> PAGE_SHIFT; | |
1242 | int array_size = count * sizeof(struct page *); | |
1243 | int i = 0; | |
33298ef6 | 1244 | int order_idx = 0; |
4ce63fcd MS |
1245 | |
1246 | if (array_size <= PAGE_SIZE) | |
23be7fda | 1247 | pages = kzalloc(array_size, GFP_KERNEL); |
4ce63fcd MS |
1248 | else |
1249 | pages = vzalloc(array_size); | |
1250 | if (!pages) | |
1251 | return NULL; | |
1252 | ||
00085f1e | 1253 | if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) |
549a17e4 MS |
1254 | { |
1255 | unsigned long order = get_order(size); | |
1256 | struct page *page; | |
1257 | ||
d834c5ab MS |
1258 | page = dma_alloc_from_contiguous(dev, count, order, |
1259 | gfp & __GFP_NOWARN); | |
549a17e4 MS |
1260 | if (!page) |
1261 | goto error; | |
1262 | ||
f1270896 | 1263 | __dma_clear_buffer(page, size, coherent_flag); |
549a17e4 MS |
1264 | |
1265 | for (i = 0; i < count; i++) | |
1266 | pages[i] = page + i; | |
1267 | ||
1268 | return pages; | |
1269 | } | |
1270 | ||
14d3ae2e | 1271 | /* Go straight to 4K chunks if caller says it's OK. */ |
00085f1e | 1272 | if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES) |
14d3ae2e DA |
1273 | order_idx = ARRAY_SIZE(iommu_order_array) - 1; |
1274 | ||
f8669bef MS |
1275 | /* |
1276 | * IOMMU can map any pages, so himem can also be used here | |
1277 | */ | |
1278 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
1279 | ||
4ce63fcd | 1280 | while (count) { |
49f28aa6 TF |
1281 | int j, order; |
1282 | ||
33298ef6 DA |
1283 | order = iommu_order_array[order_idx]; |
1284 | ||
1285 | /* Drop down when we get small */ | |
1286 | if (__fls(count) < order) { | |
1287 | order_idx++; | |
1288 | continue; | |
49f28aa6 | 1289 | } |
4ce63fcd | 1290 | |
33298ef6 DA |
1291 | if (order) { |
1292 | /* See if it's easy to allocate a high-order chunk */ | |
1293 | pages[i] = alloc_pages(gfp | __GFP_NORETRY, order); | |
1294 | ||
1295 | /* Go down a notch at first sign of pressure */ | |
1296 | if (!pages[i]) { | |
1297 | order_idx++; | |
1298 | continue; | |
1299 | } | |
1300 | } else { | |
49f28aa6 TF |
1301 | pages[i] = alloc_pages(gfp, 0); |
1302 | if (!pages[i]) | |
1303 | goto error; | |
1304 | } | |
4ce63fcd | 1305 | |
5a796eeb | 1306 | if (order) { |
4ce63fcd | 1307 | split_page(pages[i], order); |
5a796eeb HD |
1308 | j = 1 << order; |
1309 | while (--j) | |
1310 | pages[i + j] = pages[i] + j; | |
1311 | } | |
4ce63fcd | 1312 | |
f1270896 | 1313 | __dma_clear_buffer(pages[i], PAGE_SIZE << order, coherent_flag); |
4ce63fcd MS |
1314 | i += 1 << order; |
1315 | count -= 1 << order; | |
1316 | } | |
1317 | ||
1318 | return pages; | |
1319 | error: | |
9fa8af91 | 1320 | while (i--) |
4ce63fcd MS |
1321 | if (pages[i]) |
1322 | __free_pages(pages[i], 0); | |
1d5cfdb0 | 1323 | kvfree(pages); |
4ce63fcd MS |
1324 | return NULL; |
1325 | } | |
1326 | ||
549a17e4 | 1327 | static int __iommu_free_buffer(struct device *dev, struct page **pages, |
00085f1e | 1328 | size_t size, unsigned long attrs) |
4ce63fcd MS |
1329 | { |
1330 | int count = size >> PAGE_SHIFT; | |
4ce63fcd | 1331 | int i; |
549a17e4 | 1332 | |
00085f1e | 1333 | if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) { |
549a17e4 MS |
1334 | dma_release_from_contiguous(dev, pages[0], count); |
1335 | } else { | |
1336 | for (i = 0; i < count; i++) | |
1337 | if (pages[i]) | |
1338 | __free_pages(pages[i], 0); | |
1339 | } | |
1340 | ||
1d5cfdb0 | 1341 | kvfree(pages); |
4ce63fcd MS |
1342 | return 0; |
1343 | } | |
1344 | ||
4ce63fcd MS |
1345 | /* |
1346 | * Create a mapping in device IO address space for specified pages | |
1347 | */ | |
1348 | static dma_addr_t | |
7d2822df S |
1349 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size, |
1350 | unsigned long attrs) | |
4ce63fcd | 1351 | { |
89cfdb19 | 1352 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1353 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1354 | dma_addr_t dma_addr, iova; | |
90cde558 | 1355 | int i; |
4ce63fcd MS |
1356 | |
1357 | dma_addr = __alloc_iova(mapping, size); | |
72fd97bf | 1358 | if (dma_addr == DMA_MAPPING_ERROR) |
4ce63fcd MS |
1359 | return dma_addr; |
1360 | ||
1361 | iova = dma_addr; | |
1362 | for (i = 0; i < count; ) { | |
90cde558 AP |
1363 | int ret; |
1364 | ||
4ce63fcd MS |
1365 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; |
1366 | phys_addr_t phys = page_to_phys(pages[i]); | |
1367 | unsigned int len, j; | |
1368 | ||
1369 | for (j = i + 1; j < count; j++, next_pfn++) | |
1370 | if (page_to_pfn(pages[j]) != next_pfn) | |
1371 | break; | |
1372 | ||
1373 | len = (j - i) << PAGE_SHIFT; | |
c9b24996 | 1374 | ret = iommu_map(mapping->domain, iova, phys, len, |
7d2822df | 1375 | __dma_info_to_prot(DMA_BIDIRECTIONAL, attrs)); |
4ce63fcd MS |
1376 | if (ret < 0) |
1377 | goto fail; | |
1378 | iova += len; | |
1379 | i = j; | |
1380 | } | |
1381 | return dma_addr; | |
1382 | fail: | |
1383 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1384 | __free_iova(mapping, dma_addr, size); | |
72fd97bf | 1385 | return DMA_MAPPING_ERROR; |
4ce63fcd MS |
1386 | } |
1387 | ||
1388 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1389 | { | |
89cfdb19 | 1390 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1391 | |
1392 | /* | |
1393 | * add optional in-page offset from iova to size and align | |
1394 | * result to page size | |
1395 | */ | |
1396 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1397 | iova &= PAGE_MASK; | |
1398 | ||
1399 | iommu_unmap(mapping->domain, iova, size); | |
1400 | __free_iova(mapping, iova, size); | |
1401 | return 0; | |
1402 | } | |
1403 | ||
665bad7b HD |
1404 | static struct page **__atomic_get_pages(void *addr) |
1405 | { | |
36d0fd21 LA |
1406 | struct page *page; |
1407 | phys_addr_t phys; | |
1408 | ||
1409 | phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr); | |
1410 | page = phys_to_page(phys); | |
665bad7b | 1411 | |
36d0fd21 | 1412 | return (struct page **)page; |
665bad7b HD |
1413 | } |
1414 | ||
00085f1e | 1415 | static struct page **__iommu_get_pages(void *cpu_addr, unsigned long attrs) |
e9da6e99 | 1416 | { |
665bad7b HD |
1417 | if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) |
1418 | return __atomic_get_pages(cpu_addr); | |
1419 | ||
00085f1e | 1420 | if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) |
955c757e MS |
1421 | return cpu_addr; |
1422 | ||
5cf45379 | 1423 | return dma_common_find_pages(cpu_addr); |
e9da6e99 MS |
1424 | } |
1425 | ||
56506822 | 1426 | static void *__iommu_alloc_simple(struct device *dev, size_t size, gfp_t gfp, |
7d2822df S |
1427 | dma_addr_t *handle, int coherent_flag, |
1428 | unsigned long attrs) | |
479ed93a HD |
1429 | { |
1430 | struct page *page; | |
1431 | void *addr; | |
1432 | ||
56506822 GC |
1433 | if (coherent_flag == COHERENT) |
1434 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
1435 | else | |
1436 | addr = __alloc_from_pool(size, &page); | |
479ed93a HD |
1437 | if (!addr) |
1438 | return NULL; | |
1439 | ||
7d2822df | 1440 | *handle = __iommu_create_mapping(dev, &page, size, attrs); |
72fd97bf | 1441 | if (*handle == DMA_MAPPING_ERROR) |
479ed93a HD |
1442 | goto err_mapping; |
1443 | ||
1444 | return addr; | |
1445 | ||
1446 | err_mapping: | |
1447 | __free_from_pool(addr, size); | |
1448 | return NULL; | |
1449 | } | |
1450 | ||
d5898291 | 1451 | static void __iommu_free_atomic(struct device *dev, void *cpu_addr, |
56506822 | 1452 | dma_addr_t handle, size_t size, int coherent_flag) |
479ed93a HD |
1453 | { |
1454 | __iommu_remove_mapping(dev, handle, size); | |
56506822 GC |
1455 | if (coherent_flag == COHERENT) |
1456 | __dma_free_buffer(virt_to_page(cpu_addr), size); | |
1457 | else | |
1458 | __free_from_pool(cpu_addr, size); | |
479ed93a HD |
1459 | } |
1460 | ||
56506822 | 1461 | static void *__arm_iommu_alloc_attrs(struct device *dev, size_t size, |
00085f1e | 1462 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs, |
56506822 | 1463 | int coherent_flag) |
4ce63fcd | 1464 | { |
71b55663 | 1465 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
4ce63fcd MS |
1466 | struct page **pages; |
1467 | void *addr = NULL; | |
1468 | ||
72fd97bf | 1469 | *handle = DMA_MAPPING_ERROR; |
4ce63fcd MS |
1470 | size = PAGE_ALIGN(size); |
1471 | ||
56506822 GC |
1472 | if (coherent_flag == COHERENT || !gfpflags_allow_blocking(gfp)) |
1473 | return __iommu_alloc_simple(dev, size, gfp, handle, | |
7d2822df | 1474 | coherent_flag, attrs); |
479ed93a | 1475 | |
5b91a98c RZ |
1476 | /* |
1477 | * Following is a work-around (a.k.a. hack) to prevent pages | |
1478 | * with __GFP_COMP being passed to split_page() which cannot | |
1479 | * handle them. The real problem is that this flag probably | |
1480 | * should be 0 on ARM as it is not supported on this | |
1481 | * platform; see CONFIG_HUGETLBFS. | |
1482 | */ | |
1483 | gfp &= ~(__GFP_COMP); | |
1484 | ||
56506822 | 1485 | pages = __iommu_alloc_buffer(dev, size, gfp, attrs, coherent_flag); |
4ce63fcd MS |
1486 | if (!pages) |
1487 | return NULL; | |
1488 | ||
7d2822df | 1489 | *handle = __iommu_create_mapping(dev, pages, size, attrs); |
72fd97bf | 1490 | if (*handle == DMA_MAPPING_ERROR) |
4ce63fcd MS |
1491 | goto err_buffer; |
1492 | ||
00085f1e | 1493 | if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) |
955c757e MS |
1494 | return pages; |
1495 | ||
78406ff5 | 1496 | addr = dma_common_pages_remap(pages, size, prot, |
e9da6e99 | 1497 | __builtin_return_address(0)); |
4ce63fcd MS |
1498 | if (!addr) |
1499 | goto err_mapping; | |
1500 | ||
1501 | return addr; | |
1502 | ||
1503 | err_mapping: | |
1504 | __iommu_remove_mapping(dev, *handle, size); | |
1505 | err_buffer: | |
549a17e4 | 1506 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1507 | return NULL; |
1508 | } | |
1509 | ||
56506822 | 1510 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
00085f1e | 1511 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs) |
56506822 GC |
1512 | { |
1513 | return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, NORMAL); | |
1514 | } | |
1515 | ||
1516 | static void *arm_coherent_iommu_alloc_attrs(struct device *dev, size_t size, | |
00085f1e | 1517 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs) |
56506822 GC |
1518 | { |
1519 | return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, COHERENT); | |
1520 | } | |
1521 | ||
1522 | static int __arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
4ce63fcd | 1523 | void *cpu_addr, dma_addr_t dma_addr, size_t size, |
00085f1e | 1524 | unsigned long attrs) |
4ce63fcd | 1525 | { |
955c757e | 1526 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
371f0f08 | 1527 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
6248461d | 1528 | int err; |
4ce63fcd | 1529 | |
e9da6e99 MS |
1530 | if (!pages) |
1531 | return -ENXIO; | |
4ce63fcd | 1532 | |
6248461d | 1533 | if (vma->vm_pgoff >= nr_pages) |
371f0f08 MS |
1534 | return -ENXIO; |
1535 | ||
6248461d SJ |
1536 | err = vm_map_pages(vma, pages, nr_pages); |
1537 | if (err) | |
1538 | pr_err("Remapping memory failed: %d\n", err); | |
7e312103 | 1539 | |
6248461d | 1540 | return err; |
4ce63fcd | 1541 | } |
56506822 GC |
1542 | static int arm_iommu_mmap_attrs(struct device *dev, |
1543 | struct vm_area_struct *vma, void *cpu_addr, | |
00085f1e | 1544 | dma_addr_t dma_addr, size_t size, unsigned long attrs) |
56506822 GC |
1545 | { |
1546 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
1547 | ||
1548 | return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs); | |
1549 | } | |
1550 | ||
1551 | static int arm_coherent_iommu_mmap_attrs(struct device *dev, | |
1552 | struct vm_area_struct *vma, void *cpu_addr, | |
00085f1e | 1553 | dma_addr_t dma_addr, size_t size, unsigned long attrs) |
56506822 GC |
1554 | { |
1555 | return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs); | |
1556 | } | |
4ce63fcd MS |
1557 | |
1558 | /* | |
1559 | * free a page as defined by the above mapping. | |
1560 | * Must not be called with IRQs disabled. | |
1561 | */ | |
17fe8684 | 1562 | static void __arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 1563 | dma_addr_t handle, unsigned long attrs, int coherent_flag) |
4ce63fcd | 1564 | { |
836bfa0d | 1565 | struct page **pages; |
4ce63fcd MS |
1566 | size = PAGE_ALIGN(size); |
1567 | ||
56506822 GC |
1568 | if (coherent_flag == COHERENT || __in_atomic_pool(cpu_addr, size)) { |
1569 | __iommu_free_atomic(dev, cpu_addr, handle, size, coherent_flag); | |
e9da6e99 | 1570 | return; |
4ce63fcd | 1571 | } |
e9da6e99 | 1572 | |
836bfa0d YC |
1573 | pages = __iommu_get_pages(cpu_addr, attrs); |
1574 | if (!pages) { | |
1575 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
479ed93a HD |
1576 | return; |
1577 | } | |
1578 | ||
fe9041c2 | 1579 | if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0) |
51231740 | 1580 | dma_common_free_remap(cpu_addr, size); |
e9da6e99 MS |
1581 | |
1582 | __iommu_remove_mapping(dev, handle, size); | |
549a17e4 | 1583 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1584 | } |
1585 | ||
17fe8684 BD |
1586 | static void arm_iommu_free_attrs(struct device *dev, size_t size, |
1587 | void *cpu_addr, dma_addr_t handle, | |
1588 | unsigned long attrs) | |
56506822 GC |
1589 | { |
1590 | __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, NORMAL); | |
1591 | } | |
1592 | ||
17fe8684 | 1593 | static void arm_coherent_iommu_free_attrs(struct device *dev, size_t size, |
00085f1e | 1594 | void *cpu_addr, dma_addr_t handle, unsigned long attrs) |
56506822 GC |
1595 | { |
1596 | __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, COHERENT); | |
1597 | } | |
1598 | ||
dc2832e1 MS |
1599 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1600 | void *cpu_addr, dma_addr_t dma_addr, | |
00085f1e | 1601 | size_t size, unsigned long attrs) |
dc2832e1 MS |
1602 | { |
1603 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1604 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1605 | ||
1606 | if (!pages) | |
1607 | return -ENXIO; | |
1608 | ||
1609 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1610 | GFP_KERNEL); | |
4ce63fcd MS |
1611 | } |
1612 | ||
1613 | /* | |
1614 | * Map a part of the scatter-gather list into contiguous io address space | |
1615 | */ | |
1616 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1617 | size_t size, dma_addr_t *handle, | |
00085f1e | 1618 | enum dma_data_direction dir, unsigned long attrs, |
0fa478df | 1619 | bool is_coherent) |
4ce63fcd | 1620 | { |
89cfdb19 | 1621 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1622 | dma_addr_t iova, iova_base; |
1623 | int ret = 0; | |
1624 | unsigned int count; | |
1625 | struct scatterlist *s; | |
c9b24996 | 1626 | int prot; |
4ce63fcd MS |
1627 | |
1628 | size = PAGE_ALIGN(size); | |
72fd97bf | 1629 | *handle = DMA_MAPPING_ERROR; |
4ce63fcd MS |
1630 | |
1631 | iova_base = iova = __alloc_iova(mapping, size); | |
72fd97bf | 1632 | if (iova == DMA_MAPPING_ERROR) |
4ce63fcd MS |
1633 | return -ENOMEM; |
1634 | ||
1635 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
3e6110fd | 1636 | phys_addr_t phys = page_to_phys(sg_page(s)); |
4ce63fcd MS |
1637 | unsigned int len = PAGE_ALIGN(s->offset + s->length); |
1638 | ||
00085f1e | 1639 | if (!is_coherent && (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
4ce63fcd MS |
1640 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1641 | ||
7d2822df | 1642 | prot = __dma_info_to_prot(dir, attrs); |
c9b24996 AH |
1643 | |
1644 | ret = iommu_map(mapping->domain, iova, phys, len, prot); | |
4ce63fcd MS |
1645 | if (ret < 0) |
1646 | goto fail; | |
1647 | count += len >> PAGE_SHIFT; | |
1648 | iova += len; | |
1649 | } | |
1650 | *handle = iova_base; | |
1651 | ||
1652 | return 0; | |
1653 | fail: | |
1654 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1655 | __free_iova(mapping, iova_base, size); | |
1656 | return ret; | |
1657 | } | |
1658 | ||
0fa478df | 1659 | static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
00085f1e | 1660 | enum dma_data_direction dir, unsigned long attrs, |
0fa478df | 1661 | bool is_coherent) |
4ce63fcd MS |
1662 | { |
1663 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1664 | int i, count = 0; | |
1665 | unsigned int offset = s->offset; | |
1666 | unsigned int size = s->offset + s->length; | |
1667 | unsigned int max = dma_get_max_seg_size(dev); | |
1668 | ||
1669 | for (i = 1; i < nents; i++) { | |
1670 | s = sg_next(s); | |
1671 | ||
72fd97bf | 1672 | s->dma_address = DMA_MAPPING_ERROR; |
4ce63fcd MS |
1673 | s->dma_length = 0; |
1674 | ||
1675 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1676 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
0fa478df | 1677 | dir, attrs, is_coherent) < 0) |
4ce63fcd MS |
1678 | goto bad_mapping; |
1679 | ||
1680 | dma->dma_address += offset; | |
1681 | dma->dma_length = size - offset; | |
1682 | ||
1683 | size = offset = s->offset; | |
1684 | start = s; | |
1685 | dma = sg_next(dma); | |
1686 | count += 1; | |
1687 | } | |
1688 | size += s->length; | |
1689 | } | |
0fa478df RH |
1690 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs, |
1691 | is_coherent) < 0) | |
4ce63fcd MS |
1692 | goto bad_mapping; |
1693 | ||
1694 | dma->dma_address += offset; | |
1695 | dma->dma_length = size - offset; | |
1696 | ||
1697 | return count+1; | |
1698 | ||
1699 | bad_mapping: | |
1700 | for_each_sg(sg, s, count, i) | |
1701 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1702 | return 0; | |
1703 | } | |
1704 | ||
1705 | /** | |
0fa478df | 1706 | * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA |
4ce63fcd MS |
1707 | * @dev: valid struct device pointer |
1708 | * @sg: list of buffers | |
0fa478df RH |
1709 | * @nents: number of buffers to map |
1710 | * @dir: DMA transfer direction | |
4ce63fcd | 1711 | * |
0fa478df RH |
1712 | * Map a set of i/o coherent buffers described by scatterlist in streaming |
1713 | * mode for DMA. The scatter gather list elements are merged together (if | |
1714 | * possible) and tagged with the appropriate dma address and length. They are | |
1715 | * obtained via sg_dma_{address,length}. | |
4ce63fcd | 1716 | */ |
17fe8684 | 1717 | static int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg, |
00085f1e | 1718 | int nents, enum dma_data_direction dir, unsigned long attrs) |
0fa478df RH |
1719 | { |
1720 | return __iommu_map_sg(dev, sg, nents, dir, attrs, true); | |
1721 | } | |
1722 | ||
1723 | /** | |
1724 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1725 | * @dev: valid struct device pointer | |
1726 | * @sg: list of buffers | |
1727 | * @nents: number of buffers to map | |
1728 | * @dir: DMA transfer direction | |
1729 | * | |
1730 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1731 | * The scatter gather list elements are merged together (if possible) and | |
1732 | * tagged with the appropriate dma address and length. They are obtained via | |
1733 | * sg_dma_{address,length}. | |
1734 | */ | |
17fe8684 | 1735 | static int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, |
00085f1e | 1736 | int nents, enum dma_data_direction dir, unsigned long attrs) |
0fa478df RH |
1737 | { |
1738 | return __iommu_map_sg(dev, sg, nents, dir, attrs, false); | |
1739 | } | |
1740 | ||
1741 | static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
00085f1e KK |
1742 | int nents, enum dma_data_direction dir, |
1743 | unsigned long attrs, bool is_coherent) | |
4ce63fcd MS |
1744 | { |
1745 | struct scatterlist *s; | |
1746 | int i; | |
1747 | ||
1748 | for_each_sg(sg, s, nents, i) { | |
1749 | if (sg_dma_len(s)) | |
1750 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1751 | sg_dma_len(s)); | |
00085f1e | 1752 | if (!is_coherent && (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
4ce63fcd MS |
1753 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1754 | s->length, dir); | |
1755 | } | |
1756 | } | |
1757 | ||
0fa478df RH |
1758 | /** |
1759 | * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1760 | * @dev: valid struct device pointer | |
1761 | * @sg: list of buffers | |
1762 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1763 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1764 | * | |
1765 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1766 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1767 | */ | |
17fe8684 BD |
1768 | static void arm_coherent_iommu_unmap_sg(struct device *dev, |
1769 | struct scatterlist *sg, int nents, enum dma_data_direction dir, | |
00085f1e | 1770 | unsigned long attrs) |
0fa478df RH |
1771 | { |
1772 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, true); | |
1773 | } | |
1774 | ||
1775 | /** | |
1776 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1777 | * @dev: valid struct device pointer | |
1778 | * @sg: list of buffers | |
1779 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1780 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1781 | * | |
1782 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1783 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1784 | */ | |
17fe8684 BD |
1785 | static void arm_iommu_unmap_sg(struct device *dev, |
1786 | struct scatterlist *sg, int nents, | |
1787 | enum dma_data_direction dir, | |
1788 | unsigned long attrs) | |
0fa478df RH |
1789 | { |
1790 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, false); | |
1791 | } | |
1792 | ||
4ce63fcd MS |
1793 | /** |
1794 | * arm_iommu_sync_sg_for_cpu | |
1795 | * @dev: valid struct device pointer | |
1796 | * @sg: list of buffers | |
1797 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1798 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1799 | */ | |
17fe8684 BD |
1800 | static void arm_iommu_sync_sg_for_cpu(struct device *dev, |
1801 | struct scatterlist *sg, | |
4ce63fcd MS |
1802 | int nents, enum dma_data_direction dir) |
1803 | { | |
1804 | struct scatterlist *s; | |
1805 | int i; | |
1806 | ||
1807 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1808 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1809 | |
1810 | } | |
1811 | ||
1812 | /** | |
1813 | * arm_iommu_sync_sg_for_device | |
1814 | * @dev: valid struct device pointer | |
1815 | * @sg: list of buffers | |
1816 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1817 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1818 | */ | |
17fe8684 BD |
1819 | static void arm_iommu_sync_sg_for_device(struct device *dev, |
1820 | struct scatterlist *sg, | |
4ce63fcd MS |
1821 | int nents, enum dma_data_direction dir) |
1822 | { | |
1823 | struct scatterlist *s; | |
1824 | int i; | |
1825 | ||
1826 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1827 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1828 | } |
1829 | ||
1830 | ||
1831 | /** | |
0fa478df | 1832 | * arm_coherent_iommu_map_page |
4ce63fcd MS |
1833 | * @dev: valid struct device pointer |
1834 | * @page: page that buffer resides in | |
1835 | * @offset: offset into page for start of buffer | |
1836 | * @size: size of buffer to map | |
1837 | * @dir: DMA transfer direction | |
1838 | * | |
0fa478df | 1839 | * Coherent IOMMU aware version of arm_dma_map_page() |
4ce63fcd | 1840 | */ |
0fa478df | 1841 | static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page, |
4ce63fcd | 1842 | unsigned long offset, size_t size, enum dma_data_direction dir, |
00085f1e | 1843 | unsigned long attrs) |
4ce63fcd | 1844 | { |
89cfdb19 | 1845 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd | 1846 | dma_addr_t dma_addr; |
13987d68 | 1847 | int ret, prot, len = PAGE_ALIGN(size + offset); |
4ce63fcd | 1848 | |
4ce63fcd | 1849 | dma_addr = __alloc_iova(mapping, len); |
72fd97bf | 1850 | if (dma_addr == DMA_MAPPING_ERROR) |
4ce63fcd MS |
1851 | return dma_addr; |
1852 | ||
7d2822df | 1853 | prot = __dma_info_to_prot(dir, attrs); |
13987d68 WD |
1854 | |
1855 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot); | |
4ce63fcd MS |
1856 | if (ret < 0) |
1857 | goto fail; | |
1858 | ||
1859 | return dma_addr + offset; | |
1860 | fail: | |
1861 | __free_iova(mapping, dma_addr, len); | |
72fd97bf | 1862 | return DMA_MAPPING_ERROR; |
4ce63fcd MS |
1863 | } |
1864 | ||
0fa478df RH |
1865 | /** |
1866 | * arm_iommu_map_page | |
1867 | * @dev: valid struct device pointer | |
1868 | * @page: page that buffer resides in | |
1869 | * @offset: offset into page for start of buffer | |
1870 | * @size: size of buffer to map | |
1871 | * @dir: DMA transfer direction | |
1872 | * | |
1873 | * IOMMU aware version of arm_dma_map_page() | |
1874 | */ | |
1875 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1876 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
00085f1e | 1877 | unsigned long attrs) |
0fa478df | 1878 | { |
00085f1e | 1879 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
0fa478df RH |
1880 | __dma_page_cpu_to_dev(page, offset, size, dir); |
1881 | ||
1882 | return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs); | |
1883 | } | |
1884 | ||
1885 | /** | |
1886 | * arm_coherent_iommu_unmap_page | |
1887 | * @dev: valid struct device pointer | |
1888 | * @handle: DMA address of buffer | |
1889 | * @size: size of buffer (same as passed to dma_map_page) | |
1890 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1891 | * | |
1892 | * Coherent IOMMU aware version of arm_dma_unmap_page() | |
1893 | */ | |
1894 | static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
00085f1e | 1895 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
0fa478df | 1896 | { |
89cfdb19 | 1897 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
0fa478df | 1898 | dma_addr_t iova = handle & PAGE_MASK; |
0fa478df RH |
1899 | int offset = handle & ~PAGE_MASK; |
1900 | int len = PAGE_ALIGN(size + offset); | |
1901 | ||
1902 | if (!iova) | |
1903 | return; | |
1904 | ||
1905 | iommu_unmap(mapping->domain, iova, len); | |
1906 | __free_iova(mapping, iova, len); | |
1907 | } | |
1908 | ||
4ce63fcd MS |
1909 | /** |
1910 | * arm_iommu_unmap_page | |
1911 | * @dev: valid struct device pointer | |
1912 | * @handle: DMA address of buffer | |
1913 | * @size: size of buffer (same as passed to dma_map_page) | |
1914 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1915 | * | |
1916 | * IOMMU aware version of arm_dma_unmap_page() | |
1917 | */ | |
1918 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
00085f1e | 1919 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
4ce63fcd | 1920 | { |
89cfdb19 | 1921 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1922 | dma_addr_t iova = handle & PAGE_MASK; |
1923 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1924 | int offset = handle & ~PAGE_MASK; | |
1925 | int len = PAGE_ALIGN(size + offset); | |
1926 | ||
1927 | if (!iova) | |
1928 | return; | |
1929 | ||
00085f1e | 1930 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
4ce63fcd MS |
1931 | __dma_page_dev_to_cpu(page, offset, size, dir); |
1932 | ||
1933 | iommu_unmap(mapping->domain, iova, len); | |
1934 | __free_iova(mapping, iova, len); | |
1935 | } | |
1936 | ||
24ed5d2c NS |
1937 | /** |
1938 | * arm_iommu_map_resource - map a device resource for DMA | |
1939 | * @dev: valid struct device pointer | |
1940 | * @phys_addr: physical address of resource | |
1941 | * @size: size of resource to map | |
1942 | * @dir: DMA transfer direction | |
1943 | */ | |
1944 | static dma_addr_t arm_iommu_map_resource(struct device *dev, | |
1945 | phys_addr_t phys_addr, size_t size, | |
1946 | enum dma_data_direction dir, unsigned long attrs) | |
1947 | { | |
1948 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
1949 | dma_addr_t dma_addr; | |
1950 | int ret, prot; | |
1951 | phys_addr_t addr = phys_addr & PAGE_MASK; | |
1952 | unsigned int offset = phys_addr & ~PAGE_MASK; | |
1953 | size_t len = PAGE_ALIGN(size + offset); | |
1954 | ||
1955 | dma_addr = __alloc_iova(mapping, len); | |
72fd97bf | 1956 | if (dma_addr == DMA_MAPPING_ERROR) |
24ed5d2c NS |
1957 | return dma_addr; |
1958 | ||
7d2822df | 1959 | prot = __dma_info_to_prot(dir, attrs) | IOMMU_MMIO; |
24ed5d2c NS |
1960 | |
1961 | ret = iommu_map(mapping->domain, dma_addr, addr, len, prot); | |
1962 | if (ret < 0) | |
1963 | goto fail; | |
1964 | ||
1965 | return dma_addr + offset; | |
1966 | fail: | |
1967 | __free_iova(mapping, dma_addr, len); | |
72fd97bf | 1968 | return DMA_MAPPING_ERROR; |
24ed5d2c NS |
1969 | } |
1970 | ||
1971 | /** | |
1972 | * arm_iommu_unmap_resource - unmap a device DMA resource | |
1973 | * @dev: valid struct device pointer | |
1974 | * @dma_handle: DMA address to resource | |
1975 | * @size: size of resource to map | |
1976 | * @dir: DMA transfer direction | |
1977 | */ | |
1978 | static void arm_iommu_unmap_resource(struct device *dev, dma_addr_t dma_handle, | |
1979 | size_t size, enum dma_data_direction dir, | |
1980 | unsigned long attrs) | |
1981 | { | |
1982 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
1983 | dma_addr_t iova = dma_handle & PAGE_MASK; | |
1984 | unsigned int offset = dma_handle & ~PAGE_MASK; | |
1985 | size_t len = PAGE_ALIGN(size + offset); | |
1986 | ||
1987 | if (!iova) | |
1988 | return; | |
1989 | ||
1990 | iommu_unmap(mapping->domain, iova, len); | |
1991 | __free_iova(mapping, iova, len); | |
1992 | } | |
1993 | ||
4ce63fcd MS |
1994 | static void arm_iommu_sync_single_for_cpu(struct device *dev, |
1995 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1996 | { | |
89cfdb19 | 1997 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1998 | dma_addr_t iova = handle & PAGE_MASK; |
1999 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
2000 | unsigned int offset = handle & ~PAGE_MASK; | |
2001 | ||
2002 | if (!iova) | |
2003 | return; | |
2004 | ||
0fa478df | 2005 | __dma_page_dev_to_cpu(page, offset, size, dir); |
4ce63fcd MS |
2006 | } |
2007 | ||
2008 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
2009 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
2010 | { | |
89cfdb19 | 2011 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
2012 | dma_addr_t iova = handle & PAGE_MASK; |
2013 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
2014 | unsigned int offset = handle & ~PAGE_MASK; | |
2015 | ||
2016 | if (!iova) | |
2017 | return; | |
2018 | ||
2019 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
2020 | } | |
2021 | ||
17fe8684 | 2022 | static const struct dma_map_ops iommu_ops = { |
4ce63fcd MS |
2023 | .alloc = arm_iommu_alloc_attrs, |
2024 | .free = arm_iommu_free_attrs, | |
2025 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 2026 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
2027 | |
2028 | .map_page = arm_iommu_map_page, | |
2029 | .unmap_page = arm_iommu_unmap_page, | |
2030 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
2031 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
2032 | ||
2033 | .map_sg = arm_iommu_map_sg, | |
2034 | .unmap_sg = arm_iommu_unmap_sg, | |
2035 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
2036 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
24ed5d2c NS |
2037 | |
2038 | .map_resource = arm_iommu_map_resource, | |
2039 | .unmap_resource = arm_iommu_unmap_resource, | |
9eef8b8c | 2040 | |
418a7a7e | 2041 | .dma_supported = arm_dma_supported, |
4ce63fcd MS |
2042 | }; |
2043 | ||
17fe8684 | 2044 | static const struct dma_map_ops iommu_coherent_ops = { |
56506822 GC |
2045 | .alloc = arm_coherent_iommu_alloc_attrs, |
2046 | .free = arm_coherent_iommu_free_attrs, | |
2047 | .mmap = arm_coherent_iommu_mmap_attrs, | |
0fa478df RH |
2048 | .get_sgtable = arm_iommu_get_sgtable, |
2049 | ||
2050 | .map_page = arm_coherent_iommu_map_page, | |
2051 | .unmap_page = arm_coherent_iommu_unmap_page, | |
2052 | ||
2053 | .map_sg = arm_coherent_iommu_map_sg, | |
2054 | .unmap_sg = arm_coherent_iommu_unmap_sg, | |
24ed5d2c NS |
2055 | |
2056 | .map_resource = arm_iommu_map_resource, | |
2057 | .unmap_resource = arm_iommu_unmap_resource, | |
9eef8b8c | 2058 | |
418a7a7e | 2059 | .dma_supported = arm_dma_supported, |
0fa478df RH |
2060 | }; |
2061 | ||
4ce63fcd MS |
2062 | /** |
2063 | * arm_iommu_create_mapping | |
2064 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
2065 | * @base: start address of the valid IO address space | |
68efd7d2 | 2066 | * @size: maximum size of the valid IO address space |
4ce63fcd MS |
2067 | * |
2068 | * Creates a mapping structure which holds information about used/unused | |
2069 | * IO address ranges, which is required to perform memory allocation and | |
2070 | * mapping with IOMMU aware functions. | |
2071 | * | |
2072 | * The client device need to be attached to the mapping with | |
2073 | * arm_iommu_attach_device function. | |
2074 | */ | |
2075 | struct dma_iommu_mapping * | |
1424532b | 2076 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size) |
4ce63fcd | 2077 | { |
68efd7d2 MS |
2078 | unsigned int bits = size >> PAGE_SHIFT; |
2079 | unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); | |
4ce63fcd | 2080 | struct dma_iommu_mapping *mapping; |
68efd7d2 | 2081 | int extensions = 1; |
4ce63fcd MS |
2082 | int err = -ENOMEM; |
2083 | ||
1424532b MS |
2084 | /* currently only 32-bit DMA address space is supported */ |
2085 | if (size > DMA_BIT_MASK(32) + 1) | |
2086 | return ERR_PTR(-ERANGE); | |
2087 | ||
68efd7d2 | 2088 | if (!bitmap_size) |
4ce63fcd MS |
2089 | return ERR_PTR(-EINVAL); |
2090 | ||
68efd7d2 MS |
2091 | if (bitmap_size > PAGE_SIZE) { |
2092 | extensions = bitmap_size / PAGE_SIZE; | |
2093 | bitmap_size = PAGE_SIZE; | |
2094 | } | |
2095 | ||
4ce63fcd MS |
2096 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); |
2097 | if (!mapping) | |
2098 | goto err; | |
2099 | ||
68efd7d2 | 2100 | mapping->bitmap_size = bitmap_size; |
6396bb22 KC |
2101 | mapping->bitmaps = kcalloc(extensions, sizeof(unsigned long *), |
2102 | GFP_KERNEL); | |
4d852ef8 | 2103 | if (!mapping->bitmaps) |
4ce63fcd MS |
2104 | goto err2; |
2105 | ||
68efd7d2 | 2106 | mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL); |
4d852ef8 AH |
2107 | if (!mapping->bitmaps[0]) |
2108 | goto err3; | |
2109 | ||
2110 | mapping->nr_bitmaps = 1; | |
2111 | mapping->extensions = extensions; | |
4ce63fcd | 2112 | mapping->base = base; |
68efd7d2 | 2113 | mapping->bits = BITS_PER_BYTE * bitmap_size; |
4d852ef8 | 2114 | |
4ce63fcd MS |
2115 | spin_lock_init(&mapping->lock); |
2116 | ||
2117 | mapping->domain = iommu_domain_alloc(bus); | |
2118 | if (!mapping->domain) | |
4d852ef8 | 2119 | goto err4; |
4ce63fcd MS |
2120 | |
2121 | kref_init(&mapping->kref); | |
2122 | return mapping; | |
4d852ef8 AH |
2123 | err4: |
2124 | kfree(mapping->bitmaps[0]); | |
4ce63fcd | 2125 | err3: |
4d852ef8 | 2126 | kfree(mapping->bitmaps); |
4ce63fcd MS |
2127 | err2: |
2128 | kfree(mapping); | |
2129 | err: | |
2130 | return ERR_PTR(err); | |
2131 | } | |
18177d12 | 2132 | EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); |
4ce63fcd MS |
2133 | |
2134 | static void release_iommu_mapping(struct kref *kref) | |
2135 | { | |
4d852ef8 | 2136 | int i; |
4ce63fcd MS |
2137 | struct dma_iommu_mapping *mapping = |
2138 | container_of(kref, struct dma_iommu_mapping, kref); | |
2139 | ||
2140 | iommu_domain_free(mapping->domain); | |
4d852ef8 AH |
2141 | for (i = 0; i < mapping->nr_bitmaps; i++) |
2142 | kfree(mapping->bitmaps[i]); | |
2143 | kfree(mapping->bitmaps); | |
4ce63fcd MS |
2144 | kfree(mapping); |
2145 | } | |
2146 | ||
4d852ef8 AH |
2147 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) |
2148 | { | |
2149 | int next_bitmap; | |
2150 | ||
462859aa | 2151 | if (mapping->nr_bitmaps >= mapping->extensions) |
4d852ef8 AH |
2152 | return -EINVAL; |
2153 | ||
2154 | next_bitmap = mapping->nr_bitmaps; | |
2155 | mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size, | |
2156 | GFP_ATOMIC); | |
2157 | if (!mapping->bitmaps[next_bitmap]) | |
2158 | return -ENOMEM; | |
2159 | ||
2160 | mapping->nr_bitmaps++; | |
2161 | ||
2162 | return 0; | |
2163 | } | |
2164 | ||
4ce63fcd MS |
2165 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) |
2166 | { | |
2167 | if (mapping) | |
2168 | kref_put(&mapping->kref, release_iommu_mapping); | |
2169 | } | |
18177d12 | 2170 | EXPORT_SYMBOL_GPL(arm_iommu_release_mapping); |
4ce63fcd | 2171 | |
eab8d653 LP |
2172 | static int __arm_iommu_attach_device(struct device *dev, |
2173 | struct dma_iommu_mapping *mapping) | |
2174 | { | |
2175 | int err; | |
2176 | ||
2177 | err = iommu_attach_device(mapping->domain, dev); | |
2178 | if (err) | |
2179 | return err; | |
2180 | ||
2181 | kref_get(&mapping->kref); | |
89cfdb19 | 2182 | to_dma_iommu_mapping(dev) = mapping; |
eab8d653 LP |
2183 | |
2184 | pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
2185 | return 0; | |
2186 | } | |
2187 | ||
4ce63fcd MS |
2188 | /** |
2189 | * arm_iommu_attach_device | |
2190 | * @dev: valid struct device pointer | |
2191 | * @mapping: io address space mapping structure (returned from | |
2192 | * arm_iommu_create_mapping) | |
2193 | * | |
eab8d653 LP |
2194 | * Attaches specified io address space mapping to the provided device. |
2195 | * This replaces the dma operations (dma_map_ops pointer) with the | |
2196 | * IOMMU aware version. | |
2197 | * | |
4bb25789 WD |
2198 | * More than one client might be attached to the same io address space |
2199 | * mapping. | |
4ce63fcd MS |
2200 | */ |
2201 | int arm_iommu_attach_device(struct device *dev, | |
2202 | struct dma_iommu_mapping *mapping) | |
2203 | { | |
2204 | int err; | |
2205 | ||
eab8d653 | 2206 | err = __arm_iommu_attach_device(dev, mapping); |
4ce63fcd MS |
2207 | if (err) |
2208 | return err; | |
2209 | ||
eab8d653 | 2210 | set_dma_ops(dev, &iommu_ops); |
4ce63fcd MS |
2211 | return 0; |
2212 | } | |
18177d12 | 2213 | EXPORT_SYMBOL_GPL(arm_iommu_attach_device); |
4ce63fcd | 2214 | |
d3e01c51 S |
2215 | /** |
2216 | * arm_iommu_detach_device | |
2217 | * @dev: valid struct device pointer | |
2218 | * | |
2219 | * Detaches the provided device from a previously attached map. | |
4a4d68fc | 2220 | * This overwrites the dma_ops pointer with appropriate non-IOMMU ops. |
d3e01c51 S |
2221 | */ |
2222 | void arm_iommu_detach_device(struct device *dev) | |
6fe36758 HD |
2223 | { |
2224 | struct dma_iommu_mapping *mapping; | |
2225 | ||
2226 | mapping = to_dma_iommu_mapping(dev); | |
2227 | if (!mapping) { | |
2228 | dev_warn(dev, "Not attached\n"); | |
2229 | return; | |
2230 | } | |
2231 | ||
2232 | iommu_detach_device(mapping->domain, dev); | |
2233 | kref_put(&mapping->kref, release_iommu_mapping); | |
89cfdb19 | 2234 | to_dma_iommu_mapping(dev) = NULL; |
1874619a | 2235 | set_dma_ops(dev, arm_get_dma_map_ops(dev->archdata.dma_coherent)); |
6fe36758 HD |
2236 | |
2237 | pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev)); | |
2238 | } | |
18177d12 | 2239 | EXPORT_SYMBOL_GPL(arm_iommu_detach_device); |
6fe36758 | 2240 | |
5299709d | 2241 | static const struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent) |
4bb25789 WD |
2242 | { |
2243 | return coherent ? &iommu_coherent_ops : &iommu_ops; | |
2244 | } | |
2245 | ||
2246 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
53c92d79 | 2247 | const struct iommu_ops *iommu) |
4bb25789 WD |
2248 | { |
2249 | struct dma_iommu_mapping *mapping; | |
2250 | ||
2251 | if (!iommu) | |
2252 | return false; | |
2253 | ||
2254 | mapping = arm_iommu_create_mapping(dev->bus, dma_base, size); | |
2255 | if (IS_ERR(mapping)) { | |
2256 | pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n", | |
2257 | size, dev_name(dev)); | |
2258 | return false; | |
2259 | } | |
2260 | ||
eab8d653 | 2261 | if (__arm_iommu_attach_device(dev, mapping)) { |
4bb25789 WD |
2262 | pr_warn("Failed to attached device %s to IOMMU_mapping\n", |
2263 | dev_name(dev)); | |
2264 | arm_iommu_release_mapping(mapping); | |
2265 | return false; | |
2266 | } | |
2267 | ||
2268 | return true; | |
2269 | } | |
2270 | ||
2271 | static void arm_teardown_iommu_dma_ops(struct device *dev) | |
2272 | { | |
89cfdb19 | 2273 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4bb25789 | 2274 | |
c2273a18 WD |
2275 | if (!mapping) |
2276 | return; | |
2277 | ||
d3e01c51 | 2278 | arm_iommu_detach_device(dev); |
4bb25789 WD |
2279 | arm_iommu_release_mapping(mapping); |
2280 | } | |
2281 | ||
2282 | #else | |
2283 | ||
2284 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
53c92d79 | 2285 | const struct iommu_ops *iommu) |
4bb25789 WD |
2286 | { |
2287 | return false; | |
2288 | } | |
2289 | ||
2290 | static void arm_teardown_iommu_dma_ops(struct device *dev) { } | |
2291 | ||
2292 | #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops | |
2293 | ||
2294 | #endif /* CONFIG_ARM_DMA_USE_IOMMU */ | |
2295 | ||
4bb25789 | 2296 | void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, |
53c92d79 | 2297 | const struct iommu_ops *iommu, bool coherent) |
4bb25789 | 2298 | { |
5299709d | 2299 | const struct dma_map_ops *dma_ops; |
4bb25789 | 2300 | |
6f51ee70 | 2301 | dev->archdata.dma_coherent = coherent; |
ad3c7b18 CH |
2302 | #ifdef CONFIG_SWIOTLB |
2303 | dev->dma_coherent = coherent; | |
2304 | #endif | |
26b37b94 LP |
2305 | |
2306 | /* | |
2307 | * Don't override the dma_ops if they have already been set. Ideally | |
2308 | * this should be the only location where dma_ops are set, remove this | |
2309 | * check when all other callers of set_dma_ops will have disappeared. | |
2310 | */ | |
2311 | if (dev->dma_ops) | |
2312 | return; | |
2313 | ||
4bb25789 WD |
2314 | if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) |
2315 | dma_ops = arm_get_iommu_dma_map_ops(coherent); | |
2316 | else | |
2317 | dma_ops = arm_get_dma_map_ops(coherent); | |
2318 | ||
2319 | set_dma_ops(dev, dma_ops); | |
e0586326 SS |
2320 | |
2321 | #ifdef CONFIG_XEN | |
8e23c82c | 2322 | if (xen_initial_domain()) |
0e0d26e7 | 2323 | dev->dma_ops = &xen_swiotlb_dma_ops; |
e0586326 | 2324 | #endif |
a93a121a | 2325 | dev->archdata.dma_ops_setup = true; |
4bb25789 WD |
2326 | } |
2327 | ||
2328 | void arch_teardown_dma_ops(struct device *dev) | |
2329 | { | |
a93a121a LP |
2330 | if (!dev->archdata.dma_ops_setup) |
2331 | return; | |
2332 | ||
4bb25789 | 2333 | arm_teardown_iommu_dma_ops(dev); |
fc67e6f1 RM |
2334 | /* Let arch_setup_dma_ops() start again from scratch upon re-probe */ |
2335 | set_dma_ops(dev, NULL); | |
4bb25789 | 2336 | } |
ad3c7b18 CH |
2337 | |
2338 | #ifdef CONFIG_SWIOTLB | |
2339 | void arch_sync_dma_for_device(struct device *dev, phys_addr_t paddr, | |
2340 | size_t size, enum dma_data_direction dir) | |
2341 | { | |
2342 | __dma_page_cpu_to_dev(phys_to_page(paddr), paddr & (PAGE_SIZE - 1), | |
2343 | size, dir); | |
2344 | } | |
2345 | ||
2346 | void arch_sync_dma_for_cpu(struct device *dev, phys_addr_t paddr, | |
2347 | size_t size, enum dma_data_direction dir) | |
2348 | { | |
2349 | __dma_page_dev_to_cpu(phys_to_page(paddr), paddr & (PAGE_SIZE - 1), | |
2350 | size, dir); | |
2351 | } | |
2352 | ||
2353 | long arch_dma_coherent_to_pfn(struct device *dev, void *cpu_addr, | |
2354 | dma_addr_t dma_addr) | |
2355 | { | |
2356 | return dma_to_pfn(dev, dma_addr); | |
2357 | } | |
2358 | ||
ad3c7b18 CH |
2359 | void *arch_dma_alloc(struct device *dev, size_t size, dma_addr_t *dma_handle, |
2360 | gfp_t gfp, unsigned long attrs) | |
2361 | { | |
2362 | return __dma_alloc(dev, size, dma_handle, gfp, | |
2363 | __get_dma_pgprot(attrs, PAGE_KERNEL), false, | |
2364 | attrs, __builtin_return_address(0)); | |
2365 | } | |
2366 | ||
2367 | void arch_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
2368 | dma_addr_t dma_handle, unsigned long attrs) | |
2369 | { | |
2370 | __arm_dma_free(dev, size, cpu_addr, dma_handle, attrs, false); | |
2371 | } | |
2372 | #endif /* CONFIG_SWIOTLB */ |