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Commit | Line | Data |
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1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
11a5aa32 | 12 | #include <linux/bootmem.h> |
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/mm.h> | |
36d0fd21 | 15 | #include <linux/genalloc.h> |
5a0e3ad6 | 16 | #include <linux/gfp.h> |
1da177e4 LT |
17 | #include <linux/errno.h> |
18 | #include <linux/list.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/dma-mapping.h> | |
c7909509 | 22 | #include <linux/dma-contiguous.h> |
39af22a7 | 23 | #include <linux/highmem.h> |
c7909509 | 24 | #include <linux/memblock.h> |
99d1717d | 25 | #include <linux/slab.h> |
4ce63fcd | 26 | #include <linux/iommu.h> |
e9da6e99 | 27 | #include <linux/io.h> |
4ce63fcd | 28 | #include <linux/vmalloc.h> |
158e8bfe | 29 | #include <linux/sizes.h> |
a254129e | 30 | #include <linux/cma.h> |
1da177e4 | 31 | |
23759dc6 | 32 | #include <asm/memory.h> |
43377453 | 33 | #include <asm/highmem.h> |
1da177e4 | 34 | #include <asm/cacheflush.h> |
1da177e4 | 35 | #include <asm/tlbflush.h> |
99d1717d | 36 | #include <asm/mach/arch.h> |
4ce63fcd | 37 | #include <asm/dma-iommu.h> |
c7909509 MS |
38 | #include <asm/mach/map.h> |
39 | #include <asm/system_info.h> | |
40 | #include <asm/dma-contiguous.h> | |
37134cd5 | 41 | |
022ae537 RK |
42 | #include "mm.h" |
43 | ||
15237e1f MS |
44 | /* |
45 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
46 | * is either exclusively owned by the CPU (and therefore may be accessed | |
47 | * by it) or exclusively owned by the DMA device. These helper functions | |
48 | * represent the transitions between these two ownership states. | |
49 | * | |
50 | * Note, however, that on later ARMs, this notion does not work due to | |
51 | * speculative prefetches. We model our approach on the assumption that | |
52 | * the CPU does do speculative prefetches, which means we clean caches | |
53 | * before transfers and delay cache invalidation until transfer completion. | |
54 | * | |
15237e1f | 55 | */ |
51fde349 | 56 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 57 | size_t, enum dma_data_direction); |
51fde349 | 58 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
59 | size_t, enum dma_data_direction); |
60 | ||
2dc6a016 MS |
61 | /** |
62 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
63 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
64 | * @page: page that buffer resides in | |
65 | * @offset: offset into page for start of buffer | |
66 | * @size: size of buffer to map | |
67 | * @dir: DMA transfer direction | |
68 | * | |
69 | * Ensure that any data held in the cache is appropriately discarded | |
70 | * or written back. | |
71 | * | |
72 | * The device owns this memory once this call has completed. The CPU | |
73 | * can regain ownership by calling dma_unmap_page(). | |
74 | */ | |
51fde349 | 75 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
76 | unsigned long offset, size_t size, enum dma_data_direction dir, |
77 | struct dma_attrs *attrs) | |
78 | { | |
dd37e940 | 79 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
80 | __dma_page_cpu_to_dev(page, offset, size, dir); |
81 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
82 | } |
83 | ||
dd37e940 RH |
84 | static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page, |
85 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
86 | struct dma_attrs *attrs) | |
87 | { | |
88 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
89 | } | |
90 | ||
2dc6a016 MS |
91 | /** |
92 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
93 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
94 | * @handle: DMA address of buffer | |
95 | * @size: size of buffer (same as passed to dma_map_page) | |
96 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
97 | * | |
98 | * Unmap a page streaming mode DMA translation. The handle and size | |
99 | * must match what was provided in the previous dma_map_page() call. | |
100 | * All other usages are undefined. | |
101 | * | |
102 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
103 | * whatever the device wrote there. | |
104 | */ | |
51fde349 | 105 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
106 | size_t size, enum dma_data_direction dir, |
107 | struct dma_attrs *attrs) | |
108 | { | |
dd37e940 | 109 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
110 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
111 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
112 | } |
113 | ||
51fde349 | 114 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
115 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
116 | { | |
117 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
118 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 119 | __dma_page_dev_to_cpu(page, offset, size, dir); |
2dc6a016 MS |
120 | } |
121 | ||
51fde349 | 122 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
123 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
124 | { | |
125 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
126 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 127 | __dma_page_cpu_to_dev(page, offset, size, dir); |
2dc6a016 MS |
128 | } |
129 | ||
2dc6a016 | 130 | struct dma_map_ops arm_dma_ops = { |
f99d6034 MS |
131 | .alloc = arm_dma_alloc, |
132 | .free = arm_dma_free, | |
133 | .mmap = arm_dma_mmap, | |
dc2832e1 | 134 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
135 | .map_page = arm_dma_map_page, |
136 | .unmap_page = arm_dma_unmap_page, | |
137 | .map_sg = arm_dma_map_sg, | |
138 | .unmap_sg = arm_dma_unmap_sg, | |
139 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
140 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
141 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
142 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
143 | .set_dma_mask = arm_dma_set_mask, | |
144 | }; | |
145 | EXPORT_SYMBOL(arm_dma_ops); | |
146 | ||
dd37e940 RH |
147 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, |
148 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs); | |
149 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
150 | dma_addr_t handle, struct dma_attrs *attrs); | |
151 | ||
152 | struct dma_map_ops arm_coherent_dma_ops = { | |
153 | .alloc = arm_coherent_dma_alloc, | |
154 | .free = arm_coherent_dma_free, | |
155 | .mmap = arm_dma_mmap, | |
156 | .get_sgtable = arm_dma_get_sgtable, | |
157 | .map_page = arm_coherent_dma_map_page, | |
158 | .map_sg = arm_dma_map_sg, | |
159 | .set_dma_mask = arm_dma_set_mask, | |
160 | }; | |
161 | EXPORT_SYMBOL(arm_coherent_dma_ops); | |
162 | ||
9f28cde0 RK |
163 | static int __dma_supported(struct device *dev, u64 mask, bool warn) |
164 | { | |
165 | unsigned long max_dma_pfn; | |
166 | ||
167 | /* | |
168 | * If the mask allows for more memory than we can address, | |
169 | * and we actually have that much memory, then we must | |
170 | * indicate that DMA to this device is not supported. | |
171 | */ | |
172 | if (sizeof(mask) != sizeof(dma_addr_t) && | |
173 | mask > (dma_addr_t)~0 && | |
174 | dma_to_pfn(dev, ~0) < max_pfn) { | |
175 | if (warn) { | |
176 | dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", | |
177 | mask); | |
178 | dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n"); | |
179 | } | |
180 | return 0; | |
181 | } | |
182 | ||
183 | max_dma_pfn = min(max_pfn, arm_dma_pfn_limit); | |
184 | ||
185 | /* | |
186 | * Translate the device's DMA mask to a PFN limit. This | |
187 | * PFN number includes the page which we can DMA to. | |
188 | */ | |
189 | if (dma_to_pfn(dev, mask) < max_dma_pfn) { | |
190 | if (warn) | |
191 | dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", | |
192 | mask, | |
193 | dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, | |
194 | max_dma_pfn + 1); | |
195 | return 0; | |
196 | } | |
197 | ||
198 | return 1; | |
199 | } | |
200 | ||
ab6494f0 CM |
201 | static u64 get_coherent_dma_mask(struct device *dev) |
202 | { | |
4dcfa600 | 203 | u64 mask = (u64)DMA_BIT_MASK(32); |
ab6494f0 CM |
204 | |
205 | if (dev) { | |
206 | mask = dev->coherent_dma_mask; | |
207 | ||
208 | /* | |
209 | * Sanity check the DMA mask - it must be non-zero, and | |
210 | * must be able to be satisfied by a DMA allocation. | |
211 | */ | |
212 | if (mask == 0) { | |
213 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
214 | return 0; | |
215 | } | |
216 | ||
9f28cde0 | 217 | if (!__dma_supported(dev, mask, true)) |
ab6494f0 | 218 | return 0; |
ab6494f0 | 219 | } |
1da177e4 | 220 | |
ab6494f0 CM |
221 | return mask; |
222 | } | |
223 | ||
c7909509 MS |
224 | static void __dma_clear_buffer(struct page *page, size_t size) |
225 | { | |
c7909509 MS |
226 | /* |
227 | * Ensure that the allocated pages are zeroed, and that any data | |
228 | * lurking in the kernel direct-mapped region is invalidated. | |
229 | */ | |
9848e48f MS |
230 | if (PageHighMem(page)) { |
231 | phys_addr_t base = __pfn_to_phys(page_to_pfn(page)); | |
232 | phys_addr_t end = base + size; | |
233 | while (size > 0) { | |
234 | void *ptr = kmap_atomic(page); | |
235 | memset(ptr, 0, PAGE_SIZE); | |
236 | dmac_flush_range(ptr, ptr + PAGE_SIZE); | |
237 | kunmap_atomic(ptr); | |
238 | page++; | |
239 | size -= PAGE_SIZE; | |
240 | } | |
241 | outer_flush_range(base, end); | |
242 | } else { | |
243 | void *ptr = page_address(page); | |
4ce63fcd MS |
244 | memset(ptr, 0, size); |
245 | dmac_flush_range(ptr, ptr + size); | |
246 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
247 | } | |
c7909509 MS |
248 | } |
249 | ||
7a9a32a9 RK |
250 | /* |
251 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
252 | * specified gfp mask. Note that 'size' must be page aligned. | |
253 | */ | |
254 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
255 | { | |
256 | unsigned long order = get_order(size); | |
257 | struct page *page, *p, *e; | |
7a9a32a9 RK |
258 | |
259 | page = alloc_pages(gfp, order); | |
260 | if (!page) | |
261 | return NULL; | |
262 | ||
263 | /* | |
264 | * Now split the huge page and free the excess pages | |
265 | */ | |
266 | split_page(page, order); | |
267 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
268 | __free_page(p); | |
269 | ||
c7909509 | 270 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
271 | |
272 | return page; | |
273 | } | |
274 | ||
275 | /* | |
276 | * Free a DMA buffer. 'size' must be page aligned. | |
277 | */ | |
278 | static void __dma_free_buffer(struct page *page, size_t size) | |
279 | { | |
280 | struct page *e = page + (size >> PAGE_SHIFT); | |
281 | ||
282 | while (page < e) { | |
283 | __free_page(page); | |
284 | page++; | |
285 | } | |
286 | } | |
287 | ||
ab6494f0 | 288 | #ifdef CONFIG_MMU |
a5e9d38b | 289 | |
e9da6e99 | 290 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
9848e48f | 291 | pgprot_t prot, struct page **ret_page, |
6e8266e3 | 292 | const void *caller, bool want_vaddr); |
99d1717d | 293 | |
e9da6e99 MS |
294 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
295 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 296 | const void *caller, bool want_vaddr); |
99d1717d | 297 | |
e9da6e99 MS |
298 | static void * |
299 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
300 | const void *caller) | |
99d1717d | 301 | { |
e9da6e99 MS |
302 | /* |
303 | * DMA allocation can be mapped to user space, so lets | |
304 | * set VM_USERMAP flags too. | |
305 | */ | |
513510dd LA |
306 | return dma_common_contiguous_remap(page, size, |
307 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
308 | prot, caller); | |
99d1717d | 309 | } |
1da177e4 | 310 | |
e9da6e99 | 311 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 312 | { |
513510dd LA |
313 | dma_common_free_remap(cpu_addr, size, |
314 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
88c58f3b | 315 | } |
88c58f3b | 316 | |
6e5267aa | 317 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
36d0fd21 | 318 | static struct gen_pool *atomic_pool; |
6e5267aa | 319 | |
36d0fd21 | 320 | static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE; |
c7909509 MS |
321 | |
322 | static int __init early_coherent_pool(char *p) | |
323 | { | |
36d0fd21 | 324 | atomic_pool_size = memparse(p, &p); |
c7909509 MS |
325 | return 0; |
326 | } | |
327 | early_param("coherent_pool", early_coherent_pool); | |
328 | ||
6e5267aa MS |
329 | void __init init_dma_coherent_pool_size(unsigned long size) |
330 | { | |
331 | /* | |
332 | * Catch any attempt to set the pool size too late. | |
333 | */ | |
36d0fd21 | 334 | BUG_ON(atomic_pool); |
6e5267aa MS |
335 | |
336 | /* | |
337 | * Set architecture specific coherent pool size only if | |
338 | * it has not been changed by kernel command line parameter. | |
339 | */ | |
36d0fd21 LA |
340 | if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE) |
341 | atomic_pool_size = size; | |
6e5267aa MS |
342 | } |
343 | ||
c7909509 MS |
344 | /* |
345 | * Initialise the coherent pool for atomic allocations. | |
346 | */ | |
e9da6e99 | 347 | static int __init atomic_pool_init(void) |
c7909509 | 348 | { |
71b55663 | 349 | pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); |
9d1400cf | 350 | gfp_t gfp = GFP_KERNEL | GFP_DMA; |
c7909509 MS |
351 | struct page *page; |
352 | void *ptr; | |
c7909509 | 353 | |
36d0fd21 LA |
354 | atomic_pool = gen_pool_create(PAGE_SHIFT, -1); |
355 | if (!atomic_pool) | |
356 | goto out; | |
6b3fe472 | 357 | |
e464ef16 | 358 | if (dev_get_cma_area(NULL)) |
36d0fd21 | 359 | ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot, |
6e8266e3 | 360 | &page, atomic_pool_init, true); |
e9da6e99 | 361 | else |
36d0fd21 | 362 | ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot, |
6e8266e3 | 363 | &page, atomic_pool_init, true); |
c7909509 | 364 | if (ptr) { |
36d0fd21 LA |
365 | int ret; |
366 | ||
367 | ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr, | |
368 | page_to_phys(page), | |
369 | atomic_pool_size, -1); | |
370 | if (ret) | |
371 | goto destroy_genpool; | |
372 | ||
373 | gen_pool_set_algo(atomic_pool, | |
374 | gen_pool_first_fit_order_align, | |
375 | (void *)PAGE_SHIFT); | |
376 | pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n", | |
377 | atomic_pool_size / 1024); | |
c7909509 MS |
378 | return 0; |
379 | } | |
ec10665c | 380 | |
36d0fd21 LA |
381 | destroy_genpool: |
382 | gen_pool_destroy(atomic_pool); | |
383 | atomic_pool = NULL; | |
384 | out: | |
385 | pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n", | |
386 | atomic_pool_size / 1024); | |
c7909509 MS |
387 | return -ENOMEM; |
388 | } | |
389 | /* | |
390 | * CMA is activated by core_initcall, so we must be called after it. | |
391 | */ | |
e9da6e99 | 392 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
393 | |
394 | struct dma_contig_early_reserve { | |
395 | phys_addr_t base; | |
396 | unsigned long size; | |
397 | }; | |
398 | ||
399 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
400 | ||
401 | static int dma_mmu_remap_num __initdata; | |
402 | ||
403 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
404 | { | |
405 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
406 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
407 | dma_mmu_remap_num++; | |
408 | } | |
409 | ||
410 | void __init dma_contiguous_remap(void) | |
411 | { | |
412 | int i; | |
413 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
414 | phys_addr_t start = dma_mmu_remap[i].base; | |
415 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
416 | struct map_desc map; | |
417 | unsigned long addr; | |
418 | ||
419 | if (end > arm_lowmem_limit) | |
420 | end = arm_lowmem_limit; | |
421 | if (start >= end) | |
39f78e70 | 422 | continue; |
c7909509 MS |
423 | |
424 | map.pfn = __phys_to_pfn(start); | |
425 | map.virtual = __phys_to_virt(start); | |
426 | map.length = end - start; | |
427 | map.type = MT_MEMORY_DMA_READY; | |
428 | ||
429 | /* | |
6b076991 RK |
430 | * Clear previous low-memory mapping to ensure that the |
431 | * TLB does not see any conflicting entries, then flush | |
432 | * the TLB of the old entries before creating new mappings. | |
433 | * | |
434 | * This ensures that any speculatively loaded TLB entries | |
435 | * (even though they may be rare) can not cause any problems, | |
436 | * and ensures that this code is architecturally compliant. | |
c7909509 MS |
437 | */ |
438 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 439 | addr += PMD_SIZE) |
c7909509 MS |
440 | pmd_clear(pmd_off_k(addr)); |
441 | ||
6b076991 RK |
442 | flush_tlb_kernel_range(__phys_to_virt(start), |
443 | __phys_to_virt(end)); | |
444 | ||
c7909509 MS |
445 | iotable_init(&map, 1); |
446 | } | |
447 | } | |
448 | ||
c7909509 MS |
449 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
450 | void *data) | |
451 | { | |
452 | struct page *page = virt_to_page(addr); | |
453 | pgprot_t prot = *(pgprot_t *)data; | |
454 | ||
455 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
456 | return 0; | |
457 | } | |
458 | ||
459 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
460 | { | |
461 | unsigned long start = (unsigned long) page_address(page); | |
462 | unsigned end = start + size; | |
463 | ||
464 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
c7909509 MS |
465 | flush_tlb_kernel_range(start, end); |
466 | } | |
467 | ||
468 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
469 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 470 | const void *caller, bool want_vaddr) |
c7909509 MS |
471 | { |
472 | struct page *page; | |
6e8266e3 | 473 | void *ptr = NULL; |
c7909509 MS |
474 | page = __dma_alloc_buffer(dev, size, gfp); |
475 | if (!page) | |
476 | return NULL; | |
6e8266e3 CC |
477 | if (!want_vaddr) |
478 | goto out; | |
c7909509 MS |
479 | |
480 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
481 | if (!ptr) { | |
482 | __dma_free_buffer(page, size); | |
483 | return NULL; | |
484 | } | |
485 | ||
6e8266e3 | 486 | out: |
c7909509 MS |
487 | *ret_page = page; |
488 | return ptr; | |
489 | } | |
490 | ||
e9da6e99 | 491 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 492 | { |
36d0fd21 | 493 | unsigned long val; |
e9da6e99 | 494 | void *ptr = NULL; |
c7909509 | 495 | |
36d0fd21 | 496 | if (!atomic_pool) { |
e9da6e99 | 497 | WARN(1, "coherent pool not initialised!\n"); |
c7909509 MS |
498 | return NULL; |
499 | } | |
500 | ||
36d0fd21 LA |
501 | val = gen_pool_alloc(atomic_pool, size); |
502 | if (val) { | |
503 | phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val); | |
504 | ||
505 | *ret_page = phys_to_page(phys); | |
506 | ptr = (void *)val; | |
c7909509 | 507 | } |
e9da6e99 MS |
508 | |
509 | return ptr; | |
c7909509 MS |
510 | } |
511 | ||
21d0a759 HD |
512 | static bool __in_atomic_pool(void *start, size_t size) |
513 | { | |
36d0fd21 | 514 | return addr_in_gen_pool(atomic_pool, (unsigned long)start, size); |
21d0a759 HD |
515 | } |
516 | ||
e9da6e99 | 517 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 518 | { |
21d0a759 | 519 | if (!__in_atomic_pool(start, size)) |
c7909509 MS |
520 | return 0; |
521 | ||
36d0fd21 | 522 | gen_pool_free(atomic_pool, (unsigned long)start, size); |
e9da6e99 | 523 | |
c7909509 MS |
524 | return 1; |
525 | } | |
526 | ||
527 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
9848e48f | 528 | pgprot_t prot, struct page **ret_page, |
6e8266e3 | 529 | const void *caller, bool want_vaddr) |
c7909509 MS |
530 | { |
531 | unsigned long order = get_order(size); | |
532 | size_t count = size >> PAGE_SHIFT; | |
533 | struct page *page; | |
6e8266e3 | 534 | void *ptr = NULL; |
c7909509 MS |
535 | |
536 | page = dma_alloc_from_contiguous(dev, count, order); | |
537 | if (!page) | |
538 | return NULL; | |
539 | ||
540 | __dma_clear_buffer(page, size); | |
c7909509 | 541 | |
6e8266e3 CC |
542 | if (!want_vaddr) |
543 | goto out; | |
544 | ||
9848e48f MS |
545 | if (PageHighMem(page)) { |
546 | ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller); | |
547 | if (!ptr) { | |
548 | dma_release_from_contiguous(dev, page, count); | |
549 | return NULL; | |
550 | } | |
551 | } else { | |
552 | __dma_remap(page, size, prot); | |
553 | ptr = page_address(page); | |
554 | } | |
6e8266e3 CC |
555 | |
556 | out: | |
c7909509 | 557 | *ret_page = page; |
9848e48f | 558 | return ptr; |
c7909509 MS |
559 | } |
560 | ||
561 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
6e8266e3 | 562 | void *cpu_addr, size_t size, bool want_vaddr) |
c7909509 | 563 | { |
6e8266e3 CC |
564 | if (want_vaddr) { |
565 | if (PageHighMem(page)) | |
566 | __dma_free_remap(cpu_addr, size); | |
567 | else | |
568 | __dma_remap(page, size, PAGE_KERNEL); | |
569 | } | |
c7909509 MS |
570 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); |
571 | } | |
572 | ||
f99d6034 MS |
573 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
574 | { | |
575 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
576 | pgprot_writecombine(prot) : | |
577 | pgprot_dmacoherent(prot); | |
578 | return prot; | |
579 | } | |
580 | ||
c7909509 MS |
581 | #define nommu() 0 |
582 | ||
ab6494f0 | 583 | #else /* !CONFIG_MMU */ |
695ae0af | 584 | |
c7909509 MS |
585 | #define nommu() 1 |
586 | ||
6e8266e3 CC |
587 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
588 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL | |
e9da6e99 | 589 | #define __alloc_from_pool(size, ret_page) NULL |
6e8266e3 | 590 | #define __alloc_from_contiguous(dev, size, prot, ret, c, wv) NULL |
c7909509 | 591 | #define __free_from_pool(cpu_addr, size) 0 |
6e8266e3 | 592 | #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0) |
c7909509 | 593 | #define __dma_free_remap(cpu_addr, size) do { } while (0) |
31ebf944 RK |
594 | |
595 | #endif /* CONFIG_MMU */ | |
596 | ||
c7909509 MS |
597 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
598 | struct page **ret_page) | |
ab6494f0 | 599 | { |
c7909509 MS |
600 | struct page *page; |
601 | page = __dma_alloc_buffer(dev, size, gfp); | |
602 | if (!page) | |
603 | return NULL; | |
604 | ||
605 | *ret_page = page; | |
606 | return page_address(page); | |
607 | } | |
608 | ||
609 | ||
610 | ||
611 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
6e8266e3 CC |
612 | gfp_t gfp, pgprot_t prot, bool is_coherent, |
613 | struct dma_attrs *attrs, const void *caller) | |
c7909509 MS |
614 | { |
615 | u64 mask = get_coherent_dma_mask(dev); | |
3dd7ea92 | 616 | struct page *page = NULL; |
31ebf944 | 617 | void *addr; |
6e8266e3 | 618 | bool want_vaddr; |
ab6494f0 | 619 | |
c7909509 MS |
620 | #ifdef CONFIG_DMA_API_DEBUG |
621 | u64 limit = (mask + 1) & ~mask; | |
622 | if (limit && size >= limit) { | |
623 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
624 | size, mask); | |
625 | return NULL; | |
626 | } | |
627 | #endif | |
628 | ||
629 | if (!mask) | |
630 | return NULL; | |
631 | ||
632 | if (mask < 0xffffffffULL) | |
633 | gfp |= GFP_DMA; | |
634 | ||
ea2e7057 SB |
635 | /* |
636 | * Following is a work-around (a.k.a. hack) to prevent pages | |
637 | * with __GFP_COMP being passed to split_page() which cannot | |
638 | * handle them. The real problem is that this flag probably | |
639 | * should be 0 on ARM as it is not supported on this | |
640 | * platform; see CONFIG_HUGETLBFS. | |
641 | */ | |
642 | gfp &= ~(__GFP_COMP); | |
643 | ||
553ac788 | 644 | *handle = DMA_ERROR_CODE; |
04da5694 | 645 | size = PAGE_ALIGN(size); |
6e8266e3 | 646 | want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs); |
ab6494f0 | 647 | |
dd37e940 | 648 | if (is_coherent || nommu()) |
c7909509 | 649 | addr = __alloc_simple_buffer(dev, size, gfp, &page); |
633dc92a | 650 | else if (!(gfp & __GFP_WAIT)) |
e9da6e99 | 651 | addr = __alloc_from_pool(size, &page); |
e464ef16 | 652 | else if (!dev_get_cma_area(dev)) |
6e8266e3 | 653 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller, want_vaddr); |
31ebf944 | 654 | else |
6e8266e3 | 655 | addr = __alloc_from_contiguous(dev, size, prot, &page, caller, want_vaddr); |
695ae0af | 656 | |
6e8266e3 | 657 | if (page) |
9eedd963 | 658 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
695ae0af | 659 | |
6e8266e3 | 660 | return want_vaddr ? addr : page; |
31ebf944 | 661 | } |
1da177e4 LT |
662 | |
663 | /* | |
664 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
665 | * virtual and bus address for that space. | |
666 | */ | |
f99d6034 MS |
667 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
668 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 669 | { |
0ea1ec71 | 670 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
1fe53268 DB |
671 | void *memory; |
672 | ||
673 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
674 | return memory; | |
675 | ||
dd37e940 | 676 | return __dma_alloc(dev, size, handle, gfp, prot, false, |
6e8266e3 | 677 | attrs, __builtin_return_address(0)); |
dd37e940 RH |
678 | } |
679 | ||
680 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, | |
681 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
682 | { | |
0ea1ec71 | 683 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
dd37e940 RH |
684 | void *memory; |
685 | ||
686 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
687 | return memory; | |
688 | ||
689 | return __dma_alloc(dev, size, handle, gfp, prot, true, | |
6e8266e3 | 690 | attrs, __builtin_return_address(0)); |
1da177e4 | 691 | } |
1da177e4 LT |
692 | |
693 | /* | |
f99d6034 | 694 | * Create userspace mapping for the DMA-coherent memory. |
1da177e4 | 695 | */ |
f99d6034 MS |
696 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
697 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
698 | struct dma_attrs *attrs) | |
1da177e4 | 699 | { |
ab6494f0 CM |
700 | int ret = -ENXIO; |
701 | #ifdef CONFIG_MMU | |
50262a4b MS |
702 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
703 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 704 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
705 | unsigned long off = vma->vm_pgoff; |
706 | ||
f99d6034 MS |
707 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
708 | ||
47142f07 MS |
709 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
710 | return ret; | |
711 | ||
50262a4b MS |
712 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
713 | ret = remap_pfn_range(vma, vma->vm_start, | |
714 | pfn + off, | |
715 | vma->vm_end - vma->vm_start, | |
716 | vma->vm_page_prot); | |
717 | } | |
ab6494f0 | 718 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
719 | |
720 | return ret; | |
721 | } | |
722 | ||
1da177e4 | 723 | /* |
c7909509 | 724 | * Free a buffer as defined by the above mapping. |
1da177e4 | 725 | */ |
dd37e940 RH |
726 | static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
727 | dma_addr_t handle, struct dma_attrs *attrs, | |
728 | bool is_coherent) | |
1da177e4 | 729 | { |
c7909509 | 730 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
6e8266e3 | 731 | bool want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs); |
5edf71ae | 732 | |
1fe53268 DB |
733 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
734 | return; | |
735 | ||
3e82d012 RK |
736 | size = PAGE_ALIGN(size); |
737 | ||
dd37e940 | 738 | if (is_coherent || nommu()) { |
c7909509 | 739 | __dma_free_buffer(page, size); |
d9e0d149 AK |
740 | } else if (__free_from_pool(cpu_addr, size)) { |
741 | return; | |
e464ef16 | 742 | } else if (!dev_get_cma_area(dev)) { |
6e8266e3 CC |
743 | if (want_vaddr) |
744 | __dma_free_remap(cpu_addr, size); | |
c7909509 MS |
745 | __dma_free_buffer(page, size); |
746 | } else { | |
c7909509 MS |
747 | /* |
748 | * Non-atomic allocations cannot be freed with IRQs disabled | |
749 | */ | |
750 | WARN_ON(irqs_disabled()); | |
6e8266e3 | 751 | __free_from_contiguous(dev, page, cpu_addr, size, want_vaddr); |
c7909509 | 752 | } |
1da177e4 | 753 | } |
afd1a321 | 754 | |
dd37e940 RH |
755 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
756 | dma_addr_t handle, struct dma_attrs *attrs) | |
757 | { | |
758 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, false); | |
759 | } | |
760 | ||
761 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
762 | dma_addr_t handle, struct dma_attrs *attrs) | |
763 | { | |
764 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, true); | |
765 | } | |
766 | ||
dc2832e1 MS |
767 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
768 | void *cpu_addr, dma_addr_t handle, size_t size, | |
769 | struct dma_attrs *attrs) | |
770 | { | |
771 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
772 | int ret; | |
773 | ||
774 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
775 | if (unlikely(ret)) | |
776 | return ret; | |
777 | ||
778 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
779 | return 0; | |
780 | } | |
781 | ||
4ea0d737 | 782 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
783 | size_t size, enum dma_data_direction dir, |
784 | void (*op)(const void *, size_t, int)) | |
43377453 | 785 | { |
15653371 RK |
786 | unsigned long pfn; |
787 | size_t left = size; | |
788 | ||
789 | pfn = page_to_pfn(page) + offset / PAGE_SIZE; | |
790 | offset %= PAGE_SIZE; | |
791 | ||
43377453 NP |
792 | /* |
793 | * A single sg entry may refer to multiple physically contiguous | |
794 | * pages. But we still need to process highmem pages individually. | |
795 | * If highmem is not configured then the bulk of this loop gets | |
796 | * optimized out. | |
797 | */ | |
43377453 NP |
798 | do { |
799 | size_t len = left; | |
93f1d629 RK |
800 | void *vaddr; |
801 | ||
15653371 RK |
802 | page = pfn_to_page(pfn); |
803 | ||
93f1d629 | 804 | if (PageHighMem(page)) { |
15653371 | 805 | if (len + offset > PAGE_SIZE) |
93f1d629 | 806 | len = PAGE_SIZE - offset; |
dd0f67f4 JK |
807 | |
808 | if (cache_is_vipt_nonaliasing()) { | |
39af22a7 | 809 | vaddr = kmap_atomic(page); |
7e5a69e8 | 810 | op(vaddr + offset, len, dir); |
39af22a7 | 811 | kunmap_atomic(vaddr); |
dd0f67f4 JK |
812 | } else { |
813 | vaddr = kmap_high_get(page); | |
814 | if (vaddr) { | |
815 | op(vaddr + offset, len, dir); | |
816 | kunmap_high(page); | |
817 | } | |
43377453 | 818 | } |
93f1d629 RK |
819 | } else { |
820 | vaddr = page_address(page) + offset; | |
a9c9147e | 821 | op(vaddr, len, dir); |
43377453 | 822 | } |
43377453 | 823 | offset = 0; |
15653371 | 824 | pfn++; |
43377453 NP |
825 | left -= len; |
826 | } while (left); | |
827 | } | |
4ea0d737 | 828 | |
51fde349 MS |
829 | /* |
830 | * Make an area consistent for devices. | |
831 | * Note: Drivers should NOT use this function directly, as it will break | |
832 | * platforms with CONFIG_DMABOUNCE. | |
833 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
834 | */ | |
835 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
836 | size_t size, enum dma_data_direction dir) |
837 | { | |
2161c248 | 838 | phys_addr_t paddr; |
65af191a | 839 | |
a9c9147e | 840 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
841 | |
842 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
843 | if (dir == DMA_FROM_DEVICE) { |
844 | outer_inv_range(paddr, paddr + size); | |
845 | } else { | |
846 | outer_clean_range(paddr, paddr + size); | |
847 | } | |
848 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 849 | } |
4ea0d737 | 850 | |
51fde349 | 851 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
852 | size_t size, enum dma_data_direction dir) |
853 | { | |
2161c248 | 854 | phys_addr_t paddr = page_to_phys(page) + off; |
2ffe2da3 RK |
855 | |
856 | /* FIXME: non-speculating: not required */ | |
deace4a6 RK |
857 | /* in any case, don't bother invalidating if DMA to device */ |
858 | if (dir != DMA_TO_DEVICE) { | |
2ffe2da3 RK |
859 | outer_inv_range(paddr, paddr + size); |
860 | ||
deace4a6 RK |
861 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
862 | } | |
c0177800 CM |
863 | |
864 | /* | |
b2a234ed | 865 | * Mark the D-cache clean for these pages to avoid extra flushing. |
c0177800 | 866 | */ |
b2a234ed ML |
867 | if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) { |
868 | unsigned long pfn; | |
869 | size_t left = size; | |
870 | ||
871 | pfn = page_to_pfn(page) + off / PAGE_SIZE; | |
872 | off %= PAGE_SIZE; | |
873 | if (off) { | |
874 | pfn++; | |
875 | left -= PAGE_SIZE - off; | |
876 | } | |
877 | while (left >= PAGE_SIZE) { | |
878 | page = pfn_to_page(pfn++); | |
879 | set_bit(PG_dcache_clean, &page->flags); | |
880 | left -= PAGE_SIZE; | |
881 | } | |
882 | } | |
4ea0d737 | 883 | } |
43377453 | 884 | |
afd1a321 | 885 | /** |
2a550e73 | 886 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
887 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
888 | * @sg: list of buffers | |
889 | * @nents: number of buffers to map | |
890 | * @dir: DMA transfer direction | |
891 | * | |
892 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
893 | * This is the scatter-gather version of the dma_map_single interface. | |
894 | * Here the scatter gather list elements are each tagged with the | |
895 | * appropriate dma address and length. They are obtained via | |
896 | * sg_dma_{address,length}. | |
897 | * | |
898 | * Device ownership issues as mentioned for dma_map_single are the same | |
899 | * here. | |
900 | */ | |
2dc6a016 MS |
901 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
902 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 903 | { |
2a550e73 | 904 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 905 | struct scatterlist *s; |
01135d92 | 906 | int i, j; |
afd1a321 RK |
907 | |
908 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
909 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
910 | s->dma_length = s->length; | |
911 | #endif | |
2a550e73 MS |
912 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
913 | s->length, dir, attrs); | |
01135d92 RK |
914 | if (dma_mapping_error(dev, s->dma_address)) |
915 | goto bad_mapping; | |
afd1a321 | 916 | } |
afd1a321 | 917 | return nents; |
01135d92 RK |
918 | |
919 | bad_mapping: | |
920 | for_each_sg(sg, s, i, j) | |
2a550e73 | 921 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 922 | return 0; |
afd1a321 | 923 | } |
afd1a321 RK |
924 | |
925 | /** | |
2a550e73 | 926 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
927 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
928 | * @sg: list of buffers | |
0adfca6f | 929 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
930 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
931 | * | |
932 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
933 | * rules concerning calls here are the same as for dma_unmap_single(). | |
934 | */ | |
2dc6a016 MS |
935 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
936 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 937 | { |
2a550e73 | 938 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 939 | struct scatterlist *s; |
01135d92 | 940 | |
01135d92 | 941 | int i; |
24056f52 | 942 | |
01135d92 | 943 | for_each_sg(sg, s, nents, i) |
2a550e73 | 944 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 945 | } |
afd1a321 RK |
946 | |
947 | /** | |
2a550e73 | 948 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
949 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
950 | * @sg: list of buffers | |
951 | * @nents: number of buffers to map (returned from dma_map_sg) | |
952 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
953 | */ | |
2dc6a016 | 954 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
955 | int nents, enum dma_data_direction dir) |
956 | { | |
2a550e73 | 957 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
958 | struct scatterlist *s; |
959 | int i; | |
960 | ||
2a550e73 MS |
961 | for_each_sg(sg, s, nents, i) |
962 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
963 | dir); | |
afd1a321 | 964 | } |
afd1a321 RK |
965 | |
966 | /** | |
2a550e73 | 967 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
968 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
969 | * @sg: list of buffers | |
970 | * @nents: number of buffers to map (returned from dma_map_sg) | |
971 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
972 | */ | |
2dc6a016 | 973 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
974 | int nents, enum dma_data_direction dir) |
975 | { | |
2a550e73 | 976 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
977 | struct scatterlist *s; |
978 | int i; | |
979 | ||
2a550e73 MS |
980 | for_each_sg(sg, s, nents, i) |
981 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
982 | dir); | |
afd1a321 | 983 | } |
24056f52 | 984 | |
022ae537 RK |
985 | /* |
986 | * Return whether the given device DMA address mask can be supported | |
987 | * properly. For example, if your device can only drive the low 24-bits | |
988 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
989 | * to this function. | |
990 | */ | |
991 | int dma_supported(struct device *dev, u64 mask) | |
992 | { | |
9f28cde0 | 993 | return __dma_supported(dev, mask, false); |
022ae537 RK |
994 | } |
995 | EXPORT_SYMBOL(dma_supported); | |
996 | ||
87b54e78 | 997 | int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
998 | { |
999 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
1000 | return -EIO; | |
1001 | ||
022ae537 | 1002 | *dev->dma_mask = dma_mask; |
022ae537 RK |
1003 | |
1004 | return 0; | |
1005 | } | |
022ae537 | 1006 | |
24056f52 RK |
1007 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
1008 | ||
1009 | static int __init dma_debug_do_init(void) | |
1010 | { | |
1011 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
1012 | return 0; | |
1013 | } | |
1014 | fs_initcall(dma_debug_do_init); | |
4ce63fcd MS |
1015 | |
1016 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
1017 | ||
1018 | /* IOMMU */ | |
1019 | ||
4d852ef8 AH |
1020 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping); |
1021 | ||
4ce63fcd MS |
1022 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, |
1023 | size_t size) | |
1024 | { | |
1025 | unsigned int order = get_order(size); | |
1026 | unsigned int align = 0; | |
1027 | unsigned int count, start; | |
006f841d | 1028 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1029 | unsigned long flags; |
4d852ef8 AH |
1030 | dma_addr_t iova; |
1031 | int i; | |
4ce63fcd | 1032 | |
60460abf SWK |
1033 | if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT) |
1034 | order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT; | |
1035 | ||
68efd7d2 MS |
1036 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1037 | align = (1 << order) - 1; | |
4ce63fcd MS |
1038 | |
1039 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 AH |
1040 | for (i = 0; i < mapping->nr_bitmaps; i++) { |
1041 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1042 | mapping->bits, 0, count, align); | |
1043 | ||
1044 | if (start > mapping->bits) | |
1045 | continue; | |
1046 | ||
1047 | bitmap_set(mapping->bitmaps[i], start, count); | |
1048 | break; | |
4ce63fcd MS |
1049 | } |
1050 | ||
4d852ef8 AH |
1051 | /* |
1052 | * No unused range found. Try to extend the existing mapping | |
1053 | * and perform a second attempt to reserve an IO virtual | |
1054 | * address range of size bytes. | |
1055 | */ | |
1056 | if (i == mapping->nr_bitmaps) { | |
1057 | if (extend_iommu_mapping(mapping)) { | |
1058 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1059 | return DMA_ERROR_CODE; | |
1060 | } | |
1061 | ||
1062 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1063 | mapping->bits, 0, count, align); | |
1064 | ||
1065 | if (start > mapping->bits) { | |
1066 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1067 | return DMA_ERROR_CODE; | |
1068 | } | |
1069 | ||
1070 | bitmap_set(mapping->bitmaps[i], start, count); | |
1071 | } | |
4ce63fcd MS |
1072 | spin_unlock_irqrestore(&mapping->lock, flags); |
1073 | ||
006f841d | 1074 | iova = mapping->base + (mapping_size * i); |
68efd7d2 | 1075 | iova += start << PAGE_SHIFT; |
4d852ef8 AH |
1076 | |
1077 | return iova; | |
4ce63fcd MS |
1078 | } |
1079 | ||
1080 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
1081 | dma_addr_t addr, size_t size) | |
1082 | { | |
4d852ef8 | 1083 | unsigned int start, count; |
006f841d | 1084 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1085 | unsigned long flags; |
4d852ef8 AH |
1086 | dma_addr_t bitmap_base; |
1087 | u32 bitmap_index; | |
1088 | ||
1089 | if (!size) | |
1090 | return; | |
1091 | ||
006f841d | 1092 | bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size; |
4d852ef8 AH |
1093 | BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions); |
1094 | ||
006f841d | 1095 | bitmap_base = mapping->base + mapping_size * bitmap_index; |
4d852ef8 | 1096 | |
68efd7d2 | 1097 | start = (addr - bitmap_base) >> PAGE_SHIFT; |
4d852ef8 | 1098 | |
006f841d | 1099 | if (addr + size > bitmap_base + mapping_size) { |
4d852ef8 AH |
1100 | /* |
1101 | * The address range to be freed reaches into the iova | |
1102 | * range of the next bitmap. This should not happen as | |
1103 | * we don't allow this in __alloc_iova (at the | |
1104 | * moment). | |
1105 | */ | |
1106 | BUG(); | |
1107 | } else | |
68efd7d2 | 1108 | count = size >> PAGE_SHIFT; |
4ce63fcd MS |
1109 | |
1110 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 | 1111 | bitmap_clear(mapping->bitmaps[bitmap_index], start, count); |
4ce63fcd MS |
1112 | spin_unlock_irqrestore(&mapping->lock, flags); |
1113 | } | |
1114 | ||
549a17e4 MS |
1115 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, |
1116 | gfp_t gfp, struct dma_attrs *attrs) | |
4ce63fcd MS |
1117 | { |
1118 | struct page **pages; | |
1119 | int count = size >> PAGE_SHIFT; | |
1120 | int array_size = count * sizeof(struct page *); | |
1121 | int i = 0; | |
1122 | ||
1123 | if (array_size <= PAGE_SIZE) | |
23be7fda | 1124 | pages = kzalloc(array_size, GFP_KERNEL); |
4ce63fcd MS |
1125 | else |
1126 | pages = vzalloc(array_size); | |
1127 | if (!pages) | |
1128 | return NULL; | |
1129 | ||
549a17e4 MS |
1130 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) |
1131 | { | |
1132 | unsigned long order = get_order(size); | |
1133 | struct page *page; | |
1134 | ||
1135 | page = dma_alloc_from_contiguous(dev, count, order); | |
1136 | if (!page) | |
1137 | goto error; | |
1138 | ||
1139 | __dma_clear_buffer(page, size); | |
1140 | ||
1141 | for (i = 0; i < count; i++) | |
1142 | pages[i] = page + i; | |
1143 | ||
1144 | return pages; | |
1145 | } | |
1146 | ||
f8669bef MS |
1147 | /* |
1148 | * IOMMU can map any pages, so himem can also be used here | |
1149 | */ | |
1150 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
1151 | ||
4ce63fcd | 1152 | while (count) { |
593f4735 | 1153 | int j, order = __fls(count); |
4ce63fcd | 1154 | |
f8669bef | 1155 | pages[i] = alloc_pages(gfp, order); |
4ce63fcd | 1156 | while (!pages[i] && order) |
f8669bef | 1157 | pages[i] = alloc_pages(gfp, --order); |
4ce63fcd MS |
1158 | if (!pages[i]) |
1159 | goto error; | |
1160 | ||
5a796eeb | 1161 | if (order) { |
4ce63fcd | 1162 | split_page(pages[i], order); |
5a796eeb HD |
1163 | j = 1 << order; |
1164 | while (--j) | |
1165 | pages[i + j] = pages[i] + j; | |
1166 | } | |
4ce63fcd MS |
1167 | |
1168 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
1169 | i += 1 << order; | |
1170 | count -= 1 << order; | |
1171 | } | |
1172 | ||
1173 | return pages; | |
1174 | error: | |
9fa8af91 | 1175 | while (i--) |
4ce63fcd MS |
1176 | if (pages[i]) |
1177 | __free_pages(pages[i], 0); | |
46c87852 | 1178 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1179 | kfree(pages); |
1180 | else | |
1181 | vfree(pages); | |
1182 | return NULL; | |
1183 | } | |
1184 | ||
549a17e4 MS |
1185 | static int __iommu_free_buffer(struct device *dev, struct page **pages, |
1186 | size_t size, struct dma_attrs *attrs) | |
4ce63fcd MS |
1187 | { |
1188 | int count = size >> PAGE_SHIFT; | |
1189 | int array_size = count * sizeof(struct page *); | |
1190 | int i; | |
549a17e4 MS |
1191 | |
1192 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) { | |
1193 | dma_release_from_contiguous(dev, pages[0], count); | |
1194 | } else { | |
1195 | for (i = 0; i < count; i++) | |
1196 | if (pages[i]) | |
1197 | __free_pages(pages[i], 0); | |
1198 | } | |
1199 | ||
46c87852 | 1200 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1201 | kfree(pages); |
1202 | else | |
1203 | vfree(pages); | |
1204 | return 0; | |
1205 | } | |
1206 | ||
1207 | /* | |
1208 | * Create a CPU mapping for a specified pages | |
1209 | */ | |
1210 | static void * | |
e9da6e99 MS |
1211 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1212 | const void *caller) | |
4ce63fcd | 1213 | { |
513510dd LA |
1214 | return dma_common_pages_remap(pages, size, |
1215 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller); | |
4ce63fcd MS |
1216 | } |
1217 | ||
1218 | /* | |
1219 | * Create a mapping in device IO address space for specified pages | |
1220 | */ | |
1221 | static dma_addr_t | |
1222 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1223 | { | |
1224 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1225 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1226 | dma_addr_t dma_addr, iova; | |
1227 | int i, ret = DMA_ERROR_CODE; | |
1228 | ||
1229 | dma_addr = __alloc_iova(mapping, size); | |
1230 | if (dma_addr == DMA_ERROR_CODE) | |
1231 | return dma_addr; | |
1232 | ||
1233 | iova = dma_addr; | |
1234 | for (i = 0; i < count; ) { | |
1235 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; | |
1236 | phys_addr_t phys = page_to_phys(pages[i]); | |
1237 | unsigned int len, j; | |
1238 | ||
1239 | for (j = i + 1; j < count; j++, next_pfn++) | |
1240 | if (page_to_pfn(pages[j]) != next_pfn) | |
1241 | break; | |
1242 | ||
1243 | len = (j - i) << PAGE_SHIFT; | |
c9b24996 AH |
1244 | ret = iommu_map(mapping->domain, iova, phys, len, |
1245 | IOMMU_READ|IOMMU_WRITE); | |
4ce63fcd MS |
1246 | if (ret < 0) |
1247 | goto fail; | |
1248 | iova += len; | |
1249 | i = j; | |
1250 | } | |
1251 | return dma_addr; | |
1252 | fail: | |
1253 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1254 | __free_iova(mapping, dma_addr, size); | |
1255 | return DMA_ERROR_CODE; | |
1256 | } | |
1257 | ||
1258 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1259 | { | |
1260 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1261 | ||
1262 | /* | |
1263 | * add optional in-page offset from iova to size and align | |
1264 | * result to page size | |
1265 | */ | |
1266 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1267 | iova &= PAGE_MASK; | |
1268 | ||
1269 | iommu_unmap(mapping->domain, iova, size); | |
1270 | __free_iova(mapping, iova, size); | |
1271 | return 0; | |
1272 | } | |
1273 | ||
665bad7b HD |
1274 | static struct page **__atomic_get_pages(void *addr) |
1275 | { | |
36d0fd21 LA |
1276 | struct page *page; |
1277 | phys_addr_t phys; | |
1278 | ||
1279 | phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr); | |
1280 | page = phys_to_page(phys); | |
665bad7b | 1281 | |
36d0fd21 | 1282 | return (struct page **)page; |
665bad7b HD |
1283 | } |
1284 | ||
955c757e | 1285 | static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) |
e9da6e99 MS |
1286 | { |
1287 | struct vm_struct *area; | |
1288 | ||
665bad7b HD |
1289 | if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) |
1290 | return __atomic_get_pages(cpu_addr); | |
1291 | ||
955c757e MS |
1292 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1293 | return cpu_addr; | |
1294 | ||
e9da6e99 MS |
1295 | area = find_vm_area(cpu_addr); |
1296 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1297 | return area->pages; | |
1298 | return NULL; | |
1299 | } | |
1300 | ||
479ed93a HD |
1301 | static void *__iommu_alloc_atomic(struct device *dev, size_t size, |
1302 | dma_addr_t *handle) | |
1303 | { | |
1304 | struct page *page; | |
1305 | void *addr; | |
1306 | ||
1307 | addr = __alloc_from_pool(size, &page); | |
1308 | if (!addr) | |
1309 | return NULL; | |
1310 | ||
1311 | *handle = __iommu_create_mapping(dev, &page, size); | |
1312 | if (*handle == DMA_ERROR_CODE) | |
1313 | goto err_mapping; | |
1314 | ||
1315 | return addr; | |
1316 | ||
1317 | err_mapping: | |
1318 | __free_from_pool(addr, size); | |
1319 | return NULL; | |
1320 | } | |
1321 | ||
d5898291 | 1322 | static void __iommu_free_atomic(struct device *dev, void *cpu_addr, |
479ed93a HD |
1323 | dma_addr_t handle, size_t size) |
1324 | { | |
1325 | __iommu_remove_mapping(dev, handle, size); | |
d5898291 | 1326 | __free_from_pool(cpu_addr, size); |
479ed93a HD |
1327 | } |
1328 | ||
4ce63fcd MS |
1329 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
1330 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1331 | { | |
71b55663 | 1332 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
4ce63fcd MS |
1333 | struct page **pages; |
1334 | void *addr = NULL; | |
1335 | ||
1336 | *handle = DMA_ERROR_CODE; | |
1337 | size = PAGE_ALIGN(size); | |
1338 | ||
10c8562f | 1339 | if (!(gfp & __GFP_WAIT)) |
479ed93a HD |
1340 | return __iommu_alloc_atomic(dev, size, handle); |
1341 | ||
5b91a98c RZ |
1342 | /* |
1343 | * Following is a work-around (a.k.a. hack) to prevent pages | |
1344 | * with __GFP_COMP being passed to split_page() which cannot | |
1345 | * handle them. The real problem is that this flag probably | |
1346 | * should be 0 on ARM as it is not supported on this | |
1347 | * platform; see CONFIG_HUGETLBFS. | |
1348 | */ | |
1349 | gfp &= ~(__GFP_COMP); | |
1350 | ||
549a17e4 | 1351 | pages = __iommu_alloc_buffer(dev, size, gfp, attrs); |
4ce63fcd MS |
1352 | if (!pages) |
1353 | return NULL; | |
1354 | ||
1355 | *handle = __iommu_create_mapping(dev, pages, size); | |
1356 | if (*handle == DMA_ERROR_CODE) | |
1357 | goto err_buffer; | |
1358 | ||
955c757e MS |
1359 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1360 | return pages; | |
1361 | ||
e9da6e99 MS |
1362 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1363 | __builtin_return_address(0)); | |
4ce63fcd MS |
1364 | if (!addr) |
1365 | goto err_mapping; | |
1366 | ||
1367 | return addr; | |
1368 | ||
1369 | err_mapping: | |
1370 | __iommu_remove_mapping(dev, *handle, size); | |
1371 | err_buffer: | |
549a17e4 | 1372 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1373 | return NULL; |
1374 | } | |
1375 | ||
1376 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1377 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1378 | struct dma_attrs *attrs) | |
1379 | { | |
e9da6e99 MS |
1380 | unsigned long uaddr = vma->vm_start; |
1381 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1382 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1383 | |
1384 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
4ce63fcd | 1385 | |
e9da6e99 MS |
1386 | if (!pages) |
1387 | return -ENXIO; | |
4ce63fcd | 1388 | |
e9da6e99 MS |
1389 | do { |
1390 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1391 | if (ret) { | |
1392 | pr_err("Remapping memory failed: %d\n", ret); | |
1393 | return ret; | |
1394 | } | |
1395 | uaddr += PAGE_SIZE; | |
1396 | usize -= PAGE_SIZE; | |
1397 | } while (usize > 0); | |
4ce63fcd | 1398 | |
4ce63fcd MS |
1399 | return 0; |
1400 | } | |
1401 | ||
1402 | /* | |
1403 | * free a page as defined by the above mapping. | |
1404 | * Must not be called with IRQs disabled. | |
1405 | */ | |
1406 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1407 | dma_addr_t handle, struct dma_attrs *attrs) | |
1408 | { | |
836bfa0d | 1409 | struct page **pages; |
4ce63fcd MS |
1410 | size = PAGE_ALIGN(size); |
1411 | ||
836bfa0d YC |
1412 | if (__in_atomic_pool(cpu_addr, size)) { |
1413 | __iommu_free_atomic(dev, cpu_addr, handle, size); | |
e9da6e99 | 1414 | return; |
4ce63fcd | 1415 | } |
e9da6e99 | 1416 | |
836bfa0d YC |
1417 | pages = __iommu_get_pages(cpu_addr, attrs); |
1418 | if (!pages) { | |
1419 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
479ed93a HD |
1420 | return; |
1421 | } | |
1422 | ||
955c757e | 1423 | if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { |
513510dd LA |
1424 | dma_common_free_remap(cpu_addr, size, |
1425 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
955c757e | 1426 | } |
e9da6e99 MS |
1427 | |
1428 | __iommu_remove_mapping(dev, handle, size); | |
549a17e4 | 1429 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1430 | } |
1431 | ||
dc2832e1 MS |
1432 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1433 | void *cpu_addr, dma_addr_t dma_addr, | |
1434 | size_t size, struct dma_attrs *attrs) | |
1435 | { | |
1436 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1437 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1438 | ||
1439 | if (!pages) | |
1440 | return -ENXIO; | |
1441 | ||
1442 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1443 | GFP_KERNEL); | |
4ce63fcd MS |
1444 | } |
1445 | ||
c9b24996 AH |
1446 | static int __dma_direction_to_prot(enum dma_data_direction dir) |
1447 | { | |
1448 | int prot; | |
1449 | ||
1450 | switch (dir) { | |
1451 | case DMA_BIDIRECTIONAL: | |
1452 | prot = IOMMU_READ | IOMMU_WRITE; | |
1453 | break; | |
1454 | case DMA_TO_DEVICE: | |
1455 | prot = IOMMU_READ; | |
1456 | break; | |
1457 | case DMA_FROM_DEVICE: | |
1458 | prot = IOMMU_WRITE; | |
1459 | break; | |
1460 | default: | |
1461 | prot = 0; | |
1462 | } | |
1463 | ||
1464 | return prot; | |
1465 | } | |
1466 | ||
4ce63fcd MS |
1467 | /* |
1468 | * Map a part of the scatter-gather list into contiguous io address space | |
1469 | */ | |
1470 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1471 | size_t size, dma_addr_t *handle, | |
0fa478df RH |
1472 | enum dma_data_direction dir, struct dma_attrs *attrs, |
1473 | bool is_coherent) | |
4ce63fcd MS |
1474 | { |
1475 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1476 | dma_addr_t iova, iova_base; | |
1477 | int ret = 0; | |
1478 | unsigned int count; | |
1479 | struct scatterlist *s; | |
c9b24996 | 1480 | int prot; |
4ce63fcd MS |
1481 | |
1482 | size = PAGE_ALIGN(size); | |
1483 | *handle = DMA_ERROR_CODE; | |
1484 | ||
1485 | iova_base = iova = __alloc_iova(mapping, size); | |
1486 | if (iova == DMA_ERROR_CODE) | |
1487 | return -ENOMEM; | |
1488 | ||
1489 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
1490 | phys_addr_t phys = page_to_phys(sg_page(s)); | |
1491 | unsigned int len = PAGE_ALIGN(s->offset + s->length); | |
1492 | ||
0fa478df RH |
1493 | if (!is_coherent && |
1494 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1495 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1496 | ||
c9b24996 AH |
1497 | prot = __dma_direction_to_prot(dir); |
1498 | ||
1499 | ret = iommu_map(mapping->domain, iova, phys, len, prot); | |
4ce63fcd MS |
1500 | if (ret < 0) |
1501 | goto fail; | |
1502 | count += len >> PAGE_SHIFT; | |
1503 | iova += len; | |
1504 | } | |
1505 | *handle = iova_base; | |
1506 | ||
1507 | return 0; | |
1508 | fail: | |
1509 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1510 | __free_iova(mapping, iova_base, size); | |
1511 | return ret; | |
1512 | } | |
1513 | ||
0fa478df RH |
1514 | static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
1515 | enum dma_data_direction dir, struct dma_attrs *attrs, | |
1516 | bool is_coherent) | |
4ce63fcd MS |
1517 | { |
1518 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1519 | int i, count = 0; | |
1520 | unsigned int offset = s->offset; | |
1521 | unsigned int size = s->offset + s->length; | |
1522 | unsigned int max = dma_get_max_seg_size(dev); | |
1523 | ||
1524 | for (i = 1; i < nents; i++) { | |
1525 | s = sg_next(s); | |
1526 | ||
1527 | s->dma_address = DMA_ERROR_CODE; | |
1528 | s->dma_length = 0; | |
1529 | ||
1530 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1531 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
0fa478df | 1532 | dir, attrs, is_coherent) < 0) |
4ce63fcd MS |
1533 | goto bad_mapping; |
1534 | ||
1535 | dma->dma_address += offset; | |
1536 | dma->dma_length = size - offset; | |
1537 | ||
1538 | size = offset = s->offset; | |
1539 | start = s; | |
1540 | dma = sg_next(dma); | |
1541 | count += 1; | |
1542 | } | |
1543 | size += s->length; | |
1544 | } | |
0fa478df RH |
1545 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs, |
1546 | is_coherent) < 0) | |
4ce63fcd MS |
1547 | goto bad_mapping; |
1548 | ||
1549 | dma->dma_address += offset; | |
1550 | dma->dma_length = size - offset; | |
1551 | ||
1552 | return count+1; | |
1553 | ||
1554 | bad_mapping: | |
1555 | for_each_sg(sg, s, count, i) | |
1556 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1557 | return 0; | |
1558 | } | |
1559 | ||
1560 | /** | |
0fa478df | 1561 | * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA |
4ce63fcd MS |
1562 | * @dev: valid struct device pointer |
1563 | * @sg: list of buffers | |
0fa478df RH |
1564 | * @nents: number of buffers to map |
1565 | * @dir: DMA transfer direction | |
4ce63fcd | 1566 | * |
0fa478df RH |
1567 | * Map a set of i/o coherent buffers described by scatterlist in streaming |
1568 | * mode for DMA. The scatter gather list elements are merged together (if | |
1569 | * possible) and tagged with the appropriate dma address and length. They are | |
1570 | * obtained via sg_dma_{address,length}. | |
4ce63fcd | 1571 | */ |
0fa478df RH |
1572 | int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg, |
1573 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1574 | { | |
1575 | return __iommu_map_sg(dev, sg, nents, dir, attrs, true); | |
1576 | } | |
1577 | ||
1578 | /** | |
1579 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1580 | * @dev: valid struct device pointer | |
1581 | * @sg: list of buffers | |
1582 | * @nents: number of buffers to map | |
1583 | * @dir: DMA transfer direction | |
1584 | * | |
1585 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1586 | * The scatter gather list elements are merged together (if possible) and | |
1587 | * tagged with the appropriate dma address and length. They are obtained via | |
1588 | * sg_dma_{address,length}. | |
1589 | */ | |
1590 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, | |
1591 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1592 | { | |
1593 | return __iommu_map_sg(dev, sg, nents, dir, attrs, false); | |
1594 | } | |
1595 | ||
1596 | static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1597 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs, | |
1598 | bool is_coherent) | |
4ce63fcd MS |
1599 | { |
1600 | struct scatterlist *s; | |
1601 | int i; | |
1602 | ||
1603 | for_each_sg(sg, s, nents, i) { | |
1604 | if (sg_dma_len(s)) | |
1605 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1606 | sg_dma_len(s)); | |
0fa478df | 1607 | if (!is_coherent && |
97ef952a | 1608 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1609 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1610 | s->length, dir); | |
1611 | } | |
1612 | } | |
1613 | ||
0fa478df RH |
1614 | /** |
1615 | * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1616 | * @dev: valid struct device pointer | |
1617 | * @sg: list of buffers | |
1618 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1619 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1620 | * | |
1621 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1622 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1623 | */ | |
1624 | void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1625 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1626 | { | |
1627 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, true); | |
1628 | } | |
1629 | ||
1630 | /** | |
1631 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1632 | * @dev: valid struct device pointer | |
1633 | * @sg: list of buffers | |
1634 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1635 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1636 | * | |
1637 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1638 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1639 | */ | |
1640 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1641 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1642 | { | |
1643 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, false); | |
1644 | } | |
1645 | ||
4ce63fcd MS |
1646 | /** |
1647 | * arm_iommu_sync_sg_for_cpu | |
1648 | * @dev: valid struct device pointer | |
1649 | * @sg: list of buffers | |
1650 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1651 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1652 | */ | |
1653 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1654 | int nents, enum dma_data_direction dir) | |
1655 | { | |
1656 | struct scatterlist *s; | |
1657 | int i; | |
1658 | ||
1659 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1660 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1661 | |
1662 | } | |
1663 | ||
1664 | /** | |
1665 | * arm_iommu_sync_sg_for_device | |
1666 | * @dev: valid struct device pointer | |
1667 | * @sg: list of buffers | |
1668 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1669 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1670 | */ | |
1671 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1672 | int nents, enum dma_data_direction dir) | |
1673 | { | |
1674 | struct scatterlist *s; | |
1675 | int i; | |
1676 | ||
1677 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1678 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1679 | } |
1680 | ||
1681 | ||
1682 | /** | |
0fa478df | 1683 | * arm_coherent_iommu_map_page |
4ce63fcd MS |
1684 | * @dev: valid struct device pointer |
1685 | * @page: page that buffer resides in | |
1686 | * @offset: offset into page for start of buffer | |
1687 | * @size: size of buffer to map | |
1688 | * @dir: DMA transfer direction | |
1689 | * | |
0fa478df | 1690 | * Coherent IOMMU aware version of arm_dma_map_page() |
4ce63fcd | 1691 | */ |
0fa478df | 1692 | static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page, |
4ce63fcd MS |
1693 | unsigned long offset, size_t size, enum dma_data_direction dir, |
1694 | struct dma_attrs *attrs) | |
1695 | { | |
1696 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1697 | dma_addr_t dma_addr; | |
13987d68 | 1698 | int ret, prot, len = PAGE_ALIGN(size + offset); |
4ce63fcd | 1699 | |
4ce63fcd MS |
1700 | dma_addr = __alloc_iova(mapping, len); |
1701 | if (dma_addr == DMA_ERROR_CODE) | |
1702 | return dma_addr; | |
1703 | ||
c9b24996 | 1704 | prot = __dma_direction_to_prot(dir); |
13987d68 WD |
1705 | |
1706 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot); | |
4ce63fcd MS |
1707 | if (ret < 0) |
1708 | goto fail; | |
1709 | ||
1710 | return dma_addr + offset; | |
1711 | fail: | |
1712 | __free_iova(mapping, dma_addr, len); | |
1713 | return DMA_ERROR_CODE; | |
1714 | } | |
1715 | ||
0fa478df RH |
1716 | /** |
1717 | * arm_iommu_map_page | |
1718 | * @dev: valid struct device pointer | |
1719 | * @page: page that buffer resides in | |
1720 | * @offset: offset into page for start of buffer | |
1721 | * @size: size of buffer to map | |
1722 | * @dir: DMA transfer direction | |
1723 | * | |
1724 | * IOMMU aware version of arm_dma_map_page() | |
1725 | */ | |
1726 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1727 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1728 | struct dma_attrs *attrs) | |
1729 | { | |
1730 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
1731 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1732 | ||
1733 | return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs); | |
1734 | } | |
1735 | ||
1736 | /** | |
1737 | * arm_coherent_iommu_unmap_page | |
1738 | * @dev: valid struct device pointer | |
1739 | * @handle: DMA address of buffer | |
1740 | * @size: size of buffer (same as passed to dma_map_page) | |
1741 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1742 | * | |
1743 | * Coherent IOMMU aware version of arm_dma_unmap_page() | |
1744 | */ | |
1745 | static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1746 | size_t size, enum dma_data_direction dir, | |
1747 | struct dma_attrs *attrs) | |
1748 | { | |
1749 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1750 | dma_addr_t iova = handle & PAGE_MASK; | |
0fa478df RH |
1751 | int offset = handle & ~PAGE_MASK; |
1752 | int len = PAGE_ALIGN(size + offset); | |
1753 | ||
1754 | if (!iova) | |
1755 | return; | |
1756 | ||
1757 | iommu_unmap(mapping->domain, iova, len); | |
1758 | __free_iova(mapping, iova, len); | |
1759 | } | |
1760 | ||
4ce63fcd MS |
1761 | /** |
1762 | * arm_iommu_unmap_page | |
1763 | * @dev: valid struct device pointer | |
1764 | * @handle: DMA address of buffer | |
1765 | * @size: size of buffer (same as passed to dma_map_page) | |
1766 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1767 | * | |
1768 | * IOMMU aware version of arm_dma_unmap_page() | |
1769 | */ | |
1770 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1771 | size_t size, enum dma_data_direction dir, | |
1772 | struct dma_attrs *attrs) | |
1773 | { | |
1774 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1775 | dma_addr_t iova = handle & PAGE_MASK; | |
1776 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1777 | int offset = handle & ~PAGE_MASK; | |
1778 | int len = PAGE_ALIGN(size + offset); | |
1779 | ||
1780 | if (!iova) | |
1781 | return; | |
1782 | ||
0fa478df | 1783 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1784 | __dma_page_dev_to_cpu(page, offset, size, dir); |
1785 | ||
1786 | iommu_unmap(mapping->domain, iova, len); | |
1787 | __free_iova(mapping, iova, len); | |
1788 | } | |
1789 | ||
1790 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1791 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1792 | { | |
1793 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1794 | dma_addr_t iova = handle & PAGE_MASK; | |
1795 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1796 | unsigned int offset = handle & ~PAGE_MASK; | |
1797 | ||
1798 | if (!iova) | |
1799 | return; | |
1800 | ||
0fa478df | 1801 | __dma_page_dev_to_cpu(page, offset, size, dir); |
4ce63fcd MS |
1802 | } |
1803 | ||
1804 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1805 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1806 | { | |
1807 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1808 | dma_addr_t iova = handle & PAGE_MASK; | |
1809 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1810 | unsigned int offset = handle & ~PAGE_MASK; | |
1811 | ||
1812 | if (!iova) | |
1813 | return; | |
1814 | ||
1815 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1816 | } | |
1817 | ||
1818 | struct dma_map_ops iommu_ops = { | |
1819 | .alloc = arm_iommu_alloc_attrs, | |
1820 | .free = arm_iommu_free_attrs, | |
1821 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 1822 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
1823 | |
1824 | .map_page = arm_iommu_map_page, | |
1825 | .unmap_page = arm_iommu_unmap_page, | |
1826 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1827 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1828 | ||
1829 | .map_sg = arm_iommu_map_sg, | |
1830 | .unmap_sg = arm_iommu_unmap_sg, | |
1831 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1832 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
d09e1333 HD |
1833 | |
1834 | .set_dma_mask = arm_dma_set_mask, | |
4ce63fcd MS |
1835 | }; |
1836 | ||
0fa478df RH |
1837 | struct dma_map_ops iommu_coherent_ops = { |
1838 | .alloc = arm_iommu_alloc_attrs, | |
1839 | .free = arm_iommu_free_attrs, | |
1840 | .mmap = arm_iommu_mmap_attrs, | |
1841 | .get_sgtable = arm_iommu_get_sgtable, | |
1842 | ||
1843 | .map_page = arm_coherent_iommu_map_page, | |
1844 | .unmap_page = arm_coherent_iommu_unmap_page, | |
1845 | ||
1846 | .map_sg = arm_coherent_iommu_map_sg, | |
1847 | .unmap_sg = arm_coherent_iommu_unmap_sg, | |
d09e1333 HD |
1848 | |
1849 | .set_dma_mask = arm_dma_set_mask, | |
0fa478df RH |
1850 | }; |
1851 | ||
4ce63fcd MS |
1852 | /** |
1853 | * arm_iommu_create_mapping | |
1854 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
1855 | * @base: start address of the valid IO address space | |
68efd7d2 | 1856 | * @size: maximum size of the valid IO address space |
4ce63fcd MS |
1857 | * |
1858 | * Creates a mapping structure which holds information about used/unused | |
1859 | * IO address ranges, which is required to perform memory allocation and | |
1860 | * mapping with IOMMU aware functions. | |
1861 | * | |
1862 | * The client device need to be attached to the mapping with | |
1863 | * arm_iommu_attach_device function. | |
1864 | */ | |
1865 | struct dma_iommu_mapping * | |
68efd7d2 | 1866 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size) |
4ce63fcd | 1867 | { |
68efd7d2 MS |
1868 | unsigned int bits = size >> PAGE_SHIFT; |
1869 | unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); | |
4ce63fcd | 1870 | struct dma_iommu_mapping *mapping; |
68efd7d2 | 1871 | int extensions = 1; |
4ce63fcd MS |
1872 | int err = -ENOMEM; |
1873 | ||
68efd7d2 | 1874 | if (!bitmap_size) |
4ce63fcd MS |
1875 | return ERR_PTR(-EINVAL); |
1876 | ||
68efd7d2 MS |
1877 | if (bitmap_size > PAGE_SIZE) { |
1878 | extensions = bitmap_size / PAGE_SIZE; | |
1879 | bitmap_size = PAGE_SIZE; | |
1880 | } | |
1881 | ||
4ce63fcd MS |
1882 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); |
1883 | if (!mapping) | |
1884 | goto err; | |
1885 | ||
68efd7d2 MS |
1886 | mapping->bitmap_size = bitmap_size; |
1887 | mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *), | |
4d852ef8 AH |
1888 | GFP_KERNEL); |
1889 | if (!mapping->bitmaps) | |
4ce63fcd MS |
1890 | goto err2; |
1891 | ||
68efd7d2 | 1892 | mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL); |
4d852ef8 AH |
1893 | if (!mapping->bitmaps[0]) |
1894 | goto err3; | |
1895 | ||
1896 | mapping->nr_bitmaps = 1; | |
1897 | mapping->extensions = extensions; | |
4ce63fcd | 1898 | mapping->base = base; |
68efd7d2 | 1899 | mapping->bits = BITS_PER_BYTE * bitmap_size; |
4d852ef8 | 1900 | |
4ce63fcd MS |
1901 | spin_lock_init(&mapping->lock); |
1902 | ||
1903 | mapping->domain = iommu_domain_alloc(bus); | |
1904 | if (!mapping->domain) | |
4d852ef8 | 1905 | goto err4; |
4ce63fcd MS |
1906 | |
1907 | kref_init(&mapping->kref); | |
1908 | return mapping; | |
4d852ef8 AH |
1909 | err4: |
1910 | kfree(mapping->bitmaps[0]); | |
4ce63fcd | 1911 | err3: |
4d852ef8 | 1912 | kfree(mapping->bitmaps); |
4ce63fcd MS |
1913 | err2: |
1914 | kfree(mapping); | |
1915 | err: | |
1916 | return ERR_PTR(err); | |
1917 | } | |
18177d12 | 1918 | EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); |
4ce63fcd MS |
1919 | |
1920 | static void release_iommu_mapping(struct kref *kref) | |
1921 | { | |
4d852ef8 | 1922 | int i; |
4ce63fcd MS |
1923 | struct dma_iommu_mapping *mapping = |
1924 | container_of(kref, struct dma_iommu_mapping, kref); | |
1925 | ||
1926 | iommu_domain_free(mapping->domain); | |
4d852ef8 AH |
1927 | for (i = 0; i < mapping->nr_bitmaps; i++) |
1928 | kfree(mapping->bitmaps[i]); | |
1929 | kfree(mapping->bitmaps); | |
4ce63fcd MS |
1930 | kfree(mapping); |
1931 | } | |
1932 | ||
4d852ef8 AH |
1933 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) |
1934 | { | |
1935 | int next_bitmap; | |
1936 | ||
1937 | if (mapping->nr_bitmaps > mapping->extensions) | |
1938 | return -EINVAL; | |
1939 | ||
1940 | next_bitmap = mapping->nr_bitmaps; | |
1941 | mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size, | |
1942 | GFP_ATOMIC); | |
1943 | if (!mapping->bitmaps[next_bitmap]) | |
1944 | return -ENOMEM; | |
1945 | ||
1946 | mapping->nr_bitmaps++; | |
1947 | ||
1948 | return 0; | |
1949 | } | |
1950 | ||
4ce63fcd MS |
1951 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) |
1952 | { | |
1953 | if (mapping) | |
1954 | kref_put(&mapping->kref, release_iommu_mapping); | |
1955 | } | |
18177d12 | 1956 | EXPORT_SYMBOL_GPL(arm_iommu_release_mapping); |
4ce63fcd | 1957 | |
eab8d653 LP |
1958 | static int __arm_iommu_attach_device(struct device *dev, |
1959 | struct dma_iommu_mapping *mapping) | |
1960 | { | |
1961 | int err; | |
1962 | ||
1963 | err = iommu_attach_device(mapping->domain, dev); | |
1964 | if (err) | |
1965 | return err; | |
1966 | ||
1967 | kref_get(&mapping->kref); | |
1968 | dev->archdata.mapping = mapping; | |
1969 | ||
1970 | pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
1971 | return 0; | |
1972 | } | |
1973 | ||
4ce63fcd MS |
1974 | /** |
1975 | * arm_iommu_attach_device | |
1976 | * @dev: valid struct device pointer | |
1977 | * @mapping: io address space mapping structure (returned from | |
1978 | * arm_iommu_create_mapping) | |
1979 | * | |
eab8d653 LP |
1980 | * Attaches specified io address space mapping to the provided device. |
1981 | * This replaces the dma operations (dma_map_ops pointer) with the | |
1982 | * IOMMU aware version. | |
1983 | * | |
4bb25789 WD |
1984 | * More than one client might be attached to the same io address space |
1985 | * mapping. | |
4ce63fcd MS |
1986 | */ |
1987 | int arm_iommu_attach_device(struct device *dev, | |
1988 | struct dma_iommu_mapping *mapping) | |
1989 | { | |
1990 | int err; | |
1991 | ||
eab8d653 | 1992 | err = __arm_iommu_attach_device(dev, mapping); |
4ce63fcd MS |
1993 | if (err) |
1994 | return err; | |
1995 | ||
eab8d653 | 1996 | set_dma_ops(dev, &iommu_ops); |
4ce63fcd MS |
1997 | return 0; |
1998 | } | |
18177d12 | 1999 | EXPORT_SYMBOL_GPL(arm_iommu_attach_device); |
4ce63fcd | 2000 | |
eab8d653 | 2001 | static void __arm_iommu_detach_device(struct device *dev) |
6fe36758 HD |
2002 | { |
2003 | struct dma_iommu_mapping *mapping; | |
2004 | ||
2005 | mapping = to_dma_iommu_mapping(dev); | |
2006 | if (!mapping) { | |
2007 | dev_warn(dev, "Not attached\n"); | |
2008 | return; | |
2009 | } | |
2010 | ||
2011 | iommu_detach_device(mapping->domain, dev); | |
2012 | kref_put(&mapping->kref, release_iommu_mapping); | |
9e4b259d | 2013 | dev->archdata.mapping = NULL; |
6fe36758 HD |
2014 | |
2015 | pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev)); | |
2016 | } | |
eab8d653 LP |
2017 | |
2018 | /** | |
2019 | * arm_iommu_detach_device | |
2020 | * @dev: valid struct device pointer | |
2021 | * | |
2022 | * Detaches the provided device from a previously attached map. | |
2023 | * This voids the dma operations (dma_map_ops pointer) | |
2024 | */ | |
2025 | void arm_iommu_detach_device(struct device *dev) | |
2026 | { | |
2027 | __arm_iommu_detach_device(dev); | |
2028 | set_dma_ops(dev, NULL); | |
2029 | } | |
18177d12 | 2030 | EXPORT_SYMBOL_GPL(arm_iommu_detach_device); |
6fe36758 | 2031 | |
4bb25789 WD |
2032 | static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent) |
2033 | { | |
2034 | return coherent ? &iommu_coherent_ops : &iommu_ops; | |
2035 | } | |
2036 | ||
2037 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
2038 | struct iommu_ops *iommu) | |
2039 | { | |
2040 | struct dma_iommu_mapping *mapping; | |
2041 | ||
2042 | if (!iommu) | |
2043 | return false; | |
2044 | ||
2045 | mapping = arm_iommu_create_mapping(dev->bus, dma_base, size); | |
2046 | if (IS_ERR(mapping)) { | |
2047 | pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n", | |
2048 | size, dev_name(dev)); | |
2049 | return false; | |
2050 | } | |
2051 | ||
eab8d653 | 2052 | if (__arm_iommu_attach_device(dev, mapping)) { |
4bb25789 WD |
2053 | pr_warn("Failed to attached device %s to IOMMU_mapping\n", |
2054 | dev_name(dev)); | |
2055 | arm_iommu_release_mapping(mapping); | |
2056 | return false; | |
2057 | } | |
2058 | ||
2059 | return true; | |
2060 | } | |
2061 | ||
2062 | static void arm_teardown_iommu_dma_ops(struct device *dev) | |
2063 | { | |
2064 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
2065 | ||
c2273a18 WD |
2066 | if (!mapping) |
2067 | return; | |
2068 | ||
eab8d653 | 2069 | __arm_iommu_detach_device(dev); |
4bb25789 WD |
2070 | arm_iommu_release_mapping(mapping); |
2071 | } | |
2072 | ||
2073 | #else | |
2074 | ||
2075 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
2076 | struct iommu_ops *iommu) | |
2077 | { | |
2078 | return false; | |
2079 | } | |
2080 | ||
2081 | static void arm_teardown_iommu_dma_ops(struct device *dev) { } | |
2082 | ||
2083 | #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops | |
2084 | ||
2085 | #endif /* CONFIG_ARM_DMA_USE_IOMMU */ | |
2086 | ||
2087 | static struct dma_map_ops *arm_get_dma_map_ops(bool coherent) | |
2088 | { | |
2089 | return coherent ? &arm_coherent_dma_ops : &arm_dma_ops; | |
2090 | } | |
2091 | ||
2092 | void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
2093 | struct iommu_ops *iommu, bool coherent) | |
2094 | { | |
2095 | struct dma_map_ops *dma_ops; | |
2096 | ||
6f51ee70 | 2097 | dev->archdata.dma_coherent = coherent; |
4bb25789 WD |
2098 | if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) |
2099 | dma_ops = arm_get_iommu_dma_map_ops(coherent); | |
2100 | else | |
2101 | dma_ops = arm_get_dma_map_ops(coherent); | |
2102 | ||
2103 | set_dma_ops(dev, dma_ops); | |
2104 | } | |
2105 | ||
2106 | void arch_teardown_dma_ops(struct device *dev) | |
2107 | { | |
2108 | arm_teardown_iommu_dma_ops(dev); | |
2109 | } |