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1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
1da177e4 LT |
15 | #include <linux/errno.h> |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
39af22a7 | 20 | #include <linux/highmem.h> |
99d1717d | 21 | #include <linux/slab.h> |
1da177e4 | 22 | |
23759dc6 | 23 | #include <asm/memory.h> |
43377453 | 24 | #include <asm/highmem.h> |
1da177e4 | 25 | #include <asm/cacheflush.h> |
1da177e4 | 26 | #include <asm/tlbflush.h> |
37134cd5 | 27 | #include <asm/sizes.h> |
99d1717d | 28 | #include <asm/mach/arch.h> |
37134cd5 | 29 | |
022ae537 RK |
30 | #include "mm.h" |
31 | ||
2dc6a016 MS |
32 | /** |
33 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
34 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
35 | * @page: page that buffer resides in | |
36 | * @offset: offset into page for start of buffer | |
37 | * @size: size of buffer to map | |
38 | * @dir: DMA transfer direction | |
39 | * | |
40 | * Ensure that any data held in the cache is appropriately discarded | |
41 | * or written back. | |
42 | * | |
43 | * The device owns this memory once this call has completed. The CPU | |
44 | * can regain ownership by calling dma_unmap_page(). | |
45 | */ | |
46 | static inline dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, | |
47 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
48 | struct dma_attrs *attrs) | |
49 | { | |
50 | return __dma_map_page(dev, page, offset, size, dir); | |
51 | } | |
52 | ||
53 | /** | |
54 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
55 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
56 | * @handle: DMA address of buffer | |
57 | * @size: size of buffer (same as passed to dma_map_page) | |
58 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
59 | * | |
60 | * Unmap a page streaming mode DMA translation. The handle and size | |
61 | * must match what was provided in the previous dma_map_page() call. | |
62 | * All other usages are undefined. | |
63 | * | |
64 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
65 | * whatever the device wrote there. | |
66 | */ | |
67 | static inline void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, | |
68 | size_t size, enum dma_data_direction dir, | |
69 | struct dma_attrs *attrs) | |
70 | { | |
71 | __dma_unmap_page(dev, handle, size, dir); | |
72 | } | |
73 | ||
74 | static inline void arm_dma_sync_single_for_cpu(struct device *dev, | |
75 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
76 | { | |
77 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
78 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
79 | if (!dmabounce_sync_for_cpu(dev, handle, size, dir)) | |
80 | return; | |
81 | ||
82 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
83 | } | |
84 | ||
85 | static inline void arm_dma_sync_single_for_device(struct device *dev, | |
86 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
87 | { | |
88 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
89 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
90 | if (!dmabounce_sync_for_device(dev, handle, size, dir)) | |
91 | return; | |
92 | ||
93 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
94 | } | |
95 | ||
96 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask); | |
97 | ||
98 | struct dma_map_ops arm_dma_ops = { | |
99 | .map_page = arm_dma_map_page, | |
100 | .unmap_page = arm_dma_unmap_page, | |
101 | .map_sg = arm_dma_map_sg, | |
102 | .unmap_sg = arm_dma_unmap_sg, | |
103 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
104 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
105 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
106 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
107 | .set_dma_mask = arm_dma_set_mask, | |
108 | }; | |
109 | EXPORT_SYMBOL(arm_dma_ops); | |
110 | ||
ab6494f0 CM |
111 | static u64 get_coherent_dma_mask(struct device *dev) |
112 | { | |
022ae537 | 113 | u64 mask = (u64)arm_dma_limit; |
ab6494f0 CM |
114 | |
115 | if (dev) { | |
116 | mask = dev->coherent_dma_mask; | |
117 | ||
118 | /* | |
119 | * Sanity check the DMA mask - it must be non-zero, and | |
120 | * must be able to be satisfied by a DMA allocation. | |
121 | */ | |
122 | if (mask == 0) { | |
123 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
124 | return 0; | |
125 | } | |
126 | ||
022ae537 | 127 | if ((~mask) & (u64)arm_dma_limit) { |
ab6494f0 CM |
128 | dev_warn(dev, "coherent DMA mask %#llx is smaller " |
129 | "than system GFP_DMA mask %#llx\n", | |
022ae537 | 130 | mask, (u64)arm_dma_limit); |
ab6494f0 CM |
131 | return 0; |
132 | } | |
133 | } | |
1da177e4 | 134 | |
ab6494f0 CM |
135 | return mask; |
136 | } | |
137 | ||
7a9a32a9 RK |
138 | /* |
139 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
140 | * specified gfp mask. Note that 'size' must be page aligned. | |
141 | */ | |
142 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
143 | { | |
144 | unsigned long order = get_order(size); | |
145 | struct page *page, *p, *e; | |
146 | void *ptr; | |
147 | u64 mask = get_coherent_dma_mask(dev); | |
148 | ||
149 | #ifdef CONFIG_DMA_API_DEBUG | |
150 | u64 limit = (mask + 1) & ~mask; | |
151 | if (limit && size >= limit) { | |
152 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
153 | size, mask); | |
154 | return NULL; | |
155 | } | |
156 | #endif | |
157 | ||
158 | if (!mask) | |
159 | return NULL; | |
160 | ||
161 | if (mask < 0xffffffffULL) | |
162 | gfp |= GFP_DMA; | |
163 | ||
164 | page = alloc_pages(gfp, order); | |
165 | if (!page) | |
166 | return NULL; | |
167 | ||
168 | /* | |
169 | * Now split the huge page and free the excess pages | |
170 | */ | |
171 | split_page(page, order); | |
172 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
173 | __free_page(p); | |
174 | ||
175 | /* | |
176 | * Ensure that the allocated pages are zeroed, and that any data | |
177 | * lurking in the kernel direct-mapped region is invalidated. | |
178 | */ | |
179 | ptr = page_address(page); | |
180 | memset(ptr, 0, size); | |
181 | dmac_flush_range(ptr, ptr + size); | |
182 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
183 | ||
184 | return page; | |
185 | } | |
186 | ||
187 | /* | |
188 | * Free a DMA buffer. 'size' must be page aligned. | |
189 | */ | |
190 | static void __dma_free_buffer(struct page *page, size_t size) | |
191 | { | |
192 | struct page *e = page + (size >> PAGE_SHIFT); | |
193 | ||
194 | while (page < e) { | |
195 | __free_page(page); | |
196 | page++; | |
197 | } | |
198 | } | |
199 | ||
ab6494f0 | 200 | #ifdef CONFIG_MMU |
a5e9d38b | 201 | |
99d1717d | 202 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT) |
1fdb24e9 | 203 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PMD_SHIFT) |
a5e9d38b | 204 | |
1da177e4 | 205 | /* |
37134cd5 | 206 | * These are the page tables (2MB each) covering uncached, DMA consistent allocations |
1da177e4 | 207 | */ |
99d1717d JM |
208 | static pte_t **consistent_pte; |
209 | ||
99d1717d | 210 | #define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M |
99d1717d JM |
211 | |
212 | unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE; | |
213 | ||
214 | void __init init_consistent_dma_size(unsigned long size) | |
215 | { | |
216 | unsigned long base = CONSISTENT_END - ALIGN(size, SZ_2M); | |
217 | ||
218 | BUG_ON(consistent_pte); /* Check we're called before DMA region init */ | |
219 | BUG_ON(base < VMALLOC_END); | |
220 | ||
221 | /* Grow region to accommodate specified size */ | |
222 | if (base < consistent_base) | |
223 | consistent_base = base; | |
224 | } | |
1da177e4 | 225 | |
13ccf3ad | 226 | #include "vmregion.h" |
1da177e4 | 227 | |
13ccf3ad RK |
228 | static struct arm_vmregion_head consistent_head = { |
229 | .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock), | |
1da177e4 | 230 | .vm_list = LIST_HEAD_INIT(consistent_head.vm_list), |
1da177e4 LT |
231 | .vm_end = CONSISTENT_END, |
232 | }; | |
233 | ||
1da177e4 LT |
234 | #ifdef CONFIG_HUGETLB_PAGE |
235 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
236 | #endif | |
237 | ||
88c58f3b RK |
238 | /* |
239 | * Initialise the consistent memory allocation. | |
240 | */ | |
241 | static int __init consistent_init(void) | |
242 | { | |
243 | int ret = 0; | |
244 | pgd_t *pgd; | |
516295e5 | 245 | pud_t *pud; |
88c58f3b RK |
246 | pmd_t *pmd; |
247 | pte_t *pte; | |
248 | int i = 0; | |
99d1717d | 249 | unsigned long base = consistent_base; |
53cbcbcf | 250 | unsigned long num_ptes = (CONSISTENT_END - base) >> PMD_SHIFT; |
99d1717d JM |
251 | |
252 | consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL); | |
253 | if (!consistent_pte) { | |
254 | pr_err("%s: no memory\n", __func__); | |
255 | return -ENOMEM; | |
256 | } | |
257 | ||
258 | pr_debug("DMA memory: 0x%08lx - 0x%08lx:\n", base, CONSISTENT_END); | |
259 | consistent_head.vm_start = base; | |
88c58f3b RK |
260 | |
261 | do { | |
262 | pgd = pgd_offset(&init_mm, base); | |
516295e5 RK |
263 | |
264 | pud = pud_alloc(&init_mm, pgd, base); | |
265 | if (!pud) { | |
6b6f770b | 266 | pr_err("%s: no pud tables\n", __func__); |
516295e5 RK |
267 | ret = -ENOMEM; |
268 | break; | |
269 | } | |
270 | ||
271 | pmd = pmd_alloc(&init_mm, pud, base); | |
88c58f3b | 272 | if (!pmd) { |
6b6f770b | 273 | pr_err("%s: no pmd tables\n", __func__); |
88c58f3b RK |
274 | ret = -ENOMEM; |
275 | break; | |
276 | } | |
277 | WARN_ON(!pmd_none(*pmd)); | |
278 | ||
279 | pte = pte_alloc_kernel(pmd, base); | |
280 | if (!pte) { | |
6b6f770b | 281 | pr_err("%s: no pte tables\n", __func__); |
88c58f3b RK |
282 | ret = -ENOMEM; |
283 | break; | |
284 | } | |
285 | ||
286 | consistent_pte[i++] = pte; | |
e73fc88e | 287 | base += PMD_SIZE; |
88c58f3b RK |
288 | } while (base < CONSISTENT_END); |
289 | ||
290 | return ret; | |
291 | } | |
292 | ||
293 | core_initcall(consistent_init); | |
294 | ||
1da177e4 | 295 | static void * |
45cd5290 RK |
296 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, |
297 | const void *caller) | |
1da177e4 | 298 | { |
13ccf3ad | 299 | struct arm_vmregion *c; |
5bc23d32 RK |
300 | size_t align; |
301 | int bit; | |
1da177e4 | 302 | |
99d1717d | 303 | if (!consistent_pte) { |
6b6f770b | 304 | pr_err("%s: not initialised\n", __func__); |
ebd7a845 | 305 | dump_stack(); |
ebd7a845 RK |
306 | return NULL; |
307 | } | |
308 | ||
5bc23d32 RK |
309 | /* |
310 | * Align the virtual region allocation - maximum alignment is | |
311 | * a section size, minimum is a page size. This helps reduce | |
312 | * fragmentation of the DMA space, and also prevents allocations | |
313 | * smaller than a section from crossing a section boundary. | |
314 | */ | |
c947f69f | 315 | bit = fls(size - 1); |
5bc23d32 RK |
316 | if (bit > SECTION_SHIFT) |
317 | bit = SECTION_SHIFT; | |
318 | align = 1 << bit; | |
319 | ||
1da177e4 LT |
320 | /* |
321 | * Allocate a virtual address in the consistent mapping region. | |
322 | */ | |
5bc23d32 | 323 | c = arm_vmregion_alloc(&consistent_head, align, size, |
45cd5290 | 324 | gfp & ~(__GFP_DMA | __GFP_HIGHMEM), caller); |
1da177e4 | 325 | if (c) { |
37134cd5 | 326 | pte_t *pte; |
37134cd5 KH |
327 | int idx = CONSISTENT_PTE_INDEX(c->vm_start); |
328 | u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
1da177e4 | 329 | |
37134cd5 | 330 | pte = consistent_pte[idx] + off; |
1da177e4 LT |
331 | c->vm_pages = page; |
332 | ||
1da177e4 LT |
333 | do { |
334 | BUG_ON(!pte_none(*pte)); | |
335 | ||
ad1ae2fe | 336 | set_pte_ext(pte, mk_pte(page, prot), 0); |
1da177e4 LT |
337 | page++; |
338 | pte++; | |
37134cd5 KH |
339 | off++; |
340 | if (off >= PTRS_PER_PTE) { | |
341 | off = 0; | |
342 | pte = consistent_pte[++idx]; | |
343 | } | |
1da177e4 LT |
344 | } while (size -= PAGE_SIZE); |
345 | ||
2be23c47 RK |
346 | dsb(); |
347 | ||
1da177e4 LT |
348 | return (void *)c->vm_start; |
349 | } | |
1da177e4 LT |
350 | return NULL; |
351 | } | |
695ae0af RK |
352 | |
353 | static void __dma_free_remap(void *cpu_addr, size_t size) | |
354 | { | |
355 | struct arm_vmregion *c; | |
356 | unsigned long addr; | |
357 | pte_t *ptep; | |
358 | int idx; | |
359 | u32 off; | |
360 | ||
361 | c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr); | |
362 | if (!c) { | |
6b6f770b | 363 | pr_err("%s: trying to free invalid coherent area: %p\n", |
695ae0af RK |
364 | __func__, cpu_addr); |
365 | dump_stack(); | |
366 | return; | |
367 | } | |
368 | ||
369 | if ((c->vm_end - c->vm_start) != size) { | |
6b6f770b | 370 | pr_err("%s: freeing wrong coherent size (%ld != %d)\n", |
695ae0af RK |
371 | __func__, c->vm_end - c->vm_start, size); |
372 | dump_stack(); | |
373 | size = c->vm_end - c->vm_start; | |
374 | } | |
375 | ||
376 | idx = CONSISTENT_PTE_INDEX(c->vm_start); | |
377 | off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
378 | ptep = consistent_pte[idx] + off; | |
379 | addr = c->vm_start; | |
380 | do { | |
381 | pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep); | |
695ae0af RK |
382 | |
383 | ptep++; | |
384 | addr += PAGE_SIZE; | |
385 | off++; | |
386 | if (off >= PTRS_PER_PTE) { | |
387 | off = 0; | |
388 | ptep = consistent_pte[++idx]; | |
389 | } | |
390 | ||
acaac256 | 391 | if (pte_none(pte) || !pte_present(pte)) |
6b6f770b MS |
392 | pr_crit("%s: bad page in kernel page table\n", |
393 | __func__); | |
695ae0af RK |
394 | } while (size -= PAGE_SIZE); |
395 | ||
396 | flush_tlb_kernel_range(c->vm_start, c->vm_end); | |
397 | ||
398 | arm_vmregion_free(&consistent_head, c); | |
399 | } | |
400 | ||
ab6494f0 | 401 | #else /* !CONFIG_MMU */ |
695ae0af | 402 | |
45cd5290 | 403 | #define __dma_alloc_remap(page, size, gfp, prot, c) page_address(page) |
31ebf944 RK |
404 | #define __dma_free_remap(addr, size) do { } while (0) |
405 | ||
406 | #endif /* CONFIG_MMU */ | |
407 | ||
ab6494f0 CM |
408 | static void * |
409 | __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, | |
45cd5290 | 410 | pgprot_t prot, const void *caller) |
ab6494f0 | 411 | { |
04da5694 | 412 | struct page *page; |
31ebf944 | 413 | void *addr; |
ab6494f0 | 414 | |
ea2e7057 SB |
415 | /* |
416 | * Following is a work-around (a.k.a. hack) to prevent pages | |
417 | * with __GFP_COMP being passed to split_page() which cannot | |
418 | * handle them. The real problem is that this flag probably | |
419 | * should be 0 on ARM as it is not supported on this | |
420 | * platform; see CONFIG_HUGETLBFS. | |
421 | */ | |
422 | gfp &= ~(__GFP_COMP); | |
423 | ||
553ac788 | 424 | *handle = DMA_ERROR_CODE; |
04da5694 | 425 | size = PAGE_ALIGN(size); |
ab6494f0 | 426 | |
04da5694 RK |
427 | page = __dma_alloc_buffer(dev, size, gfp); |
428 | if (!page) | |
429 | return NULL; | |
ab6494f0 | 430 | |
31ebf944 | 431 | if (!arch_is_coherent()) |
45cd5290 | 432 | addr = __dma_alloc_remap(page, size, gfp, prot, caller); |
31ebf944 RK |
433 | else |
434 | addr = page_address(page); | |
695ae0af | 435 | |
31ebf944 | 436 | if (addr) |
9eedd963 | 437 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
d8e89b47 RK |
438 | else |
439 | __dma_free_buffer(page, size); | |
695ae0af | 440 | |
31ebf944 RK |
441 | return addr; |
442 | } | |
1da177e4 LT |
443 | |
444 | /* | |
445 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
446 | * virtual and bus address for that space. | |
447 | */ | |
448 | void * | |
f9e3214a | 449 | dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 | 450 | { |
1fe53268 DES |
451 | void *memory; |
452 | ||
453 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
454 | return memory; | |
455 | ||
1da177e4 | 456 | return __dma_alloc(dev, size, handle, gfp, |
45cd5290 RK |
457 | pgprot_dmacoherent(pgprot_kernel), |
458 | __builtin_return_address(0)); | |
1da177e4 LT |
459 | } |
460 | EXPORT_SYMBOL(dma_alloc_coherent); | |
461 | ||
462 | /* | |
463 | * Allocate a writecombining region, in much the same way as | |
464 | * dma_alloc_coherent above. | |
465 | */ | |
466 | void * | |
f9e3214a | 467 | dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 LT |
468 | { |
469 | return __dma_alloc(dev, size, handle, gfp, | |
45cd5290 RK |
470 | pgprot_writecombine(pgprot_kernel), |
471 | __builtin_return_address(0)); | |
1da177e4 LT |
472 | } |
473 | EXPORT_SYMBOL(dma_alloc_writecombine); | |
474 | ||
475 | static int dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
476 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
477 | { | |
ab6494f0 CM |
478 | int ret = -ENXIO; |
479 | #ifdef CONFIG_MMU | |
13ccf3ad RK |
480 | unsigned long user_size, kern_size; |
481 | struct arm_vmregion *c; | |
1da177e4 | 482 | |
47142f07 MS |
483 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
484 | return ret; | |
485 | ||
1da177e4 LT |
486 | user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
487 | ||
13ccf3ad | 488 | c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr); |
1da177e4 LT |
489 | if (c) { |
490 | unsigned long off = vma->vm_pgoff; | |
491 | ||
492 | kern_size = (c->vm_end - c->vm_start) >> PAGE_SHIFT; | |
493 | ||
494 | if (off < kern_size && | |
495 | user_size <= (kern_size - off)) { | |
1da177e4 LT |
496 | ret = remap_pfn_range(vma, vma->vm_start, |
497 | page_to_pfn(c->vm_pages) + off, | |
498 | user_size << PAGE_SHIFT, | |
499 | vma->vm_page_prot); | |
500 | } | |
501 | } | |
ab6494f0 | 502 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
503 | |
504 | return ret; | |
505 | } | |
506 | ||
507 | int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, | |
508 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
509 | { | |
26a26d32 | 510 | vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot); |
1da177e4 LT |
511 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); |
512 | } | |
513 | EXPORT_SYMBOL(dma_mmap_coherent); | |
514 | ||
515 | int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma, | |
516 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
517 | { | |
518 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
519 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); | |
520 | } | |
521 | EXPORT_SYMBOL(dma_mmap_writecombine); | |
522 | ||
523 | /* | |
524 | * free a page as defined by the above mapping. | |
5edf71ae | 525 | * Must not be called with IRQs disabled. |
1da177e4 LT |
526 | */ |
527 | void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle) | |
528 | { | |
5edf71ae RK |
529 | WARN_ON(irqs_disabled()); |
530 | ||
1fe53268 DES |
531 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
532 | return; | |
533 | ||
3e82d012 RK |
534 | size = PAGE_ALIGN(size); |
535 | ||
695ae0af RK |
536 | if (!arch_is_coherent()) |
537 | __dma_free_remap(cpu_addr, size); | |
7a9a32a9 | 538 | |
9eedd963 | 539 | __dma_free_buffer(pfn_to_page(dma_to_pfn(dev, handle)), size); |
1da177e4 LT |
540 | } |
541 | EXPORT_SYMBOL(dma_free_coherent); | |
542 | ||
4ea0d737 | 543 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
544 | size_t size, enum dma_data_direction dir, |
545 | void (*op)(const void *, size_t, int)) | |
43377453 NP |
546 | { |
547 | /* | |
548 | * A single sg entry may refer to multiple physically contiguous | |
549 | * pages. But we still need to process highmem pages individually. | |
550 | * If highmem is not configured then the bulk of this loop gets | |
551 | * optimized out. | |
552 | */ | |
553 | size_t left = size; | |
554 | do { | |
555 | size_t len = left; | |
93f1d629 RK |
556 | void *vaddr; |
557 | ||
558 | if (PageHighMem(page)) { | |
559 | if (len + offset > PAGE_SIZE) { | |
560 | if (offset >= PAGE_SIZE) { | |
561 | page += offset / PAGE_SIZE; | |
562 | offset %= PAGE_SIZE; | |
563 | } | |
564 | len = PAGE_SIZE - offset; | |
565 | } | |
566 | vaddr = kmap_high_get(page); | |
567 | if (vaddr) { | |
568 | vaddr += offset; | |
a9c9147e | 569 | op(vaddr, len, dir); |
93f1d629 | 570 | kunmap_high(page); |
7e5a69e8 | 571 | } else if (cache_is_vipt()) { |
39af22a7 NP |
572 | /* unmapped pages might still be cached */ |
573 | vaddr = kmap_atomic(page); | |
7e5a69e8 | 574 | op(vaddr + offset, len, dir); |
39af22a7 | 575 | kunmap_atomic(vaddr); |
43377453 | 576 | } |
93f1d629 RK |
577 | } else { |
578 | vaddr = page_address(page) + offset; | |
a9c9147e | 579 | op(vaddr, len, dir); |
43377453 | 580 | } |
43377453 NP |
581 | offset = 0; |
582 | page++; | |
583 | left -= len; | |
584 | } while (left); | |
585 | } | |
4ea0d737 RK |
586 | |
587 | void ___dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
588 | size_t size, enum dma_data_direction dir) | |
589 | { | |
65af191a | 590 | unsigned long paddr; |
65af191a | 591 | |
a9c9147e | 592 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
593 | |
594 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
595 | if (dir == DMA_FROM_DEVICE) { |
596 | outer_inv_range(paddr, paddr + size); | |
597 | } else { | |
598 | outer_clean_range(paddr, paddr + size); | |
599 | } | |
600 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 RK |
601 | } |
602 | EXPORT_SYMBOL(___dma_page_cpu_to_dev); | |
603 | ||
604 | void ___dma_page_dev_to_cpu(struct page *page, unsigned long off, | |
605 | size_t size, enum dma_data_direction dir) | |
606 | { | |
2ffe2da3 RK |
607 | unsigned long paddr = page_to_phys(page) + off; |
608 | ||
609 | /* FIXME: non-speculating: not required */ | |
610 | /* don't bother invalidating if DMA to device */ | |
611 | if (dir != DMA_TO_DEVICE) | |
612 | outer_inv_range(paddr, paddr + size); | |
613 | ||
a9c9147e | 614 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
c0177800 CM |
615 | |
616 | /* | |
617 | * Mark the D-cache clean for this page to avoid extra flushing. | |
618 | */ | |
619 | if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE) | |
620 | set_bit(PG_dcache_clean, &page->flags); | |
4ea0d737 RK |
621 | } |
622 | EXPORT_SYMBOL(___dma_page_dev_to_cpu); | |
43377453 | 623 | |
afd1a321 | 624 | /** |
2a550e73 | 625 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
626 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
627 | * @sg: list of buffers | |
628 | * @nents: number of buffers to map | |
629 | * @dir: DMA transfer direction | |
630 | * | |
631 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
632 | * This is the scatter-gather version of the dma_map_single interface. | |
633 | * Here the scatter gather list elements are each tagged with the | |
634 | * appropriate dma address and length. They are obtained via | |
635 | * sg_dma_{address,length}. | |
636 | * | |
637 | * Device ownership issues as mentioned for dma_map_single are the same | |
638 | * here. | |
639 | */ | |
2dc6a016 MS |
640 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
641 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 642 | { |
2a550e73 | 643 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 644 | struct scatterlist *s; |
01135d92 | 645 | int i, j; |
afd1a321 RK |
646 | |
647 | for_each_sg(sg, s, nents, i) { | |
2a550e73 MS |
648 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
649 | s->length, dir, attrs); | |
01135d92 RK |
650 | if (dma_mapping_error(dev, s->dma_address)) |
651 | goto bad_mapping; | |
afd1a321 | 652 | } |
afd1a321 | 653 | return nents; |
01135d92 RK |
654 | |
655 | bad_mapping: | |
656 | for_each_sg(sg, s, i, j) | |
2a550e73 | 657 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 658 | return 0; |
afd1a321 | 659 | } |
afd1a321 RK |
660 | |
661 | /** | |
2a550e73 | 662 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
663 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
664 | * @sg: list of buffers | |
0adfca6f | 665 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
666 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
667 | * | |
668 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
669 | * rules concerning calls here are the same as for dma_unmap_single(). | |
670 | */ | |
2dc6a016 MS |
671 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
672 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 673 | { |
2a550e73 | 674 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 675 | struct scatterlist *s; |
2a550e73 | 676 | |
01135d92 RK |
677 | int i; |
678 | ||
679 | for_each_sg(sg, s, nents, i) | |
2a550e73 | 680 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 681 | } |
afd1a321 RK |
682 | |
683 | /** | |
2a550e73 | 684 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
685 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
686 | * @sg: list of buffers | |
687 | * @nents: number of buffers to map (returned from dma_map_sg) | |
688 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
689 | */ | |
2dc6a016 | 690 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
691 | int nents, enum dma_data_direction dir) |
692 | { | |
2a550e73 | 693 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
694 | struct scatterlist *s; |
695 | int i; | |
696 | ||
2a550e73 MS |
697 | for_each_sg(sg, s, nents, i) |
698 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
699 | dir); | |
afd1a321 | 700 | } |
afd1a321 RK |
701 | |
702 | /** | |
2a550e73 | 703 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
704 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
705 | * @sg: list of buffers | |
706 | * @nents: number of buffers to map (returned from dma_map_sg) | |
707 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
708 | */ | |
2dc6a016 | 709 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
710 | int nents, enum dma_data_direction dir) |
711 | { | |
2a550e73 | 712 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
713 | struct scatterlist *s; |
714 | int i; | |
715 | ||
2a550e73 MS |
716 | for_each_sg(sg, s, nents, i) |
717 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
718 | dir); | |
afd1a321 | 719 | } |
24056f52 | 720 | |
022ae537 RK |
721 | /* |
722 | * Return whether the given device DMA address mask can be supported | |
723 | * properly. For example, if your device can only drive the low 24-bits | |
724 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
725 | * to this function. | |
726 | */ | |
727 | int dma_supported(struct device *dev, u64 mask) | |
728 | { | |
729 | if (mask < (u64)arm_dma_limit) | |
730 | return 0; | |
731 | return 1; | |
732 | } | |
733 | EXPORT_SYMBOL(dma_supported); | |
734 | ||
2dc6a016 | 735 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
736 | { |
737 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
738 | return -EIO; | |
739 | ||
740 | #ifndef CONFIG_DMABOUNCE | |
741 | *dev->dma_mask = dma_mask; | |
742 | #endif | |
743 | ||
744 | return 0; | |
745 | } | |
022ae537 | 746 | |
24056f52 RK |
747 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
748 | ||
749 | static int __init dma_debug_do_init(void) | |
750 | { | |
45cd5290 RK |
751 | #ifdef CONFIG_MMU |
752 | arm_vmregion_create_proc("dma-mappings", &consistent_head); | |
753 | #endif | |
24056f52 RK |
754 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); |
755 | return 0; | |
756 | } | |
757 | fs_initcall(dma_debug_do_init); |