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Commit | Line | Data |
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1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
11a5aa32 | 12 | #include <linux/bootmem.h> |
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/mm.h> | |
5a0e3ad6 | 15 | #include <linux/gfp.h> |
1da177e4 LT |
16 | #include <linux/errno.h> |
17 | #include <linux/list.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/dma-mapping.h> | |
c7909509 | 21 | #include <linux/dma-contiguous.h> |
39af22a7 | 22 | #include <linux/highmem.h> |
c7909509 | 23 | #include <linux/memblock.h> |
99d1717d | 24 | #include <linux/slab.h> |
4ce63fcd | 25 | #include <linux/iommu.h> |
e9da6e99 | 26 | #include <linux/io.h> |
4ce63fcd | 27 | #include <linux/vmalloc.h> |
158e8bfe | 28 | #include <linux/sizes.h> |
1da177e4 | 29 | |
23759dc6 | 30 | #include <asm/memory.h> |
43377453 | 31 | #include <asm/highmem.h> |
1da177e4 | 32 | #include <asm/cacheflush.h> |
1da177e4 | 33 | #include <asm/tlbflush.h> |
99d1717d | 34 | #include <asm/mach/arch.h> |
4ce63fcd | 35 | #include <asm/dma-iommu.h> |
c7909509 MS |
36 | #include <asm/mach/map.h> |
37 | #include <asm/system_info.h> | |
38 | #include <asm/dma-contiguous.h> | |
37134cd5 | 39 | |
022ae537 RK |
40 | #include "mm.h" |
41 | ||
15237e1f MS |
42 | /* |
43 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
44 | * is either exclusively owned by the CPU (and therefore may be accessed | |
45 | * by it) or exclusively owned by the DMA device. These helper functions | |
46 | * represent the transitions between these two ownership states. | |
47 | * | |
48 | * Note, however, that on later ARMs, this notion does not work due to | |
49 | * speculative prefetches. We model our approach on the assumption that | |
50 | * the CPU does do speculative prefetches, which means we clean caches | |
51 | * before transfers and delay cache invalidation until transfer completion. | |
52 | * | |
15237e1f | 53 | */ |
51fde349 | 54 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 55 | size_t, enum dma_data_direction); |
51fde349 | 56 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
57 | size_t, enum dma_data_direction); |
58 | ||
2dc6a016 MS |
59 | /** |
60 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
61 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
62 | * @page: page that buffer resides in | |
63 | * @offset: offset into page for start of buffer | |
64 | * @size: size of buffer to map | |
65 | * @dir: DMA transfer direction | |
66 | * | |
67 | * Ensure that any data held in the cache is appropriately discarded | |
68 | * or written back. | |
69 | * | |
70 | * The device owns this memory once this call has completed. The CPU | |
71 | * can regain ownership by calling dma_unmap_page(). | |
72 | */ | |
51fde349 | 73 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
74 | unsigned long offset, size_t size, enum dma_data_direction dir, |
75 | struct dma_attrs *attrs) | |
76 | { | |
dd37e940 | 77 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
78 | __dma_page_cpu_to_dev(page, offset, size, dir); |
79 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
80 | } |
81 | ||
dd37e940 RH |
82 | static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page, |
83 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
84 | struct dma_attrs *attrs) | |
85 | { | |
86 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
87 | } | |
88 | ||
2dc6a016 MS |
89 | /** |
90 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
91 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
92 | * @handle: DMA address of buffer | |
93 | * @size: size of buffer (same as passed to dma_map_page) | |
94 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
95 | * | |
96 | * Unmap a page streaming mode DMA translation. The handle and size | |
97 | * must match what was provided in the previous dma_map_page() call. | |
98 | * All other usages are undefined. | |
99 | * | |
100 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
101 | * whatever the device wrote there. | |
102 | */ | |
51fde349 | 103 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
104 | size_t size, enum dma_data_direction dir, |
105 | struct dma_attrs *attrs) | |
106 | { | |
dd37e940 | 107 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
108 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
109 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
110 | } |
111 | ||
51fde349 | 112 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
113 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
114 | { | |
115 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
116 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 117 | __dma_page_dev_to_cpu(page, offset, size, dir); |
2dc6a016 MS |
118 | } |
119 | ||
51fde349 | 120 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
121 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
122 | { | |
123 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
124 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 125 | __dma_page_cpu_to_dev(page, offset, size, dir); |
2dc6a016 MS |
126 | } |
127 | ||
2dc6a016 | 128 | struct dma_map_ops arm_dma_ops = { |
f99d6034 MS |
129 | .alloc = arm_dma_alloc, |
130 | .free = arm_dma_free, | |
131 | .mmap = arm_dma_mmap, | |
dc2832e1 | 132 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
133 | .map_page = arm_dma_map_page, |
134 | .unmap_page = arm_dma_unmap_page, | |
135 | .map_sg = arm_dma_map_sg, | |
136 | .unmap_sg = arm_dma_unmap_sg, | |
137 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
138 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
139 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
140 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
141 | .set_dma_mask = arm_dma_set_mask, | |
142 | }; | |
143 | EXPORT_SYMBOL(arm_dma_ops); | |
144 | ||
dd37e940 RH |
145 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, |
146 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs); | |
147 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
148 | dma_addr_t handle, struct dma_attrs *attrs); | |
149 | ||
150 | struct dma_map_ops arm_coherent_dma_ops = { | |
151 | .alloc = arm_coherent_dma_alloc, | |
152 | .free = arm_coherent_dma_free, | |
153 | .mmap = arm_dma_mmap, | |
154 | .get_sgtable = arm_dma_get_sgtable, | |
155 | .map_page = arm_coherent_dma_map_page, | |
156 | .map_sg = arm_dma_map_sg, | |
157 | .set_dma_mask = arm_dma_set_mask, | |
158 | }; | |
159 | EXPORT_SYMBOL(arm_coherent_dma_ops); | |
160 | ||
9f28cde0 RK |
161 | static int __dma_supported(struct device *dev, u64 mask, bool warn) |
162 | { | |
163 | unsigned long max_dma_pfn; | |
164 | ||
165 | /* | |
166 | * If the mask allows for more memory than we can address, | |
167 | * and we actually have that much memory, then we must | |
168 | * indicate that DMA to this device is not supported. | |
169 | */ | |
170 | if (sizeof(mask) != sizeof(dma_addr_t) && | |
171 | mask > (dma_addr_t)~0 && | |
172 | dma_to_pfn(dev, ~0) < max_pfn) { | |
173 | if (warn) { | |
174 | dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", | |
175 | mask); | |
176 | dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n"); | |
177 | } | |
178 | return 0; | |
179 | } | |
180 | ||
181 | max_dma_pfn = min(max_pfn, arm_dma_pfn_limit); | |
182 | ||
183 | /* | |
184 | * Translate the device's DMA mask to a PFN limit. This | |
185 | * PFN number includes the page which we can DMA to. | |
186 | */ | |
187 | if (dma_to_pfn(dev, mask) < max_dma_pfn) { | |
188 | if (warn) | |
189 | dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", | |
190 | mask, | |
191 | dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, | |
192 | max_dma_pfn + 1); | |
193 | return 0; | |
194 | } | |
195 | ||
196 | return 1; | |
197 | } | |
198 | ||
ab6494f0 CM |
199 | static u64 get_coherent_dma_mask(struct device *dev) |
200 | { | |
4dcfa600 | 201 | u64 mask = (u64)DMA_BIT_MASK(32); |
ab6494f0 CM |
202 | |
203 | if (dev) { | |
204 | mask = dev->coherent_dma_mask; | |
205 | ||
206 | /* | |
207 | * Sanity check the DMA mask - it must be non-zero, and | |
208 | * must be able to be satisfied by a DMA allocation. | |
209 | */ | |
210 | if (mask == 0) { | |
211 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
212 | return 0; | |
213 | } | |
214 | ||
9f28cde0 | 215 | if (!__dma_supported(dev, mask, true)) |
ab6494f0 | 216 | return 0; |
ab6494f0 | 217 | } |
1da177e4 | 218 | |
ab6494f0 CM |
219 | return mask; |
220 | } | |
221 | ||
c7909509 MS |
222 | static void __dma_clear_buffer(struct page *page, size_t size) |
223 | { | |
c7909509 MS |
224 | /* |
225 | * Ensure that the allocated pages are zeroed, and that any data | |
226 | * lurking in the kernel direct-mapped region is invalidated. | |
227 | */ | |
9848e48f MS |
228 | if (PageHighMem(page)) { |
229 | phys_addr_t base = __pfn_to_phys(page_to_pfn(page)); | |
230 | phys_addr_t end = base + size; | |
231 | while (size > 0) { | |
232 | void *ptr = kmap_atomic(page); | |
233 | memset(ptr, 0, PAGE_SIZE); | |
234 | dmac_flush_range(ptr, ptr + PAGE_SIZE); | |
235 | kunmap_atomic(ptr); | |
236 | page++; | |
237 | size -= PAGE_SIZE; | |
238 | } | |
239 | outer_flush_range(base, end); | |
240 | } else { | |
241 | void *ptr = page_address(page); | |
4ce63fcd MS |
242 | memset(ptr, 0, size); |
243 | dmac_flush_range(ptr, ptr + size); | |
244 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
245 | } | |
c7909509 MS |
246 | } |
247 | ||
7a9a32a9 RK |
248 | /* |
249 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
250 | * specified gfp mask. Note that 'size' must be page aligned. | |
251 | */ | |
252 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
253 | { | |
254 | unsigned long order = get_order(size); | |
255 | struct page *page, *p, *e; | |
7a9a32a9 RK |
256 | |
257 | page = alloc_pages(gfp, order); | |
258 | if (!page) | |
259 | return NULL; | |
260 | ||
261 | /* | |
262 | * Now split the huge page and free the excess pages | |
263 | */ | |
264 | split_page(page, order); | |
265 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
266 | __free_page(p); | |
267 | ||
c7909509 | 268 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
269 | |
270 | return page; | |
271 | } | |
272 | ||
273 | /* | |
274 | * Free a DMA buffer. 'size' must be page aligned. | |
275 | */ | |
276 | static void __dma_free_buffer(struct page *page, size_t size) | |
277 | { | |
278 | struct page *e = page + (size >> PAGE_SHIFT); | |
279 | ||
280 | while (page < e) { | |
281 | __free_page(page); | |
282 | page++; | |
283 | } | |
284 | } | |
285 | ||
ab6494f0 | 286 | #ifdef CONFIG_MMU |
e9da6e99 | 287 | #ifdef CONFIG_HUGETLB_PAGE |
1355e2a6 | 288 | #warning ARM Coherent DMA allocator does not (yet) support huge TLB |
e9da6e99 | 289 | #endif |
a5e9d38b | 290 | |
e9da6e99 | 291 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
9848e48f MS |
292 | pgprot_t prot, struct page **ret_page, |
293 | const void *caller); | |
99d1717d | 294 | |
e9da6e99 MS |
295 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
296 | pgprot_t prot, struct page **ret_page, | |
297 | const void *caller); | |
99d1717d | 298 | |
e9da6e99 MS |
299 | static void * |
300 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
301 | const void *caller) | |
99d1717d | 302 | { |
e9da6e99 MS |
303 | struct vm_struct *area; |
304 | unsigned long addr; | |
99d1717d | 305 | |
e9da6e99 MS |
306 | /* |
307 | * DMA allocation can be mapped to user space, so lets | |
308 | * set VM_USERMAP flags too. | |
309 | */ | |
310 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
311 | caller); | |
312 | if (!area) | |
313 | return NULL; | |
314 | addr = (unsigned long)area->addr; | |
315 | area->phys_addr = __pfn_to_phys(page_to_pfn(page)); | |
99d1717d | 316 | |
e9da6e99 MS |
317 | if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) { |
318 | vunmap((void *)addr); | |
319 | return NULL; | |
320 | } | |
321 | return (void *)addr; | |
99d1717d | 322 | } |
1da177e4 | 323 | |
e9da6e99 | 324 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 325 | { |
e9da6e99 MS |
326 | unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP; |
327 | struct vm_struct *area = find_vm_area(cpu_addr); | |
328 | if (!area || (area->flags & flags) != flags) { | |
329 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
330 | return; | |
99d1717d | 331 | } |
e9da6e99 MS |
332 | unmap_kernel_range((unsigned long)cpu_addr, size); |
333 | vunmap(cpu_addr); | |
88c58f3b | 334 | } |
88c58f3b | 335 | |
6e5267aa MS |
336 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
337 | ||
e9da6e99 MS |
338 | struct dma_pool { |
339 | size_t size; | |
340 | spinlock_t lock; | |
341 | unsigned long *bitmap; | |
342 | unsigned long nr_pages; | |
343 | void *vaddr; | |
6b3fe472 | 344 | struct page **pages; |
c7909509 MS |
345 | }; |
346 | ||
e9da6e99 | 347 | static struct dma_pool atomic_pool = { |
6e5267aa | 348 | .size = DEFAULT_DMA_COHERENT_POOL_SIZE, |
e9da6e99 | 349 | }; |
c7909509 MS |
350 | |
351 | static int __init early_coherent_pool(char *p) | |
352 | { | |
e9da6e99 | 353 | atomic_pool.size = memparse(p, &p); |
c7909509 MS |
354 | return 0; |
355 | } | |
356 | early_param("coherent_pool", early_coherent_pool); | |
357 | ||
6e5267aa MS |
358 | void __init init_dma_coherent_pool_size(unsigned long size) |
359 | { | |
360 | /* | |
361 | * Catch any attempt to set the pool size too late. | |
362 | */ | |
363 | BUG_ON(atomic_pool.vaddr); | |
364 | ||
365 | /* | |
366 | * Set architecture specific coherent pool size only if | |
367 | * it has not been changed by kernel command line parameter. | |
368 | */ | |
369 | if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE) | |
370 | atomic_pool.size = size; | |
371 | } | |
372 | ||
c7909509 MS |
373 | /* |
374 | * Initialise the coherent pool for atomic allocations. | |
375 | */ | |
e9da6e99 | 376 | static int __init atomic_pool_init(void) |
c7909509 | 377 | { |
e9da6e99 | 378 | struct dma_pool *pool = &atomic_pool; |
71b55663 | 379 | pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); |
9d1400cf | 380 | gfp_t gfp = GFP_KERNEL | GFP_DMA; |
e9da6e99 MS |
381 | unsigned long nr_pages = pool->size >> PAGE_SHIFT; |
382 | unsigned long *bitmap; | |
c7909509 | 383 | struct page *page; |
6b3fe472 | 384 | struct page **pages; |
c7909509 | 385 | void *ptr; |
e9da6e99 | 386 | int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long); |
c7909509 | 387 | |
e9da6e99 MS |
388 | bitmap = kzalloc(bitmap_size, GFP_KERNEL); |
389 | if (!bitmap) | |
390 | goto no_bitmap; | |
c7909509 | 391 | |
6b3fe472 HD |
392 | pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL); |
393 | if (!pages) | |
394 | goto no_pages; | |
395 | ||
f825c736 | 396 | if (IS_ENABLED(CONFIG_DMA_CMA)) |
9848e48f MS |
397 | ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page, |
398 | atomic_pool_init); | |
e9da6e99 | 399 | else |
9d1400cf MS |
400 | ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page, |
401 | atomic_pool_init); | |
c7909509 | 402 | if (ptr) { |
6b3fe472 HD |
403 | int i; |
404 | ||
405 | for (i = 0; i < nr_pages; i++) | |
406 | pages[i] = page + i; | |
407 | ||
e9da6e99 MS |
408 | spin_lock_init(&pool->lock); |
409 | pool->vaddr = ptr; | |
6b3fe472 | 410 | pool->pages = pages; |
e9da6e99 MS |
411 | pool->bitmap = bitmap; |
412 | pool->nr_pages = nr_pages; | |
413 | pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n", | |
414 | (unsigned)pool->size / 1024); | |
c7909509 MS |
415 | return 0; |
416 | } | |
ec10665c SK |
417 | |
418 | kfree(pages); | |
6b3fe472 | 419 | no_pages: |
e9da6e99 MS |
420 | kfree(bitmap); |
421 | no_bitmap: | |
422 | pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n", | |
423 | (unsigned)pool->size / 1024); | |
c7909509 MS |
424 | return -ENOMEM; |
425 | } | |
426 | /* | |
427 | * CMA is activated by core_initcall, so we must be called after it. | |
428 | */ | |
e9da6e99 | 429 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
430 | |
431 | struct dma_contig_early_reserve { | |
432 | phys_addr_t base; | |
433 | unsigned long size; | |
434 | }; | |
435 | ||
436 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
437 | ||
438 | static int dma_mmu_remap_num __initdata; | |
439 | ||
440 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
441 | { | |
442 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
443 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
444 | dma_mmu_remap_num++; | |
445 | } | |
446 | ||
447 | void __init dma_contiguous_remap(void) | |
448 | { | |
449 | int i; | |
450 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
451 | phys_addr_t start = dma_mmu_remap[i].base; | |
452 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
453 | struct map_desc map; | |
454 | unsigned long addr; | |
455 | ||
456 | if (end > arm_lowmem_limit) | |
457 | end = arm_lowmem_limit; | |
458 | if (start >= end) | |
39f78e70 | 459 | continue; |
c7909509 MS |
460 | |
461 | map.pfn = __phys_to_pfn(start); | |
462 | map.virtual = __phys_to_virt(start); | |
463 | map.length = end - start; | |
464 | map.type = MT_MEMORY_DMA_READY; | |
465 | ||
466 | /* | |
467 | * Clear previous low-memory mapping | |
468 | */ | |
469 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 470 | addr += PMD_SIZE) |
c7909509 MS |
471 | pmd_clear(pmd_off_k(addr)); |
472 | ||
473 | iotable_init(&map, 1); | |
474 | } | |
475 | } | |
476 | ||
c7909509 MS |
477 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
478 | void *data) | |
479 | { | |
480 | struct page *page = virt_to_page(addr); | |
481 | pgprot_t prot = *(pgprot_t *)data; | |
482 | ||
483 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
484 | return 0; | |
485 | } | |
486 | ||
487 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
488 | { | |
489 | unsigned long start = (unsigned long) page_address(page); | |
490 | unsigned end = start + size; | |
491 | ||
492 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
c7909509 MS |
493 | flush_tlb_kernel_range(start, end); |
494 | } | |
495 | ||
496 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
497 | pgprot_t prot, struct page **ret_page, | |
498 | const void *caller) | |
499 | { | |
500 | struct page *page; | |
501 | void *ptr; | |
502 | page = __dma_alloc_buffer(dev, size, gfp); | |
503 | if (!page) | |
504 | return NULL; | |
505 | ||
506 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
507 | if (!ptr) { | |
508 | __dma_free_buffer(page, size); | |
509 | return NULL; | |
510 | } | |
511 | ||
512 | *ret_page = page; | |
513 | return ptr; | |
514 | } | |
515 | ||
e9da6e99 | 516 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 517 | { |
e9da6e99 MS |
518 | struct dma_pool *pool = &atomic_pool; |
519 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
520 | unsigned int pageno; | |
521 | unsigned long flags; | |
522 | void *ptr = NULL; | |
e4ea6918 | 523 | unsigned long align_mask; |
c7909509 | 524 | |
e9da6e99 MS |
525 | if (!pool->vaddr) { |
526 | WARN(1, "coherent pool not initialised!\n"); | |
c7909509 MS |
527 | return NULL; |
528 | } | |
529 | ||
530 | /* | |
531 | * Align the region allocation - allocations from pool are rather | |
532 | * small, so align them to their order in pages, minimum is a page | |
533 | * size. This helps reduce fragmentation of the DMA space. | |
534 | */ | |
e4ea6918 | 535 | align_mask = (1 << get_order(size)) - 1; |
e9da6e99 MS |
536 | |
537 | spin_lock_irqsave(&pool->lock, flags); | |
538 | pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages, | |
e4ea6918 | 539 | 0, count, align_mask); |
e9da6e99 MS |
540 | if (pageno < pool->nr_pages) { |
541 | bitmap_set(pool->bitmap, pageno, count); | |
542 | ptr = pool->vaddr + PAGE_SIZE * pageno; | |
6b3fe472 | 543 | *ret_page = pool->pages[pageno]; |
fb71285f MS |
544 | } else { |
545 | pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n" | |
546 | "Please increase it with coherent_pool= kernel parameter!\n", | |
547 | (unsigned)pool->size / 1024); | |
c7909509 | 548 | } |
e9da6e99 MS |
549 | spin_unlock_irqrestore(&pool->lock, flags); |
550 | ||
551 | return ptr; | |
c7909509 MS |
552 | } |
553 | ||
21d0a759 HD |
554 | static bool __in_atomic_pool(void *start, size_t size) |
555 | { | |
556 | struct dma_pool *pool = &atomic_pool; | |
557 | void *end = start + size; | |
558 | void *pool_start = pool->vaddr; | |
559 | void *pool_end = pool->vaddr + pool->size; | |
560 | ||
f3d87524 | 561 | if (start < pool_start || start >= pool_end) |
21d0a759 HD |
562 | return false; |
563 | ||
564 | if (end <= pool_end) | |
565 | return true; | |
566 | ||
567 | WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n", | |
568 | start, end - 1, pool_start, pool_end - 1); | |
569 | ||
570 | return false; | |
571 | } | |
572 | ||
e9da6e99 | 573 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 574 | { |
e9da6e99 MS |
575 | struct dma_pool *pool = &atomic_pool; |
576 | unsigned long pageno, count; | |
577 | unsigned long flags; | |
c7909509 | 578 | |
21d0a759 | 579 | if (!__in_atomic_pool(start, size)) |
c7909509 MS |
580 | return 0; |
581 | ||
e9da6e99 MS |
582 | pageno = (start - pool->vaddr) >> PAGE_SHIFT; |
583 | count = size >> PAGE_SHIFT; | |
584 | ||
585 | spin_lock_irqsave(&pool->lock, flags); | |
586 | bitmap_clear(pool->bitmap, pageno, count); | |
587 | spin_unlock_irqrestore(&pool->lock, flags); | |
588 | ||
c7909509 MS |
589 | return 1; |
590 | } | |
591 | ||
592 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
9848e48f MS |
593 | pgprot_t prot, struct page **ret_page, |
594 | const void *caller) | |
c7909509 MS |
595 | { |
596 | unsigned long order = get_order(size); | |
597 | size_t count = size >> PAGE_SHIFT; | |
598 | struct page *page; | |
9848e48f | 599 | void *ptr; |
c7909509 MS |
600 | |
601 | page = dma_alloc_from_contiguous(dev, count, order); | |
602 | if (!page) | |
603 | return NULL; | |
604 | ||
605 | __dma_clear_buffer(page, size); | |
c7909509 | 606 | |
9848e48f MS |
607 | if (PageHighMem(page)) { |
608 | ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller); | |
609 | if (!ptr) { | |
610 | dma_release_from_contiguous(dev, page, count); | |
611 | return NULL; | |
612 | } | |
613 | } else { | |
614 | __dma_remap(page, size, prot); | |
615 | ptr = page_address(page); | |
616 | } | |
c7909509 | 617 | *ret_page = page; |
9848e48f | 618 | return ptr; |
c7909509 MS |
619 | } |
620 | ||
621 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
9848e48f | 622 | void *cpu_addr, size_t size) |
c7909509 | 623 | { |
9848e48f MS |
624 | if (PageHighMem(page)) |
625 | __dma_free_remap(cpu_addr, size); | |
626 | else | |
71b55663 | 627 | __dma_remap(page, size, PAGE_KERNEL); |
c7909509 MS |
628 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); |
629 | } | |
630 | ||
f99d6034 MS |
631 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
632 | { | |
633 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
634 | pgprot_writecombine(prot) : | |
635 | pgprot_dmacoherent(prot); | |
636 | return prot; | |
637 | } | |
638 | ||
c7909509 MS |
639 | #define nommu() 0 |
640 | ||
ab6494f0 | 641 | #else /* !CONFIG_MMU */ |
695ae0af | 642 | |
c7909509 MS |
643 | #define nommu() 1 |
644 | ||
f99d6034 | 645 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
c7909509 | 646 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL |
e9da6e99 | 647 | #define __alloc_from_pool(size, ret_page) NULL |
9848e48f | 648 | #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL |
c7909509 | 649 | #define __free_from_pool(cpu_addr, size) 0 |
9848e48f | 650 | #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0) |
c7909509 | 651 | #define __dma_free_remap(cpu_addr, size) do { } while (0) |
31ebf944 RK |
652 | |
653 | #endif /* CONFIG_MMU */ | |
654 | ||
c7909509 MS |
655 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
656 | struct page **ret_page) | |
ab6494f0 | 657 | { |
c7909509 MS |
658 | struct page *page; |
659 | page = __dma_alloc_buffer(dev, size, gfp); | |
660 | if (!page) | |
661 | return NULL; | |
662 | ||
663 | *ret_page = page; | |
664 | return page_address(page); | |
665 | } | |
666 | ||
667 | ||
668 | ||
669 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
dd37e940 | 670 | gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller) |
c7909509 MS |
671 | { |
672 | u64 mask = get_coherent_dma_mask(dev); | |
3dd7ea92 | 673 | struct page *page = NULL; |
31ebf944 | 674 | void *addr; |
ab6494f0 | 675 | |
c7909509 MS |
676 | #ifdef CONFIG_DMA_API_DEBUG |
677 | u64 limit = (mask + 1) & ~mask; | |
678 | if (limit && size >= limit) { | |
679 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
680 | size, mask); | |
681 | return NULL; | |
682 | } | |
683 | #endif | |
684 | ||
685 | if (!mask) | |
686 | return NULL; | |
687 | ||
688 | if (mask < 0xffffffffULL) | |
689 | gfp |= GFP_DMA; | |
690 | ||
ea2e7057 SB |
691 | /* |
692 | * Following is a work-around (a.k.a. hack) to prevent pages | |
693 | * with __GFP_COMP being passed to split_page() which cannot | |
694 | * handle them. The real problem is that this flag probably | |
695 | * should be 0 on ARM as it is not supported on this | |
696 | * platform; see CONFIG_HUGETLBFS. | |
697 | */ | |
698 | gfp &= ~(__GFP_COMP); | |
699 | ||
553ac788 | 700 | *handle = DMA_ERROR_CODE; |
04da5694 | 701 | size = PAGE_ALIGN(size); |
ab6494f0 | 702 | |
dd37e940 | 703 | if (is_coherent || nommu()) |
c7909509 | 704 | addr = __alloc_simple_buffer(dev, size, gfp, &page); |
633dc92a | 705 | else if (!(gfp & __GFP_WAIT)) |
e9da6e99 | 706 | addr = __alloc_from_pool(size, &page); |
f825c736 | 707 | else if (!IS_ENABLED(CONFIG_DMA_CMA)) |
c7909509 | 708 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller); |
31ebf944 | 709 | else |
9848e48f | 710 | addr = __alloc_from_contiguous(dev, size, prot, &page, caller); |
695ae0af | 711 | |
31ebf944 | 712 | if (addr) |
9eedd963 | 713 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
695ae0af | 714 | |
31ebf944 RK |
715 | return addr; |
716 | } | |
1da177e4 LT |
717 | |
718 | /* | |
719 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
720 | * virtual and bus address for that space. | |
721 | */ | |
f99d6034 MS |
722 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
723 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 724 | { |
0ea1ec71 | 725 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
1fe53268 DES |
726 | void *memory; |
727 | ||
728 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
729 | return memory; | |
730 | ||
dd37e940 RH |
731 | return __dma_alloc(dev, size, handle, gfp, prot, false, |
732 | __builtin_return_address(0)); | |
733 | } | |
734 | ||
735 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, | |
736 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
737 | { | |
0ea1ec71 | 738 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
dd37e940 RH |
739 | void *memory; |
740 | ||
741 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
742 | return memory; | |
743 | ||
744 | return __dma_alloc(dev, size, handle, gfp, prot, true, | |
45cd5290 | 745 | __builtin_return_address(0)); |
1da177e4 | 746 | } |
1da177e4 LT |
747 | |
748 | /* | |
f99d6034 | 749 | * Create userspace mapping for the DMA-coherent memory. |
1da177e4 | 750 | */ |
f99d6034 MS |
751 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
752 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
753 | struct dma_attrs *attrs) | |
1da177e4 | 754 | { |
ab6494f0 CM |
755 | int ret = -ENXIO; |
756 | #ifdef CONFIG_MMU | |
50262a4b MS |
757 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
758 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 759 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
760 | unsigned long off = vma->vm_pgoff; |
761 | ||
f99d6034 MS |
762 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
763 | ||
47142f07 MS |
764 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
765 | return ret; | |
766 | ||
50262a4b MS |
767 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
768 | ret = remap_pfn_range(vma, vma->vm_start, | |
769 | pfn + off, | |
770 | vma->vm_end - vma->vm_start, | |
771 | vma->vm_page_prot); | |
772 | } | |
ab6494f0 | 773 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
774 | |
775 | return ret; | |
776 | } | |
777 | ||
1da177e4 | 778 | /* |
c7909509 | 779 | * Free a buffer as defined by the above mapping. |
1da177e4 | 780 | */ |
dd37e940 RH |
781 | static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
782 | dma_addr_t handle, struct dma_attrs *attrs, | |
783 | bool is_coherent) | |
1da177e4 | 784 | { |
c7909509 | 785 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
5edf71ae | 786 | |
1fe53268 DES |
787 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
788 | return; | |
789 | ||
3e82d012 RK |
790 | size = PAGE_ALIGN(size); |
791 | ||
dd37e940 | 792 | if (is_coherent || nommu()) { |
c7909509 | 793 | __dma_free_buffer(page, size); |
d9e0d149 AK |
794 | } else if (__free_from_pool(cpu_addr, size)) { |
795 | return; | |
f825c736 | 796 | } else if (!IS_ENABLED(CONFIG_DMA_CMA)) { |
695ae0af | 797 | __dma_free_remap(cpu_addr, size); |
c7909509 MS |
798 | __dma_free_buffer(page, size); |
799 | } else { | |
c7909509 MS |
800 | /* |
801 | * Non-atomic allocations cannot be freed with IRQs disabled | |
802 | */ | |
803 | WARN_ON(irqs_disabled()); | |
9848e48f | 804 | __free_from_contiguous(dev, page, cpu_addr, size); |
c7909509 | 805 | } |
1da177e4 | 806 | } |
afd1a321 | 807 | |
dd37e940 RH |
808 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
809 | dma_addr_t handle, struct dma_attrs *attrs) | |
810 | { | |
811 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, false); | |
812 | } | |
813 | ||
814 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
815 | dma_addr_t handle, struct dma_attrs *attrs) | |
816 | { | |
817 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, true); | |
818 | } | |
819 | ||
dc2832e1 MS |
820 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
821 | void *cpu_addr, dma_addr_t handle, size_t size, | |
822 | struct dma_attrs *attrs) | |
823 | { | |
824 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
825 | int ret; | |
826 | ||
827 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
828 | if (unlikely(ret)) | |
829 | return ret; | |
830 | ||
831 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
832 | return 0; | |
833 | } | |
834 | ||
4ea0d737 | 835 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
836 | size_t size, enum dma_data_direction dir, |
837 | void (*op)(const void *, size_t, int)) | |
43377453 | 838 | { |
15653371 RK |
839 | unsigned long pfn; |
840 | size_t left = size; | |
841 | ||
842 | pfn = page_to_pfn(page) + offset / PAGE_SIZE; | |
843 | offset %= PAGE_SIZE; | |
844 | ||
43377453 NP |
845 | /* |
846 | * A single sg entry may refer to multiple physically contiguous | |
847 | * pages. But we still need to process highmem pages individually. | |
848 | * If highmem is not configured then the bulk of this loop gets | |
849 | * optimized out. | |
850 | */ | |
43377453 NP |
851 | do { |
852 | size_t len = left; | |
93f1d629 RK |
853 | void *vaddr; |
854 | ||
15653371 RK |
855 | page = pfn_to_page(pfn); |
856 | ||
93f1d629 | 857 | if (PageHighMem(page)) { |
15653371 | 858 | if (len + offset > PAGE_SIZE) |
93f1d629 | 859 | len = PAGE_SIZE - offset; |
dd0f67f4 JK |
860 | |
861 | if (cache_is_vipt_nonaliasing()) { | |
39af22a7 | 862 | vaddr = kmap_atomic(page); |
7e5a69e8 | 863 | op(vaddr + offset, len, dir); |
39af22a7 | 864 | kunmap_atomic(vaddr); |
dd0f67f4 JK |
865 | } else { |
866 | vaddr = kmap_high_get(page); | |
867 | if (vaddr) { | |
868 | op(vaddr + offset, len, dir); | |
869 | kunmap_high(page); | |
870 | } | |
43377453 | 871 | } |
93f1d629 RK |
872 | } else { |
873 | vaddr = page_address(page) + offset; | |
a9c9147e | 874 | op(vaddr, len, dir); |
43377453 | 875 | } |
43377453 | 876 | offset = 0; |
15653371 | 877 | pfn++; |
43377453 NP |
878 | left -= len; |
879 | } while (left); | |
880 | } | |
4ea0d737 | 881 | |
51fde349 MS |
882 | /* |
883 | * Make an area consistent for devices. | |
884 | * Note: Drivers should NOT use this function directly, as it will break | |
885 | * platforms with CONFIG_DMABOUNCE. | |
886 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
887 | */ | |
888 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
889 | size_t size, enum dma_data_direction dir) |
890 | { | |
65af191a | 891 | unsigned long paddr; |
65af191a | 892 | |
a9c9147e | 893 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
894 | |
895 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
896 | if (dir == DMA_FROM_DEVICE) { |
897 | outer_inv_range(paddr, paddr + size); | |
898 | } else { | |
899 | outer_clean_range(paddr, paddr + size); | |
900 | } | |
901 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 902 | } |
4ea0d737 | 903 | |
51fde349 | 904 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
905 | size_t size, enum dma_data_direction dir) |
906 | { | |
2ffe2da3 RK |
907 | unsigned long paddr = page_to_phys(page) + off; |
908 | ||
909 | /* FIXME: non-speculating: not required */ | |
910 | /* don't bother invalidating if DMA to device */ | |
911 | if (dir != DMA_TO_DEVICE) | |
912 | outer_inv_range(paddr, paddr + size); | |
913 | ||
a9c9147e | 914 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
c0177800 CM |
915 | |
916 | /* | |
b2a234ed | 917 | * Mark the D-cache clean for these pages to avoid extra flushing. |
c0177800 | 918 | */ |
b2a234ed ML |
919 | if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) { |
920 | unsigned long pfn; | |
921 | size_t left = size; | |
922 | ||
923 | pfn = page_to_pfn(page) + off / PAGE_SIZE; | |
924 | off %= PAGE_SIZE; | |
925 | if (off) { | |
926 | pfn++; | |
927 | left -= PAGE_SIZE - off; | |
928 | } | |
929 | while (left >= PAGE_SIZE) { | |
930 | page = pfn_to_page(pfn++); | |
931 | set_bit(PG_dcache_clean, &page->flags); | |
932 | left -= PAGE_SIZE; | |
933 | } | |
934 | } | |
4ea0d737 | 935 | } |
43377453 | 936 | |
afd1a321 | 937 | /** |
2a550e73 | 938 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
939 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
940 | * @sg: list of buffers | |
941 | * @nents: number of buffers to map | |
942 | * @dir: DMA transfer direction | |
943 | * | |
944 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
945 | * This is the scatter-gather version of the dma_map_single interface. | |
946 | * Here the scatter gather list elements are each tagged with the | |
947 | * appropriate dma address and length. They are obtained via | |
948 | * sg_dma_{address,length}. | |
949 | * | |
950 | * Device ownership issues as mentioned for dma_map_single are the same | |
951 | * here. | |
952 | */ | |
2dc6a016 MS |
953 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
954 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 955 | { |
2a550e73 | 956 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 957 | struct scatterlist *s; |
01135d92 | 958 | int i, j; |
afd1a321 RK |
959 | |
960 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
961 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
962 | s->dma_length = s->length; | |
963 | #endif | |
2a550e73 MS |
964 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
965 | s->length, dir, attrs); | |
01135d92 RK |
966 | if (dma_mapping_error(dev, s->dma_address)) |
967 | goto bad_mapping; | |
afd1a321 | 968 | } |
afd1a321 | 969 | return nents; |
01135d92 RK |
970 | |
971 | bad_mapping: | |
972 | for_each_sg(sg, s, i, j) | |
2a550e73 | 973 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 974 | return 0; |
afd1a321 | 975 | } |
afd1a321 RK |
976 | |
977 | /** | |
2a550e73 | 978 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
979 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
980 | * @sg: list of buffers | |
0adfca6f | 981 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
982 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
983 | * | |
984 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
985 | * rules concerning calls here are the same as for dma_unmap_single(). | |
986 | */ | |
2dc6a016 MS |
987 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
988 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 989 | { |
2a550e73 | 990 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 991 | struct scatterlist *s; |
01135d92 | 992 | |
01135d92 | 993 | int i; |
24056f52 | 994 | |
01135d92 | 995 | for_each_sg(sg, s, nents, i) |
2a550e73 | 996 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 997 | } |
afd1a321 RK |
998 | |
999 | /** | |
2a550e73 | 1000 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
1001 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1002 | * @sg: list of buffers | |
1003 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1004 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1005 | */ | |
2dc6a016 | 1006 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1007 | int nents, enum dma_data_direction dir) |
1008 | { | |
2a550e73 | 1009 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1010 | struct scatterlist *s; |
1011 | int i; | |
1012 | ||
2a550e73 MS |
1013 | for_each_sg(sg, s, nents, i) |
1014 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
1015 | dir); | |
afd1a321 | 1016 | } |
afd1a321 RK |
1017 | |
1018 | /** | |
2a550e73 | 1019 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
1020 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1021 | * @sg: list of buffers | |
1022 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1023 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1024 | */ | |
2dc6a016 | 1025 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1026 | int nents, enum dma_data_direction dir) |
1027 | { | |
2a550e73 | 1028 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1029 | struct scatterlist *s; |
1030 | int i; | |
1031 | ||
2a550e73 MS |
1032 | for_each_sg(sg, s, nents, i) |
1033 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
1034 | dir); | |
afd1a321 | 1035 | } |
24056f52 | 1036 | |
022ae537 RK |
1037 | /* |
1038 | * Return whether the given device DMA address mask can be supported | |
1039 | * properly. For example, if your device can only drive the low 24-bits | |
1040 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
1041 | * to this function. | |
1042 | */ | |
1043 | int dma_supported(struct device *dev, u64 mask) | |
1044 | { | |
9f28cde0 | 1045 | return __dma_supported(dev, mask, false); |
022ae537 RK |
1046 | } |
1047 | EXPORT_SYMBOL(dma_supported); | |
1048 | ||
87b54e78 | 1049 | int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
1050 | { |
1051 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
1052 | return -EIO; | |
1053 | ||
022ae537 | 1054 | *dev->dma_mask = dma_mask; |
022ae537 RK |
1055 | |
1056 | return 0; | |
1057 | } | |
022ae537 | 1058 | |
24056f52 RK |
1059 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
1060 | ||
1061 | static int __init dma_debug_do_init(void) | |
1062 | { | |
1063 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
1064 | return 0; | |
1065 | } | |
1066 | fs_initcall(dma_debug_do_init); | |
4ce63fcd MS |
1067 | |
1068 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
1069 | ||
1070 | /* IOMMU */ | |
1071 | ||
4d852ef8 AH |
1072 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping); |
1073 | ||
4ce63fcd MS |
1074 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, |
1075 | size_t size) | |
1076 | { | |
1077 | unsigned int order = get_order(size); | |
1078 | unsigned int align = 0; | |
1079 | unsigned int count, start; | |
1080 | unsigned long flags; | |
4d852ef8 AH |
1081 | dma_addr_t iova; |
1082 | int i; | |
4ce63fcd | 1083 | |
60460abf SWK |
1084 | if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT) |
1085 | order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT; | |
1086 | ||
4ce63fcd MS |
1087 | count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) + |
1088 | (1 << mapping->order) - 1) >> mapping->order; | |
1089 | ||
1090 | if (order > mapping->order) | |
1091 | align = (1 << (order - mapping->order)) - 1; | |
1092 | ||
1093 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 AH |
1094 | for (i = 0; i < mapping->nr_bitmaps; i++) { |
1095 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1096 | mapping->bits, 0, count, align); | |
1097 | ||
1098 | if (start > mapping->bits) | |
1099 | continue; | |
1100 | ||
1101 | bitmap_set(mapping->bitmaps[i], start, count); | |
1102 | break; | |
4ce63fcd MS |
1103 | } |
1104 | ||
4d852ef8 AH |
1105 | /* |
1106 | * No unused range found. Try to extend the existing mapping | |
1107 | * and perform a second attempt to reserve an IO virtual | |
1108 | * address range of size bytes. | |
1109 | */ | |
1110 | if (i == mapping->nr_bitmaps) { | |
1111 | if (extend_iommu_mapping(mapping)) { | |
1112 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1113 | return DMA_ERROR_CODE; | |
1114 | } | |
1115 | ||
1116 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1117 | mapping->bits, 0, count, align); | |
1118 | ||
1119 | if (start > mapping->bits) { | |
1120 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1121 | return DMA_ERROR_CODE; | |
1122 | } | |
1123 | ||
1124 | bitmap_set(mapping->bitmaps[i], start, count); | |
1125 | } | |
4ce63fcd MS |
1126 | spin_unlock_irqrestore(&mapping->lock, flags); |
1127 | ||
4d852ef8 AH |
1128 | iova = mapping->base + (mapping->size * i); |
1129 | iova += start << (mapping->order + PAGE_SHIFT); | |
1130 | ||
1131 | return iova; | |
4ce63fcd MS |
1132 | } |
1133 | ||
1134 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
1135 | dma_addr_t addr, size_t size) | |
1136 | { | |
4d852ef8 | 1137 | unsigned int start, count; |
4ce63fcd | 1138 | unsigned long flags; |
4d852ef8 AH |
1139 | dma_addr_t bitmap_base; |
1140 | u32 bitmap_index; | |
1141 | ||
1142 | if (!size) | |
1143 | return; | |
1144 | ||
1145 | bitmap_index = (u32) (addr - mapping->base) / (u32) mapping->size; | |
1146 | BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions); | |
1147 | ||
1148 | bitmap_base = mapping->base + mapping->size * bitmap_index; | |
1149 | ||
1150 | start = (addr - bitmap_base) >> (mapping->order + PAGE_SHIFT); | |
1151 | ||
1152 | if (addr + size > bitmap_base + mapping->size) { | |
1153 | /* | |
1154 | * The address range to be freed reaches into the iova | |
1155 | * range of the next bitmap. This should not happen as | |
1156 | * we don't allow this in __alloc_iova (at the | |
1157 | * moment). | |
1158 | */ | |
1159 | BUG(); | |
1160 | } else | |
1161 | count = ((size >> PAGE_SHIFT) + | |
1162 | (1 << mapping->order) - 1) >> mapping->order; | |
4ce63fcd MS |
1163 | |
1164 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 | 1165 | bitmap_clear(mapping->bitmaps[bitmap_index], start, count); |
4ce63fcd MS |
1166 | spin_unlock_irqrestore(&mapping->lock, flags); |
1167 | } | |
1168 | ||
549a17e4 MS |
1169 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, |
1170 | gfp_t gfp, struct dma_attrs *attrs) | |
4ce63fcd MS |
1171 | { |
1172 | struct page **pages; | |
1173 | int count = size >> PAGE_SHIFT; | |
1174 | int array_size = count * sizeof(struct page *); | |
1175 | int i = 0; | |
1176 | ||
1177 | if (array_size <= PAGE_SIZE) | |
1178 | pages = kzalloc(array_size, gfp); | |
1179 | else | |
1180 | pages = vzalloc(array_size); | |
1181 | if (!pages) | |
1182 | return NULL; | |
1183 | ||
549a17e4 MS |
1184 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) |
1185 | { | |
1186 | unsigned long order = get_order(size); | |
1187 | struct page *page; | |
1188 | ||
1189 | page = dma_alloc_from_contiguous(dev, count, order); | |
1190 | if (!page) | |
1191 | goto error; | |
1192 | ||
1193 | __dma_clear_buffer(page, size); | |
1194 | ||
1195 | for (i = 0; i < count; i++) | |
1196 | pages[i] = page + i; | |
1197 | ||
1198 | return pages; | |
1199 | } | |
1200 | ||
f8669bef MS |
1201 | /* |
1202 | * IOMMU can map any pages, so himem can also be used here | |
1203 | */ | |
1204 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
1205 | ||
4ce63fcd | 1206 | while (count) { |
593f4735 | 1207 | int j, order = __fls(count); |
4ce63fcd | 1208 | |
f8669bef | 1209 | pages[i] = alloc_pages(gfp, order); |
4ce63fcd | 1210 | while (!pages[i] && order) |
f8669bef | 1211 | pages[i] = alloc_pages(gfp, --order); |
4ce63fcd MS |
1212 | if (!pages[i]) |
1213 | goto error; | |
1214 | ||
5a796eeb | 1215 | if (order) { |
4ce63fcd | 1216 | split_page(pages[i], order); |
5a796eeb HD |
1217 | j = 1 << order; |
1218 | while (--j) | |
1219 | pages[i + j] = pages[i] + j; | |
1220 | } | |
4ce63fcd MS |
1221 | |
1222 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
1223 | i += 1 << order; | |
1224 | count -= 1 << order; | |
1225 | } | |
1226 | ||
1227 | return pages; | |
1228 | error: | |
9fa8af91 | 1229 | while (i--) |
4ce63fcd MS |
1230 | if (pages[i]) |
1231 | __free_pages(pages[i], 0); | |
46c87852 | 1232 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1233 | kfree(pages); |
1234 | else | |
1235 | vfree(pages); | |
1236 | return NULL; | |
1237 | } | |
1238 | ||
549a17e4 MS |
1239 | static int __iommu_free_buffer(struct device *dev, struct page **pages, |
1240 | size_t size, struct dma_attrs *attrs) | |
4ce63fcd MS |
1241 | { |
1242 | int count = size >> PAGE_SHIFT; | |
1243 | int array_size = count * sizeof(struct page *); | |
1244 | int i; | |
549a17e4 MS |
1245 | |
1246 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) { | |
1247 | dma_release_from_contiguous(dev, pages[0], count); | |
1248 | } else { | |
1249 | for (i = 0; i < count; i++) | |
1250 | if (pages[i]) | |
1251 | __free_pages(pages[i], 0); | |
1252 | } | |
1253 | ||
46c87852 | 1254 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1255 | kfree(pages); |
1256 | else | |
1257 | vfree(pages); | |
1258 | return 0; | |
1259 | } | |
1260 | ||
1261 | /* | |
1262 | * Create a CPU mapping for a specified pages | |
1263 | */ | |
1264 | static void * | |
e9da6e99 MS |
1265 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1266 | const void *caller) | |
4ce63fcd | 1267 | { |
e9da6e99 MS |
1268 | unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1269 | struct vm_struct *area; | |
1270 | unsigned long p; | |
4ce63fcd | 1271 | |
e9da6e99 MS |
1272 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, |
1273 | caller); | |
1274 | if (!area) | |
4ce63fcd | 1275 | return NULL; |
4ce63fcd | 1276 | |
e9da6e99 MS |
1277 | area->pages = pages; |
1278 | area->nr_pages = nr_pages; | |
1279 | p = (unsigned long)area->addr; | |
4ce63fcd | 1280 | |
e9da6e99 MS |
1281 | for (i = 0; i < nr_pages; i++) { |
1282 | phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i])); | |
1283 | if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot)) | |
1284 | goto err; | |
1285 | p += PAGE_SIZE; | |
4ce63fcd | 1286 | } |
e9da6e99 MS |
1287 | return area->addr; |
1288 | err: | |
1289 | unmap_kernel_range((unsigned long)area->addr, size); | |
1290 | vunmap(area->addr); | |
4ce63fcd MS |
1291 | return NULL; |
1292 | } | |
1293 | ||
1294 | /* | |
1295 | * Create a mapping in device IO address space for specified pages | |
1296 | */ | |
1297 | static dma_addr_t | |
1298 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1299 | { | |
1300 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1301 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1302 | dma_addr_t dma_addr, iova; | |
1303 | int i, ret = DMA_ERROR_CODE; | |
1304 | ||
1305 | dma_addr = __alloc_iova(mapping, size); | |
1306 | if (dma_addr == DMA_ERROR_CODE) | |
1307 | return dma_addr; | |
1308 | ||
1309 | iova = dma_addr; | |
1310 | for (i = 0; i < count; ) { | |
1311 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; | |
1312 | phys_addr_t phys = page_to_phys(pages[i]); | |
1313 | unsigned int len, j; | |
1314 | ||
1315 | for (j = i + 1; j < count; j++, next_pfn++) | |
1316 | if (page_to_pfn(pages[j]) != next_pfn) | |
1317 | break; | |
1318 | ||
1319 | len = (j - i) << PAGE_SHIFT; | |
c9b24996 AH |
1320 | ret = iommu_map(mapping->domain, iova, phys, len, |
1321 | IOMMU_READ|IOMMU_WRITE); | |
4ce63fcd MS |
1322 | if (ret < 0) |
1323 | goto fail; | |
1324 | iova += len; | |
1325 | i = j; | |
1326 | } | |
1327 | return dma_addr; | |
1328 | fail: | |
1329 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1330 | __free_iova(mapping, dma_addr, size); | |
1331 | return DMA_ERROR_CODE; | |
1332 | } | |
1333 | ||
1334 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1335 | { | |
1336 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1337 | ||
1338 | /* | |
1339 | * add optional in-page offset from iova to size and align | |
1340 | * result to page size | |
1341 | */ | |
1342 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1343 | iova &= PAGE_MASK; | |
1344 | ||
1345 | iommu_unmap(mapping->domain, iova, size); | |
1346 | __free_iova(mapping, iova, size); | |
1347 | return 0; | |
1348 | } | |
1349 | ||
665bad7b HD |
1350 | static struct page **__atomic_get_pages(void *addr) |
1351 | { | |
1352 | struct dma_pool *pool = &atomic_pool; | |
1353 | struct page **pages = pool->pages; | |
1354 | int offs = (addr - pool->vaddr) >> PAGE_SHIFT; | |
1355 | ||
1356 | return pages + offs; | |
1357 | } | |
1358 | ||
955c757e | 1359 | static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) |
e9da6e99 MS |
1360 | { |
1361 | struct vm_struct *area; | |
1362 | ||
665bad7b HD |
1363 | if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) |
1364 | return __atomic_get_pages(cpu_addr); | |
1365 | ||
955c757e MS |
1366 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1367 | return cpu_addr; | |
1368 | ||
e9da6e99 MS |
1369 | area = find_vm_area(cpu_addr); |
1370 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1371 | return area->pages; | |
1372 | return NULL; | |
1373 | } | |
1374 | ||
479ed93a HD |
1375 | static void *__iommu_alloc_atomic(struct device *dev, size_t size, |
1376 | dma_addr_t *handle) | |
1377 | { | |
1378 | struct page *page; | |
1379 | void *addr; | |
1380 | ||
1381 | addr = __alloc_from_pool(size, &page); | |
1382 | if (!addr) | |
1383 | return NULL; | |
1384 | ||
1385 | *handle = __iommu_create_mapping(dev, &page, size); | |
1386 | if (*handle == DMA_ERROR_CODE) | |
1387 | goto err_mapping; | |
1388 | ||
1389 | return addr; | |
1390 | ||
1391 | err_mapping: | |
1392 | __free_from_pool(addr, size); | |
1393 | return NULL; | |
1394 | } | |
1395 | ||
d5898291 | 1396 | static void __iommu_free_atomic(struct device *dev, void *cpu_addr, |
479ed93a HD |
1397 | dma_addr_t handle, size_t size) |
1398 | { | |
1399 | __iommu_remove_mapping(dev, handle, size); | |
d5898291 | 1400 | __free_from_pool(cpu_addr, size); |
479ed93a HD |
1401 | } |
1402 | ||
4ce63fcd MS |
1403 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
1404 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1405 | { | |
71b55663 | 1406 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
4ce63fcd MS |
1407 | struct page **pages; |
1408 | void *addr = NULL; | |
1409 | ||
1410 | *handle = DMA_ERROR_CODE; | |
1411 | size = PAGE_ALIGN(size); | |
1412 | ||
10c8562f | 1413 | if (!(gfp & __GFP_WAIT)) |
479ed93a HD |
1414 | return __iommu_alloc_atomic(dev, size, handle); |
1415 | ||
5b91a98c RZ |
1416 | /* |
1417 | * Following is a work-around (a.k.a. hack) to prevent pages | |
1418 | * with __GFP_COMP being passed to split_page() which cannot | |
1419 | * handle them. The real problem is that this flag probably | |
1420 | * should be 0 on ARM as it is not supported on this | |
1421 | * platform; see CONFIG_HUGETLBFS. | |
1422 | */ | |
1423 | gfp &= ~(__GFP_COMP); | |
1424 | ||
549a17e4 | 1425 | pages = __iommu_alloc_buffer(dev, size, gfp, attrs); |
4ce63fcd MS |
1426 | if (!pages) |
1427 | return NULL; | |
1428 | ||
1429 | *handle = __iommu_create_mapping(dev, pages, size); | |
1430 | if (*handle == DMA_ERROR_CODE) | |
1431 | goto err_buffer; | |
1432 | ||
955c757e MS |
1433 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1434 | return pages; | |
1435 | ||
e9da6e99 MS |
1436 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1437 | __builtin_return_address(0)); | |
4ce63fcd MS |
1438 | if (!addr) |
1439 | goto err_mapping; | |
1440 | ||
1441 | return addr; | |
1442 | ||
1443 | err_mapping: | |
1444 | __iommu_remove_mapping(dev, *handle, size); | |
1445 | err_buffer: | |
549a17e4 | 1446 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1447 | return NULL; |
1448 | } | |
1449 | ||
1450 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1451 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1452 | struct dma_attrs *attrs) | |
1453 | { | |
e9da6e99 MS |
1454 | unsigned long uaddr = vma->vm_start; |
1455 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1456 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1457 | |
1458 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
4ce63fcd | 1459 | |
e9da6e99 MS |
1460 | if (!pages) |
1461 | return -ENXIO; | |
4ce63fcd | 1462 | |
e9da6e99 MS |
1463 | do { |
1464 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1465 | if (ret) { | |
1466 | pr_err("Remapping memory failed: %d\n", ret); | |
1467 | return ret; | |
1468 | } | |
1469 | uaddr += PAGE_SIZE; | |
1470 | usize -= PAGE_SIZE; | |
1471 | } while (usize > 0); | |
4ce63fcd | 1472 | |
4ce63fcd MS |
1473 | return 0; |
1474 | } | |
1475 | ||
1476 | /* | |
1477 | * free a page as defined by the above mapping. | |
1478 | * Must not be called with IRQs disabled. | |
1479 | */ | |
1480 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1481 | dma_addr_t handle, struct dma_attrs *attrs) | |
1482 | { | |
836bfa0d | 1483 | struct page **pages; |
4ce63fcd MS |
1484 | size = PAGE_ALIGN(size); |
1485 | ||
836bfa0d YC |
1486 | if (__in_atomic_pool(cpu_addr, size)) { |
1487 | __iommu_free_atomic(dev, cpu_addr, handle, size); | |
e9da6e99 | 1488 | return; |
4ce63fcd | 1489 | } |
e9da6e99 | 1490 | |
836bfa0d YC |
1491 | pages = __iommu_get_pages(cpu_addr, attrs); |
1492 | if (!pages) { | |
1493 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
479ed93a HD |
1494 | return; |
1495 | } | |
1496 | ||
955c757e MS |
1497 | if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { |
1498 | unmap_kernel_range((unsigned long)cpu_addr, size); | |
1499 | vunmap(cpu_addr); | |
1500 | } | |
e9da6e99 MS |
1501 | |
1502 | __iommu_remove_mapping(dev, handle, size); | |
549a17e4 | 1503 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1504 | } |
1505 | ||
dc2832e1 MS |
1506 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1507 | void *cpu_addr, dma_addr_t dma_addr, | |
1508 | size_t size, struct dma_attrs *attrs) | |
1509 | { | |
1510 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1511 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1512 | ||
1513 | if (!pages) | |
1514 | return -ENXIO; | |
1515 | ||
1516 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1517 | GFP_KERNEL); | |
4ce63fcd MS |
1518 | } |
1519 | ||
c9b24996 AH |
1520 | static int __dma_direction_to_prot(enum dma_data_direction dir) |
1521 | { | |
1522 | int prot; | |
1523 | ||
1524 | switch (dir) { | |
1525 | case DMA_BIDIRECTIONAL: | |
1526 | prot = IOMMU_READ | IOMMU_WRITE; | |
1527 | break; | |
1528 | case DMA_TO_DEVICE: | |
1529 | prot = IOMMU_READ; | |
1530 | break; | |
1531 | case DMA_FROM_DEVICE: | |
1532 | prot = IOMMU_WRITE; | |
1533 | break; | |
1534 | default: | |
1535 | prot = 0; | |
1536 | } | |
1537 | ||
1538 | return prot; | |
1539 | } | |
1540 | ||
4ce63fcd MS |
1541 | /* |
1542 | * Map a part of the scatter-gather list into contiguous io address space | |
1543 | */ | |
1544 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1545 | size_t size, dma_addr_t *handle, | |
0fa478df RH |
1546 | enum dma_data_direction dir, struct dma_attrs *attrs, |
1547 | bool is_coherent) | |
4ce63fcd MS |
1548 | { |
1549 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1550 | dma_addr_t iova, iova_base; | |
1551 | int ret = 0; | |
1552 | unsigned int count; | |
1553 | struct scatterlist *s; | |
c9b24996 | 1554 | int prot; |
4ce63fcd MS |
1555 | |
1556 | size = PAGE_ALIGN(size); | |
1557 | *handle = DMA_ERROR_CODE; | |
1558 | ||
1559 | iova_base = iova = __alloc_iova(mapping, size); | |
1560 | if (iova == DMA_ERROR_CODE) | |
1561 | return -ENOMEM; | |
1562 | ||
1563 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
1564 | phys_addr_t phys = page_to_phys(sg_page(s)); | |
1565 | unsigned int len = PAGE_ALIGN(s->offset + s->length); | |
1566 | ||
0fa478df RH |
1567 | if (!is_coherent && |
1568 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1569 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1570 | ||
c9b24996 AH |
1571 | prot = __dma_direction_to_prot(dir); |
1572 | ||
1573 | ret = iommu_map(mapping->domain, iova, phys, len, prot); | |
4ce63fcd MS |
1574 | if (ret < 0) |
1575 | goto fail; | |
1576 | count += len >> PAGE_SHIFT; | |
1577 | iova += len; | |
1578 | } | |
1579 | *handle = iova_base; | |
1580 | ||
1581 | return 0; | |
1582 | fail: | |
1583 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1584 | __free_iova(mapping, iova_base, size); | |
1585 | return ret; | |
1586 | } | |
1587 | ||
0fa478df RH |
1588 | static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
1589 | enum dma_data_direction dir, struct dma_attrs *attrs, | |
1590 | bool is_coherent) | |
4ce63fcd MS |
1591 | { |
1592 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1593 | int i, count = 0; | |
1594 | unsigned int offset = s->offset; | |
1595 | unsigned int size = s->offset + s->length; | |
1596 | unsigned int max = dma_get_max_seg_size(dev); | |
1597 | ||
1598 | for (i = 1; i < nents; i++) { | |
1599 | s = sg_next(s); | |
1600 | ||
1601 | s->dma_address = DMA_ERROR_CODE; | |
1602 | s->dma_length = 0; | |
1603 | ||
1604 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1605 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
0fa478df | 1606 | dir, attrs, is_coherent) < 0) |
4ce63fcd MS |
1607 | goto bad_mapping; |
1608 | ||
1609 | dma->dma_address += offset; | |
1610 | dma->dma_length = size - offset; | |
1611 | ||
1612 | size = offset = s->offset; | |
1613 | start = s; | |
1614 | dma = sg_next(dma); | |
1615 | count += 1; | |
1616 | } | |
1617 | size += s->length; | |
1618 | } | |
0fa478df RH |
1619 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs, |
1620 | is_coherent) < 0) | |
4ce63fcd MS |
1621 | goto bad_mapping; |
1622 | ||
1623 | dma->dma_address += offset; | |
1624 | dma->dma_length = size - offset; | |
1625 | ||
1626 | return count+1; | |
1627 | ||
1628 | bad_mapping: | |
1629 | for_each_sg(sg, s, count, i) | |
1630 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1631 | return 0; | |
1632 | } | |
1633 | ||
1634 | /** | |
0fa478df | 1635 | * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA |
4ce63fcd MS |
1636 | * @dev: valid struct device pointer |
1637 | * @sg: list of buffers | |
0fa478df RH |
1638 | * @nents: number of buffers to map |
1639 | * @dir: DMA transfer direction | |
4ce63fcd | 1640 | * |
0fa478df RH |
1641 | * Map a set of i/o coherent buffers described by scatterlist in streaming |
1642 | * mode for DMA. The scatter gather list elements are merged together (if | |
1643 | * possible) and tagged with the appropriate dma address and length. They are | |
1644 | * obtained via sg_dma_{address,length}. | |
4ce63fcd | 1645 | */ |
0fa478df RH |
1646 | int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg, |
1647 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1648 | { | |
1649 | return __iommu_map_sg(dev, sg, nents, dir, attrs, true); | |
1650 | } | |
1651 | ||
1652 | /** | |
1653 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1654 | * @dev: valid struct device pointer | |
1655 | * @sg: list of buffers | |
1656 | * @nents: number of buffers to map | |
1657 | * @dir: DMA transfer direction | |
1658 | * | |
1659 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1660 | * The scatter gather list elements are merged together (if possible) and | |
1661 | * tagged with the appropriate dma address and length. They are obtained via | |
1662 | * sg_dma_{address,length}. | |
1663 | */ | |
1664 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, | |
1665 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1666 | { | |
1667 | return __iommu_map_sg(dev, sg, nents, dir, attrs, false); | |
1668 | } | |
1669 | ||
1670 | static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1671 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs, | |
1672 | bool is_coherent) | |
4ce63fcd MS |
1673 | { |
1674 | struct scatterlist *s; | |
1675 | int i; | |
1676 | ||
1677 | for_each_sg(sg, s, nents, i) { | |
1678 | if (sg_dma_len(s)) | |
1679 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1680 | sg_dma_len(s)); | |
0fa478df | 1681 | if (!is_coherent && |
97ef952a | 1682 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1683 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1684 | s->length, dir); | |
1685 | } | |
1686 | } | |
1687 | ||
0fa478df RH |
1688 | /** |
1689 | * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1690 | * @dev: valid struct device pointer | |
1691 | * @sg: list of buffers | |
1692 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1693 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1694 | * | |
1695 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1696 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1697 | */ | |
1698 | void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1699 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1700 | { | |
1701 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, true); | |
1702 | } | |
1703 | ||
1704 | /** | |
1705 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1706 | * @dev: valid struct device pointer | |
1707 | * @sg: list of buffers | |
1708 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1709 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1710 | * | |
1711 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1712 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1713 | */ | |
1714 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1715 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1716 | { | |
1717 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, false); | |
1718 | } | |
1719 | ||
4ce63fcd MS |
1720 | /** |
1721 | * arm_iommu_sync_sg_for_cpu | |
1722 | * @dev: valid struct device pointer | |
1723 | * @sg: list of buffers | |
1724 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1725 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1726 | */ | |
1727 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1728 | int nents, enum dma_data_direction dir) | |
1729 | { | |
1730 | struct scatterlist *s; | |
1731 | int i; | |
1732 | ||
1733 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1734 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1735 | |
1736 | } | |
1737 | ||
1738 | /** | |
1739 | * arm_iommu_sync_sg_for_device | |
1740 | * @dev: valid struct device pointer | |
1741 | * @sg: list of buffers | |
1742 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1743 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1744 | */ | |
1745 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1746 | int nents, enum dma_data_direction dir) | |
1747 | { | |
1748 | struct scatterlist *s; | |
1749 | int i; | |
1750 | ||
1751 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1752 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1753 | } |
1754 | ||
1755 | ||
1756 | /** | |
0fa478df | 1757 | * arm_coherent_iommu_map_page |
4ce63fcd MS |
1758 | * @dev: valid struct device pointer |
1759 | * @page: page that buffer resides in | |
1760 | * @offset: offset into page for start of buffer | |
1761 | * @size: size of buffer to map | |
1762 | * @dir: DMA transfer direction | |
1763 | * | |
0fa478df | 1764 | * Coherent IOMMU aware version of arm_dma_map_page() |
4ce63fcd | 1765 | */ |
0fa478df | 1766 | static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page, |
4ce63fcd MS |
1767 | unsigned long offset, size_t size, enum dma_data_direction dir, |
1768 | struct dma_attrs *attrs) | |
1769 | { | |
1770 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1771 | dma_addr_t dma_addr; | |
13987d68 | 1772 | int ret, prot, len = PAGE_ALIGN(size + offset); |
4ce63fcd | 1773 | |
4ce63fcd MS |
1774 | dma_addr = __alloc_iova(mapping, len); |
1775 | if (dma_addr == DMA_ERROR_CODE) | |
1776 | return dma_addr; | |
1777 | ||
c9b24996 | 1778 | prot = __dma_direction_to_prot(dir); |
13987d68 WD |
1779 | |
1780 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot); | |
4ce63fcd MS |
1781 | if (ret < 0) |
1782 | goto fail; | |
1783 | ||
1784 | return dma_addr + offset; | |
1785 | fail: | |
1786 | __free_iova(mapping, dma_addr, len); | |
1787 | return DMA_ERROR_CODE; | |
1788 | } | |
1789 | ||
0fa478df RH |
1790 | /** |
1791 | * arm_iommu_map_page | |
1792 | * @dev: valid struct device pointer | |
1793 | * @page: page that buffer resides in | |
1794 | * @offset: offset into page for start of buffer | |
1795 | * @size: size of buffer to map | |
1796 | * @dir: DMA transfer direction | |
1797 | * | |
1798 | * IOMMU aware version of arm_dma_map_page() | |
1799 | */ | |
1800 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1801 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1802 | struct dma_attrs *attrs) | |
1803 | { | |
1804 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
1805 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1806 | ||
1807 | return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs); | |
1808 | } | |
1809 | ||
1810 | /** | |
1811 | * arm_coherent_iommu_unmap_page | |
1812 | * @dev: valid struct device pointer | |
1813 | * @handle: DMA address of buffer | |
1814 | * @size: size of buffer (same as passed to dma_map_page) | |
1815 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1816 | * | |
1817 | * Coherent IOMMU aware version of arm_dma_unmap_page() | |
1818 | */ | |
1819 | static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1820 | size_t size, enum dma_data_direction dir, | |
1821 | struct dma_attrs *attrs) | |
1822 | { | |
1823 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1824 | dma_addr_t iova = handle & PAGE_MASK; | |
0fa478df RH |
1825 | int offset = handle & ~PAGE_MASK; |
1826 | int len = PAGE_ALIGN(size + offset); | |
1827 | ||
1828 | if (!iova) | |
1829 | return; | |
1830 | ||
1831 | iommu_unmap(mapping->domain, iova, len); | |
1832 | __free_iova(mapping, iova, len); | |
1833 | } | |
1834 | ||
4ce63fcd MS |
1835 | /** |
1836 | * arm_iommu_unmap_page | |
1837 | * @dev: valid struct device pointer | |
1838 | * @handle: DMA address of buffer | |
1839 | * @size: size of buffer (same as passed to dma_map_page) | |
1840 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1841 | * | |
1842 | * IOMMU aware version of arm_dma_unmap_page() | |
1843 | */ | |
1844 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1845 | size_t size, enum dma_data_direction dir, | |
1846 | struct dma_attrs *attrs) | |
1847 | { | |
1848 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1849 | dma_addr_t iova = handle & PAGE_MASK; | |
1850 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1851 | int offset = handle & ~PAGE_MASK; | |
1852 | int len = PAGE_ALIGN(size + offset); | |
1853 | ||
1854 | if (!iova) | |
1855 | return; | |
1856 | ||
0fa478df | 1857 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1858 | __dma_page_dev_to_cpu(page, offset, size, dir); |
1859 | ||
1860 | iommu_unmap(mapping->domain, iova, len); | |
1861 | __free_iova(mapping, iova, len); | |
1862 | } | |
1863 | ||
1864 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1865 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1866 | { | |
1867 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1868 | dma_addr_t iova = handle & PAGE_MASK; | |
1869 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1870 | unsigned int offset = handle & ~PAGE_MASK; | |
1871 | ||
1872 | if (!iova) | |
1873 | return; | |
1874 | ||
0fa478df | 1875 | __dma_page_dev_to_cpu(page, offset, size, dir); |
4ce63fcd MS |
1876 | } |
1877 | ||
1878 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1879 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1880 | { | |
1881 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1882 | dma_addr_t iova = handle & PAGE_MASK; | |
1883 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1884 | unsigned int offset = handle & ~PAGE_MASK; | |
1885 | ||
1886 | if (!iova) | |
1887 | return; | |
1888 | ||
1889 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1890 | } | |
1891 | ||
1892 | struct dma_map_ops iommu_ops = { | |
1893 | .alloc = arm_iommu_alloc_attrs, | |
1894 | .free = arm_iommu_free_attrs, | |
1895 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 1896 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
1897 | |
1898 | .map_page = arm_iommu_map_page, | |
1899 | .unmap_page = arm_iommu_unmap_page, | |
1900 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1901 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1902 | ||
1903 | .map_sg = arm_iommu_map_sg, | |
1904 | .unmap_sg = arm_iommu_unmap_sg, | |
1905 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1906 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
d09e1333 HD |
1907 | |
1908 | .set_dma_mask = arm_dma_set_mask, | |
4ce63fcd MS |
1909 | }; |
1910 | ||
0fa478df RH |
1911 | struct dma_map_ops iommu_coherent_ops = { |
1912 | .alloc = arm_iommu_alloc_attrs, | |
1913 | .free = arm_iommu_free_attrs, | |
1914 | .mmap = arm_iommu_mmap_attrs, | |
1915 | .get_sgtable = arm_iommu_get_sgtable, | |
1916 | ||
1917 | .map_page = arm_coherent_iommu_map_page, | |
1918 | .unmap_page = arm_coherent_iommu_unmap_page, | |
1919 | ||
1920 | .map_sg = arm_coherent_iommu_map_sg, | |
1921 | .unmap_sg = arm_coherent_iommu_unmap_sg, | |
d09e1333 HD |
1922 | |
1923 | .set_dma_mask = arm_dma_set_mask, | |
0fa478df RH |
1924 | }; |
1925 | ||
4ce63fcd MS |
1926 | /** |
1927 | * arm_iommu_create_mapping | |
1928 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
1929 | * @base: start address of the valid IO address space | |
1930 | * @size: size of the valid IO address space | |
1931 | * @order: accuracy of the IO addresses allocations | |
1932 | * | |
1933 | * Creates a mapping structure which holds information about used/unused | |
1934 | * IO address ranges, which is required to perform memory allocation and | |
1935 | * mapping with IOMMU aware functions. | |
1936 | * | |
1937 | * The client device need to be attached to the mapping with | |
1938 | * arm_iommu_attach_device function. | |
1939 | */ | |
1940 | struct dma_iommu_mapping * | |
1941 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size, | |
1942 | int order) | |
1943 | { | |
1944 | unsigned int count = size >> (PAGE_SHIFT + order); | |
4ce63fcd | 1945 | struct dma_iommu_mapping *mapping; |
4d852ef8 | 1946 | int extensions = 0; |
4ce63fcd MS |
1947 | int err = -ENOMEM; |
1948 | ||
1949 | if (!count) | |
1950 | return ERR_PTR(-EINVAL); | |
1951 | ||
1952 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); | |
1953 | if (!mapping) | |
1954 | goto err; | |
1955 | ||
4d852ef8 AH |
1956 | mapping->bitmap_size = BITS_TO_LONGS(count) * sizeof(long); |
1957 | mapping->bitmaps = kzalloc((extensions + 1) * sizeof(unsigned long *), | |
1958 | GFP_KERNEL); | |
1959 | if (!mapping->bitmaps) | |
4ce63fcd MS |
1960 | goto err2; |
1961 | ||
4d852ef8 AH |
1962 | mapping->bitmaps[0] = kzalloc(mapping->bitmap_size, GFP_KERNEL); |
1963 | if (!mapping->bitmaps[0]) | |
1964 | goto err3; | |
1965 | ||
1966 | mapping->nr_bitmaps = 1; | |
1967 | mapping->extensions = extensions; | |
4ce63fcd | 1968 | mapping->base = base; |
4d852ef8 | 1969 | mapping->size = size; |
4ce63fcd | 1970 | mapping->order = order; |
4d852ef8 AH |
1971 | mapping->bits = BITS_PER_BYTE * mapping->bitmap_size; |
1972 | ||
4ce63fcd MS |
1973 | spin_lock_init(&mapping->lock); |
1974 | ||
1975 | mapping->domain = iommu_domain_alloc(bus); | |
1976 | if (!mapping->domain) | |
4d852ef8 | 1977 | goto err4; |
4ce63fcd MS |
1978 | |
1979 | kref_init(&mapping->kref); | |
1980 | return mapping; | |
4d852ef8 AH |
1981 | err4: |
1982 | kfree(mapping->bitmaps[0]); | |
4ce63fcd | 1983 | err3: |
4d852ef8 | 1984 | kfree(mapping->bitmaps); |
4ce63fcd MS |
1985 | err2: |
1986 | kfree(mapping); | |
1987 | err: | |
1988 | return ERR_PTR(err); | |
1989 | } | |
18177d12 | 1990 | EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); |
4ce63fcd MS |
1991 | |
1992 | static void release_iommu_mapping(struct kref *kref) | |
1993 | { | |
4d852ef8 | 1994 | int i; |
4ce63fcd MS |
1995 | struct dma_iommu_mapping *mapping = |
1996 | container_of(kref, struct dma_iommu_mapping, kref); | |
1997 | ||
1998 | iommu_domain_free(mapping->domain); | |
4d852ef8 AH |
1999 | for (i = 0; i < mapping->nr_bitmaps; i++) |
2000 | kfree(mapping->bitmaps[i]); | |
2001 | kfree(mapping->bitmaps); | |
4ce63fcd MS |
2002 | kfree(mapping); |
2003 | } | |
2004 | ||
4d852ef8 AH |
2005 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) |
2006 | { | |
2007 | int next_bitmap; | |
2008 | ||
2009 | if (mapping->nr_bitmaps > mapping->extensions) | |
2010 | return -EINVAL; | |
2011 | ||
2012 | next_bitmap = mapping->nr_bitmaps; | |
2013 | mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size, | |
2014 | GFP_ATOMIC); | |
2015 | if (!mapping->bitmaps[next_bitmap]) | |
2016 | return -ENOMEM; | |
2017 | ||
2018 | mapping->nr_bitmaps++; | |
2019 | ||
2020 | return 0; | |
2021 | } | |
2022 | ||
4ce63fcd MS |
2023 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) |
2024 | { | |
2025 | if (mapping) | |
2026 | kref_put(&mapping->kref, release_iommu_mapping); | |
2027 | } | |
18177d12 | 2028 | EXPORT_SYMBOL_GPL(arm_iommu_release_mapping); |
4ce63fcd MS |
2029 | |
2030 | /** | |
2031 | * arm_iommu_attach_device | |
2032 | * @dev: valid struct device pointer | |
2033 | * @mapping: io address space mapping structure (returned from | |
2034 | * arm_iommu_create_mapping) | |
2035 | * | |
2036 | * Attaches specified io address space mapping to the provided device, | |
2037 | * this replaces the dma operations (dma_map_ops pointer) with the | |
2038 | * IOMMU aware version. More than one client might be attached to | |
2039 | * the same io address space mapping. | |
2040 | */ | |
2041 | int arm_iommu_attach_device(struct device *dev, | |
2042 | struct dma_iommu_mapping *mapping) | |
2043 | { | |
2044 | int err; | |
2045 | ||
2046 | err = iommu_attach_device(mapping->domain, dev); | |
2047 | if (err) | |
2048 | return err; | |
2049 | ||
2050 | kref_get(&mapping->kref); | |
2051 | dev->archdata.mapping = mapping; | |
2052 | set_dma_ops(dev, &iommu_ops); | |
2053 | ||
75c59716 | 2054 | pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev)); |
4ce63fcd MS |
2055 | return 0; |
2056 | } | |
18177d12 | 2057 | EXPORT_SYMBOL_GPL(arm_iommu_attach_device); |
4ce63fcd | 2058 | |
6fe36758 HD |
2059 | /** |
2060 | * arm_iommu_detach_device | |
2061 | * @dev: valid struct device pointer | |
2062 | * | |
2063 | * Detaches the provided device from a previously attached map. | |
2064 | * This voids the dma operations (dma_map_ops pointer) | |
2065 | */ | |
2066 | void arm_iommu_detach_device(struct device *dev) | |
2067 | { | |
2068 | struct dma_iommu_mapping *mapping; | |
2069 | ||
2070 | mapping = to_dma_iommu_mapping(dev); | |
2071 | if (!mapping) { | |
2072 | dev_warn(dev, "Not attached\n"); | |
2073 | return; | |
2074 | } | |
2075 | ||
2076 | iommu_detach_device(mapping->domain, dev); | |
2077 | kref_put(&mapping->kref, release_iommu_mapping); | |
9e4b259d | 2078 | dev->archdata.mapping = NULL; |
6fe36758 HD |
2079 | set_dma_ops(dev, NULL); |
2080 | ||
2081 | pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev)); | |
2082 | } | |
18177d12 | 2083 | EXPORT_SYMBOL_GPL(arm_iommu_detach_device); |
6fe36758 | 2084 | |
4ce63fcd | 2085 | #endif |