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1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
1da177e4 LT |
15 | #include <linux/errno.h> |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
c7909509 | 20 | #include <linux/dma-contiguous.h> |
39af22a7 | 21 | #include <linux/highmem.h> |
c7909509 | 22 | #include <linux/memblock.h> |
99d1717d | 23 | #include <linux/slab.h> |
4ce63fcd | 24 | #include <linux/iommu.h> |
e9da6e99 | 25 | #include <linux/io.h> |
4ce63fcd | 26 | #include <linux/vmalloc.h> |
1da177e4 | 27 | |
23759dc6 | 28 | #include <asm/memory.h> |
43377453 | 29 | #include <asm/highmem.h> |
1da177e4 | 30 | #include <asm/cacheflush.h> |
1da177e4 | 31 | #include <asm/tlbflush.h> |
37134cd5 | 32 | #include <asm/sizes.h> |
99d1717d | 33 | #include <asm/mach/arch.h> |
4ce63fcd | 34 | #include <asm/dma-iommu.h> |
c7909509 MS |
35 | #include <asm/mach/map.h> |
36 | #include <asm/system_info.h> | |
37 | #include <asm/dma-contiguous.h> | |
37134cd5 | 38 | |
022ae537 RK |
39 | #include "mm.h" |
40 | ||
15237e1f MS |
41 | /* |
42 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
43 | * is either exclusively owned by the CPU (and therefore may be accessed | |
44 | * by it) or exclusively owned by the DMA device. These helper functions | |
45 | * represent the transitions between these two ownership states. | |
46 | * | |
47 | * Note, however, that on later ARMs, this notion does not work due to | |
48 | * speculative prefetches. We model our approach on the assumption that | |
49 | * the CPU does do speculative prefetches, which means we clean caches | |
50 | * before transfers and delay cache invalidation until transfer completion. | |
51 | * | |
15237e1f | 52 | */ |
51fde349 | 53 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 54 | size_t, enum dma_data_direction); |
51fde349 | 55 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
56 | size_t, enum dma_data_direction); |
57 | ||
2dc6a016 MS |
58 | /** |
59 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
60 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
61 | * @page: page that buffer resides in | |
62 | * @offset: offset into page for start of buffer | |
63 | * @size: size of buffer to map | |
64 | * @dir: DMA transfer direction | |
65 | * | |
66 | * Ensure that any data held in the cache is appropriately discarded | |
67 | * or written back. | |
68 | * | |
69 | * The device owns this memory once this call has completed. The CPU | |
70 | * can regain ownership by calling dma_unmap_page(). | |
71 | */ | |
51fde349 | 72 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
73 | unsigned long offset, size_t size, enum dma_data_direction dir, |
74 | struct dma_attrs *attrs) | |
75 | { | |
51fde349 MS |
76 | if (!arch_is_coherent()) |
77 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
78 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
79 | } |
80 | ||
81 | /** | |
82 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
83 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
84 | * @handle: DMA address of buffer | |
85 | * @size: size of buffer (same as passed to dma_map_page) | |
86 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
87 | * | |
88 | * Unmap a page streaming mode DMA translation. The handle and size | |
89 | * must match what was provided in the previous dma_map_page() call. | |
90 | * All other usages are undefined. | |
91 | * | |
92 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
93 | * whatever the device wrote there. | |
94 | */ | |
51fde349 | 95 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
96 | size_t size, enum dma_data_direction dir, |
97 | struct dma_attrs *attrs) | |
98 | { | |
51fde349 MS |
99 | if (!arch_is_coherent()) |
100 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), | |
101 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
102 | } |
103 | ||
51fde349 | 104 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
105 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
106 | { | |
107 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
108 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
109 | if (!arch_is_coherent()) |
110 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
2dc6a016 MS |
111 | } |
112 | ||
51fde349 | 113 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
114 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
115 | { | |
116 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
117 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
118 | if (!arch_is_coherent()) |
119 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
2dc6a016 MS |
120 | } |
121 | ||
122 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask); | |
123 | ||
124 | struct dma_map_ops arm_dma_ops = { | |
f99d6034 MS |
125 | .alloc = arm_dma_alloc, |
126 | .free = arm_dma_free, | |
127 | .mmap = arm_dma_mmap, | |
2dc6a016 MS |
128 | .map_page = arm_dma_map_page, |
129 | .unmap_page = arm_dma_unmap_page, | |
130 | .map_sg = arm_dma_map_sg, | |
131 | .unmap_sg = arm_dma_unmap_sg, | |
132 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
133 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
134 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
135 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
136 | .set_dma_mask = arm_dma_set_mask, | |
137 | }; | |
138 | EXPORT_SYMBOL(arm_dma_ops); | |
139 | ||
ab6494f0 CM |
140 | static u64 get_coherent_dma_mask(struct device *dev) |
141 | { | |
022ae537 | 142 | u64 mask = (u64)arm_dma_limit; |
ab6494f0 CM |
143 | |
144 | if (dev) { | |
145 | mask = dev->coherent_dma_mask; | |
146 | ||
147 | /* | |
148 | * Sanity check the DMA mask - it must be non-zero, and | |
149 | * must be able to be satisfied by a DMA allocation. | |
150 | */ | |
151 | if (mask == 0) { | |
152 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
153 | return 0; | |
154 | } | |
155 | ||
022ae537 | 156 | if ((~mask) & (u64)arm_dma_limit) { |
ab6494f0 CM |
157 | dev_warn(dev, "coherent DMA mask %#llx is smaller " |
158 | "than system GFP_DMA mask %#llx\n", | |
022ae537 | 159 | mask, (u64)arm_dma_limit); |
ab6494f0 CM |
160 | return 0; |
161 | } | |
162 | } | |
1da177e4 | 163 | |
ab6494f0 CM |
164 | return mask; |
165 | } | |
166 | ||
c7909509 MS |
167 | static void __dma_clear_buffer(struct page *page, size_t size) |
168 | { | |
169 | void *ptr; | |
170 | /* | |
171 | * Ensure that the allocated pages are zeroed, and that any data | |
172 | * lurking in the kernel direct-mapped region is invalidated. | |
173 | */ | |
174 | ptr = page_address(page); | |
4ce63fcd MS |
175 | if (ptr) { |
176 | memset(ptr, 0, size); | |
177 | dmac_flush_range(ptr, ptr + size); | |
178 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
179 | } | |
c7909509 MS |
180 | } |
181 | ||
7a9a32a9 RK |
182 | /* |
183 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
184 | * specified gfp mask. Note that 'size' must be page aligned. | |
185 | */ | |
186 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
187 | { | |
188 | unsigned long order = get_order(size); | |
189 | struct page *page, *p, *e; | |
7a9a32a9 RK |
190 | |
191 | page = alloc_pages(gfp, order); | |
192 | if (!page) | |
193 | return NULL; | |
194 | ||
195 | /* | |
196 | * Now split the huge page and free the excess pages | |
197 | */ | |
198 | split_page(page, order); | |
199 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
200 | __free_page(p); | |
201 | ||
c7909509 | 202 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
203 | |
204 | return page; | |
205 | } | |
206 | ||
207 | /* | |
208 | * Free a DMA buffer. 'size' must be page aligned. | |
209 | */ | |
210 | static void __dma_free_buffer(struct page *page, size_t size) | |
211 | { | |
212 | struct page *e = page + (size >> PAGE_SHIFT); | |
213 | ||
214 | while (page < e) { | |
215 | __free_page(page); | |
216 | page++; | |
217 | } | |
218 | } | |
219 | ||
ab6494f0 | 220 | #ifdef CONFIG_MMU |
e9da6e99 MS |
221 | #ifdef CONFIG_HUGETLB_PAGE |
222 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
223 | #endif | |
a5e9d38b | 224 | |
e9da6e99 MS |
225 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
226 | pgprot_t prot, struct page **ret_page); | |
99d1717d | 227 | |
e9da6e99 MS |
228 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
229 | pgprot_t prot, struct page **ret_page, | |
230 | const void *caller); | |
99d1717d | 231 | |
e9da6e99 MS |
232 | static void * |
233 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
234 | const void *caller) | |
99d1717d | 235 | { |
e9da6e99 MS |
236 | struct vm_struct *area; |
237 | unsigned long addr; | |
99d1717d | 238 | |
e9da6e99 MS |
239 | /* |
240 | * DMA allocation can be mapped to user space, so lets | |
241 | * set VM_USERMAP flags too. | |
242 | */ | |
243 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
244 | caller); | |
245 | if (!area) | |
246 | return NULL; | |
247 | addr = (unsigned long)area->addr; | |
248 | area->phys_addr = __pfn_to_phys(page_to_pfn(page)); | |
99d1717d | 249 | |
e9da6e99 MS |
250 | if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) { |
251 | vunmap((void *)addr); | |
252 | return NULL; | |
253 | } | |
254 | return (void *)addr; | |
99d1717d | 255 | } |
1da177e4 | 256 | |
e9da6e99 | 257 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 258 | { |
e9da6e99 MS |
259 | unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP; |
260 | struct vm_struct *area = find_vm_area(cpu_addr); | |
261 | if (!area || (area->flags & flags) != flags) { | |
262 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
263 | return; | |
99d1717d | 264 | } |
e9da6e99 MS |
265 | unmap_kernel_range((unsigned long)cpu_addr, size); |
266 | vunmap(cpu_addr); | |
88c58f3b | 267 | } |
88c58f3b | 268 | |
e9da6e99 MS |
269 | struct dma_pool { |
270 | size_t size; | |
271 | spinlock_t lock; | |
272 | unsigned long *bitmap; | |
273 | unsigned long nr_pages; | |
274 | void *vaddr; | |
275 | struct page *page; | |
c7909509 MS |
276 | }; |
277 | ||
e9da6e99 MS |
278 | static struct dma_pool atomic_pool = { |
279 | .size = SZ_256K, | |
280 | }; | |
c7909509 MS |
281 | |
282 | static int __init early_coherent_pool(char *p) | |
283 | { | |
e9da6e99 | 284 | atomic_pool.size = memparse(p, &p); |
c7909509 MS |
285 | return 0; |
286 | } | |
287 | early_param("coherent_pool", early_coherent_pool); | |
288 | ||
289 | /* | |
290 | * Initialise the coherent pool for atomic allocations. | |
291 | */ | |
e9da6e99 | 292 | static int __init atomic_pool_init(void) |
c7909509 | 293 | { |
e9da6e99 | 294 | struct dma_pool *pool = &atomic_pool; |
c7909509 | 295 | pgprot_t prot = pgprot_dmacoherent(pgprot_kernel); |
e9da6e99 MS |
296 | unsigned long nr_pages = pool->size >> PAGE_SHIFT; |
297 | unsigned long *bitmap; | |
c7909509 MS |
298 | struct page *page; |
299 | void *ptr; | |
e9da6e99 | 300 | int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long); |
c7909509 | 301 | |
e9da6e99 MS |
302 | bitmap = kzalloc(bitmap_size, GFP_KERNEL); |
303 | if (!bitmap) | |
304 | goto no_bitmap; | |
c7909509 | 305 | |
e9da6e99 MS |
306 | if (IS_ENABLED(CONFIG_CMA)) |
307 | ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page); | |
308 | else | |
309 | ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot, | |
310 | &page, NULL); | |
c7909509 | 311 | if (ptr) { |
e9da6e99 MS |
312 | spin_lock_init(&pool->lock); |
313 | pool->vaddr = ptr; | |
314 | pool->page = page; | |
315 | pool->bitmap = bitmap; | |
316 | pool->nr_pages = nr_pages; | |
317 | pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n", | |
318 | (unsigned)pool->size / 1024); | |
c7909509 MS |
319 | return 0; |
320 | } | |
e9da6e99 MS |
321 | kfree(bitmap); |
322 | no_bitmap: | |
323 | pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n", | |
324 | (unsigned)pool->size / 1024); | |
c7909509 MS |
325 | return -ENOMEM; |
326 | } | |
327 | /* | |
328 | * CMA is activated by core_initcall, so we must be called after it. | |
329 | */ | |
e9da6e99 | 330 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
331 | |
332 | struct dma_contig_early_reserve { | |
333 | phys_addr_t base; | |
334 | unsigned long size; | |
335 | }; | |
336 | ||
337 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
338 | ||
339 | static int dma_mmu_remap_num __initdata; | |
340 | ||
341 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
342 | { | |
343 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
344 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
345 | dma_mmu_remap_num++; | |
346 | } | |
347 | ||
348 | void __init dma_contiguous_remap(void) | |
349 | { | |
350 | int i; | |
351 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
352 | phys_addr_t start = dma_mmu_remap[i].base; | |
353 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
354 | struct map_desc map; | |
355 | unsigned long addr; | |
356 | ||
357 | if (end > arm_lowmem_limit) | |
358 | end = arm_lowmem_limit; | |
359 | if (start >= end) | |
360 | return; | |
361 | ||
362 | map.pfn = __phys_to_pfn(start); | |
363 | map.virtual = __phys_to_virt(start); | |
364 | map.length = end - start; | |
365 | map.type = MT_MEMORY_DMA_READY; | |
366 | ||
367 | /* | |
368 | * Clear previous low-memory mapping | |
369 | */ | |
370 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 371 | addr += PMD_SIZE) |
c7909509 MS |
372 | pmd_clear(pmd_off_k(addr)); |
373 | ||
374 | iotable_init(&map, 1); | |
375 | } | |
376 | } | |
377 | ||
c7909509 MS |
378 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
379 | void *data) | |
380 | { | |
381 | struct page *page = virt_to_page(addr); | |
382 | pgprot_t prot = *(pgprot_t *)data; | |
383 | ||
384 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
385 | return 0; | |
386 | } | |
387 | ||
388 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
389 | { | |
390 | unsigned long start = (unsigned long) page_address(page); | |
391 | unsigned end = start + size; | |
392 | ||
393 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
394 | dsb(); | |
395 | flush_tlb_kernel_range(start, end); | |
396 | } | |
397 | ||
398 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
399 | pgprot_t prot, struct page **ret_page, | |
400 | const void *caller) | |
401 | { | |
402 | struct page *page; | |
403 | void *ptr; | |
404 | page = __dma_alloc_buffer(dev, size, gfp); | |
405 | if (!page) | |
406 | return NULL; | |
407 | ||
408 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
409 | if (!ptr) { | |
410 | __dma_free_buffer(page, size); | |
411 | return NULL; | |
412 | } | |
413 | ||
414 | *ret_page = page; | |
415 | return ptr; | |
416 | } | |
417 | ||
e9da6e99 | 418 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 419 | { |
e9da6e99 MS |
420 | struct dma_pool *pool = &atomic_pool; |
421 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
422 | unsigned int pageno; | |
423 | unsigned long flags; | |
424 | void *ptr = NULL; | |
c7909509 MS |
425 | size_t align; |
426 | ||
e9da6e99 MS |
427 | if (!pool->vaddr) { |
428 | WARN(1, "coherent pool not initialised!\n"); | |
c7909509 MS |
429 | return NULL; |
430 | } | |
431 | ||
432 | /* | |
433 | * Align the region allocation - allocations from pool are rather | |
434 | * small, so align them to their order in pages, minimum is a page | |
435 | * size. This helps reduce fragmentation of the DMA space. | |
436 | */ | |
437 | align = PAGE_SIZE << get_order(size); | |
e9da6e99 MS |
438 | |
439 | spin_lock_irqsave(&pool->lock, flags); | |
440 | pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages, | |
441 | 0, count, (1 << align) - 1); | |
442 | if (pageno < pool->nr_pages) { | |
443 | bitmap_set(pool->bitmap, pageno, count); | |
444 | ptr = pool->vaddr + PAGE_SIZE * pageno; | |
445 | *ret_page = pool->page + pageno; | |
c7909509 | 446 | } |
e9da6e99 MS |
447 | spin_unlock_irqrestore(&pool->lock, flags); |
448 | ||
449 | return ptr; | |
c7909509 MS |
450 | } |
451 | ||
e9da6e99 | 452 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 453 | { |
e9da6e99 MS |
454 | struct dma_pool *pool = &atomic_pool; |
455 | unsigned long pageno, count; | |
456 | unsigned long flags; | |
c7909509 | 457 | |
e9da6e99 | 458 | if (start < pool->vaddr || start > pool->vaddr + pool->size) |
c7909509 MS |
459 | return 0; |
460 | ||
e9da6e99 MS |
461 | if (start + size > pool->vaddr + pool->size) { |
462 | WARN(1, "freeing wrong coherent size from pool\n"); | |
463 | return 0; | |
c7909509 MS |
464 | } |
465 | ||
e9da6e99 MS |
466 | pageno = (start - pool->vaddr) >> PAGE_SHIFT; |
467 | count = size >> PAGE_SHIFT; | |
468 | ||
469 | spin_lock_irqsave(&pool->lock, flags); | |
470 | bitmap_clear(pool->bitmap, pageno, count); | |
471 | spin_unlock_irqrestore(&pool->lock, flags); | |
472 | ||
c7909509 MS |
473 | return 1; |
474 | } | |
475 | ||
476 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
477 | pgprot_t prot, struct page **ret_page) | |
478 | { | |
479 | unsigned long order = get_order(size); | |
480 | size_t count = size >> PAGE_SHIFT; | |
481 | struct page *page; | |
482 | ||
483 | page = dma_alloc_from_contiguous(dev, count, order); | |
484 | if (!page) | |
485 | return NULL; | |
486 | ||
487 | __dma_clear_buffer(page, size); | |
488 | __dma_remap(page, size, prot); | |
489 | ||
490 | *ret_page = page; | |
491 | return page_address(page); | |
492 | } | |
493 | ||
494 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
495 | size_t size) | |
496 | { | |
497 | __dma_remap(page, size, pgprot_kernel); | |
498 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); | |
499 | } | |
500 | ||
f99d6034 MS |
501 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
502 | { | |
503 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
504 | pgprot_writecombine(prot) : | |
505 | pgprot_dmacoherent(prot); | |
506 | return prot; | |
507 | } | |
508 | ||
c7909509 MS |
509 | #define nommu() 0 |
510 | ||
ab6494f0 | 511 | #else /* !CONFIG_MMU */ |
695ae0af | 512 | |
c7909509 MS |
513 | #define nommu() 1 |
514 | ||
f99d6034 | 515 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
c7909509 | 516 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL |
e9da6e99 | 517 | #define __alloc_from_pool(size, ret_page) NULL |
c7909509 MS |
518 | #define __alloc_from_contiguous(dev, size, prot, ret) NULL |
519 | #define __free_from_pool(cpu_addr, size) 0 | |
520 | #define __free_from_contiguous(dev, page, size) do { } while (0) | |
521 | #define __dma_free_remap(cpu_addr, size) do { } while (0) | |
31ebf944 RK |
522 | |
523 | #endif /* CONFIG_MMU */ | |
524 | ||
c7909509 MS |
525 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
526 | struct page **ret_page) | |
ab6494f0 | 527 | { |
c7909509 MS |
528 | struct page *page; |
529 | page = __dma_alloc_buffer(dev, size, gfp); | |
530 | if (!page) | |
531 | return NULL; | |
532 | ||
533 | *ret_page = page; | |
534 | return page_address(page); | |
535 | } | |
536 | ||
537 | ||
538 | ||
539 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
540 | gfp_t gfp, pgprot_t prot, const void *caller) | |
541 | { | |
542 | u64 mask = get_coherent_dma_mask(dev); | |
04da5694 | 543 | struct page *page; |
31ebf944 | 544 | void *addr; |
ab6494f0 | 545 | |
c7909509 MS |
546 | #ifdef CONFIG_DMA_API_DEBUG |
547 | u64 limit = (mask + 1) & ~mask; | |
548 | if (limit && size >= limit) { | |
549 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
550 | size, mask); | |
551 | return NULL; | |
552 | } | |
553 | #endif | |
554 | ||
555 | if (!mask) | |
556 | return NULL; | |
557 | ||
558 | if (mask < 0xffffffffULL) | |
559 | gfp |= GFP_DMA; | |
560 | ||
ea2e7057 SB |
561 | /* |
562 | * Following is a work-around (a.k.a. hack) to prevent pages | |
563 | * with __GFP_COMP being passed to split_page() which cannot | |
564 | * handle them. The real problem is that this flag probably | |
565 | * should be 0 on ARM as it is not supported on this | |
566 | * platform; see CONFIG_HUGETLBFS. | |
567 | */ | |
568 | gfp &= ~(__GFP_COMP); | |
569 | ||
553ac788 | 570 | *handle = DMA_ERROR_CODE; |
04da5694 | 571 | size = PAGE_ALIGN(size); |
ab6494f0 | 572 | |
c7909509 MS |
573 | if (arch_is_coherent() || nommu()) |
574 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
e9da6e99 MS |
575 | else if (gfp & GFP_ATOMIC) |
576 | addr = __alloc_from_pool(size, &page); | |
f1ae98da | 577 | else if (!IS_ENABLED(CONFIG_CMA)) |
c7909509 | 578 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller); |
31ebf944 | 579 | else |
c7909509 | 580 | addr = __alloc_from_contiguous(dev, size, prot, &page); |
695ae0af | 581 | |
31ebf944 | 582 | if (addr) |
9eedd963 | 583 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
695ae0af | 584 | |
31ebf944 RK |
585 | return addr; |
586 | } | |
1da177e4 LT |
587 | |
588 | /* | |
589 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
590 | * virtual and bus address for that space. | |
591 | */ | |
f99d6034 MS |
592 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
593 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 594 | { |
f99d6034 | 595 | pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); |
1fe53268 DES |
596 | void *memory; |
597 | ||
598 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
599 | return memory; | |
600 | ||
f99d6034 | 601 | return __dma_alloc(dev, size, handle, gfp, prot, |
45cd5290 | 602 | __builtin_return_address(0)); |
1da177e4 | 603 | } |
1da177e4 LT |
604 | |
605 | /* | |
f99d6034 | 606 | * Create userspace mapping for the DMA-coherent memory. |
1da177e4 | 607 | */ |
f99d6034 MS |
608 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
609 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
610 | struct dma_attrs *attrs) | |
1da177e4 | 611 | { |
ab6494f0 CM |
612 | int ret = -ENXIO; |
613 | #ifdef CONFIG_MMU | |
50262a4b MS |
614 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
615 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 616 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
617 | unsigned long off = vma->vm_pgoff; |
618 | ||
f99d6034 MS |
619 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
620 | ||
47142f07 MS |
621 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
622 | return ret; | |
623 | ||
50262a4b MS |
624 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
625 | ret = remap_pfn_range(vma, vma->vm_start, | |
626 | pfn + off, | |
627 | vma->vm_end - vma->vm_start, | |
628 | vma->vm_page_prot); | |
629 | } | |
ab6494f0 | 630 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
631 | |
632 | return ret; | |
633 | } | |
634 | ||
1da177e4 | 635 | /* |
c7909509 | 636 | * Free a buffer as defined by the above mapping. |
1da177e4 | 637 | */ |
f99d6034 MS |
638 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
639 | dma_addr_t handle, struct dma_attrs *attrs) | |
1da177e4 | 640 | { |
c7909509 | 641 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
5edf71ae | 642 | |
1fe53268 DES |
643 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
644 | return; | |
645 | ||
3e82d012 RK |
646 | size = PAGE_ALIGN(size); |
647 | ||
c7909509 MS |
648 | if (arch_is_coherent() || nommu()) { |
649 | __dma_free_buffer(page, size); | |
f1ae98da | 650 | } else if (!IS_ENABLED(CONFIG_CMA)) { |
695ae0af | 651 | __dma_free_remap(cpu_addr, size); |
c7909509 MS |
652 | __dma_free_buffer(page, size); |
653 | } else { | |
654 | if (__free_from_pool(cpu_addr, size)) | |
655 | return; | |
656 | /* | |
657 | * Non-atomic allocations cannot be freed with IRQs disabled | |
658 | */ | |
659 | WARN_ON(irqs_disabled()); | |
660 | __free_from_contiguous(dev, page, size); | |
661 | } | |
1da177e4 | 662 | } |
afd1a321 | 663 | |
4ea0d737 | 664 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
665 | size_t size, enum dma_data_direction dir, |
666 | void (*op)(const void *, size_t, int)) | |
43377453 NP |
667 | { |
668 | /* | |
669 | * A single sg entry may refer to multiple physically contiguous | |
670 | * pages. But we still need to process highmem pages individually. | |
671 | * If highmem is not configured then the bulk of this loop gets | |
672 | * optimized out. | |
673 | */ | |
674 | size_t left = size; | |
675 | do { | |
676 | size_t len = left; | |
93f1d629 RK |
677 | void *vaddr; |
678 | ||
679 | if (PageHighMem(page)) { | |
680 | if (len + offset > PAGE_SIZE) { | |
681 | if (offset >= PAGE_SIZE) { | |
682 | page += offset / PAGE_SIZE; | |
683 | offset %= PAGE_SIZE; | |
684 | } | |
685 | len = PAGE_SIZE - offset; | |
686 | } | |
687 | vaddr = kmap_high_get(page); | |
688 | if (vaddr) { | |
689 | vaddr += offset; | |
a9c9147e | 690 | op(vaddr, len, dir); |
93f1d629 | 691 | kunmap_high(page); |
7e5a69e8 | 692 | } else if (cache_is_vipt()) { |
39af22a7 NP |
693 | /* unmapped pages might still be cached */ |
694 | vaddr = kmap_atomic(page); | |
7e5a69e8 | 695 | op(vaddr + offset, len, dir); |
39af22a7 | 696 | kunmap_atomic(vaddr); |
43377453 | 697 | } |
93f1d629 RK |
698 | } else { |
699 | vaddr = page_address(page) + offset; | |
a9c9147e | 700 | op(vaddr, len, dir); |
43377453 | 701 | } |
43377453 NP |
702 | offset = 0; |
703 | page++; | |
704 | left -= len; | |
705 | } while (left); | |
706 | } | |
4ea0d737 | 707 | |
51fde349 MS |
708 | /* |
709 | * Make an area consistent for devices. | |
710 | * Note: Drivers should NOT use this function directly, as it will break | |
711 | * platforms with CONFIG_DMABOUNCE. | |
712 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
713 | */ | |
714 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
715 | size_t size, enum dma_data_direction dir) |
716 | { | |
65af191a | 717 | unsigned long paddr; |
65af191a | 718 | |
a9c9147e | 719 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
720 | |
721 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
722 | if (dir == DMA_FROM_DEVICE) { |
723 | outer_inv_range(paddr, paddr + size); | |
724 | } else { | |
725 | outer_clean_range(paddr, paddr + size); | |
726 | } | |
727 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 728 | } |
4ea0d737 | 729 | |
51fde349 | 730 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
731 | size_t size, enum dma_data_direction dir) |
732 | { | |
2ffe2da3 RK |
733 | unsigned long paddr = page_to_phys(page) + off; |
734 | ||
735 | /* FIXME: non-speculating: not required */ | |
736 | /* don't bother invalidating if DMA to device */ | |
737 | if (dir != DMA_TO_DEVICE) | |
738 | outer_inv_range(paddr, paddr + size); | |
739 | ||
a9c9147e | 740 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
c0177800 CM |
741 | |
742 | /* | |
743 | * Mark the D-cache clean for this page to avoid extra flushing. | |
744 | */ | |
745 | if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE) | |
746 | set_bit(PG_dcache_clean, &page->flags); | |
4ea0d737 | 747 | } |
43377453 | 748 | |
afd1a321 | 749 | /** |
2a550e73 | 750 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
751 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
752 | * @sg: list of buffers | |
753 | * @nents: number of buffers to map | |
754 | * @dir: DMA transfer direction | |
755 | * | |
756 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
757 | * This is the scatter-gather version of the dma_map_single interface. | |
758 | * Here the scatter gather list elements are each tagged with the | |
759 | * appropriate dma address and length. They are obtained via | |
760 | * sg_dma_{address,length}. | |
761 | * | |
762 | * Device ownership issues as mentioned for dma_map_single are the same | |
763 | * here. | |
764 | */ | |
2dc6a016 MS |
765 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
766 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 767 | { |
2a550e73 | 768 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 769 | struct scatterlist *s; |
01135d92 | 770 | int i, j; |
afd1a321 RK |
771 | |
772 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
773 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
774 | s->dma_length = s->length; | |
775 | #endif | |
2a550e73 MS |
776 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
777 | s->length, dir, attrs); | |
01135d92 RK |
778 | if (dma_mapping_error(dev, s->dma_address)) |
779 | goto bad_mapping; | |
afd1a321 | 780 | } |
afd1a321 | 781 | return nents; |
01135d92 RK |
782 | |
783 | bad_mapping: | |
784 | for_each_sg(sg, s, i, j) | |
2a550e73 | 785 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 786 | return 0; |
afd1a321 | 787 | } |
afd1a321 RK |
788 | |
789 | /** | |
2a550e73 | 790 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
791 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
792 | * @sg: list of buffers | |
0adfca6f | 793 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
794 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
795 | * | |
796 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
797 | * rules concerning calls here are the same as for dma_unmap_single(). | |
798 | */ | |
2dc6a016 MS |
799 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
800 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 801 | { |
2a550e73 | 802 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 803 | struct scatterlist *s; |
01135d92 | 804 | |
01135d92 | 805 | int i; |
24056f52 | 806 | |
01135d92 | 807 | for_each_sg(sg, s, nents, i) |
2a550e73 | 808 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 809 | } |
afd1a321 RK |
810 | |
811 | /** | |
2a550e73 | 812 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
813 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
814 | * @sg: list of buffers | |
815 | * @nents: number of buffers to map (returned from dma_map_sg) | |
816 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
817 | */ | |
2dc6a016 | 818 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
819 | int nents, enum dma_data_direction dir) |
820 | { | |
2a550e73 | 821 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
822 | struct scatterlist *s; |
823 | int i; | |
824 | ||
2a550e73 MS |
825 | for_each_sg(sg, s, nents, i) |
826 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
827 | dir); | |
afd1a321 | 828 | } |
afd1a321 RK |
829 | |
830 | /** | |
2a550e73 | 831 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
832 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
833 | * @sg: list of buffers | |
834 | * @nents: number of buffers to map (returned from dma_map_sg) | |
835 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
836 | */ | |
2dc6a016 | 837 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
838 | int nents, enum dma_data_direction dir) |
839 | { | |
2a550e73 | 840 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
841 | struct scatterlist *s; |
842 | int i; | |
843 | ||
2a550e73 MS |
844 | for_each_sg(sg, s, nents, i) |
845 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
846 | dir); | |
afd1a321 | 847 | } |
24056f52 | 848 | |
022ae537 RK |
849 | /* |
850 | * Return whether the given device DMA address mask can be supported | |
851 | * properly. For example, if your device can only drive the low 24-bits | |
852 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
853 | * to this function. | |
854 | */ | |
855 | int dma_supported(struct device *dev, u64 mask) | |
856 | { | |
857 | if (mask < (u64)arm_dma_limit) | |
858 | return 0; | |
859 | return 1; | |
860 | } | |
861 | EXPORT_SYMBOL(dma_supported); | |
862 | ||
2dc6a016 | 863 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
864 | { |
865 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
866 | return -EIO; | |
867 | ||
022ae537 | 868 | *dev->dma_mask = dma_mask; |
022ae537 RK |
869 | |
870 | return 0; | |
871 | } | |
022ae537 | 872 | |
24056f52 RK |
873 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
874 | ||
875 | static int __init dma_debug_do_init(void) | |
876 | { | |
877 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
878 | return 0; | |
879 | } | |
880 | fs_initcall(dma_debug_do_init); | |
4ce63fcd MS |
881 | |
882 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
883 | ||
884 | /* IOMMU */ | |
885 | ||
886 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, | |
887 | size_t size) | |
888 | { | |
889 | unsigned int order = get_order(size); | |
890 | unsigned int align = 0; | |
891 | unsigned int count, start; | |
892 | unsigned long flags; | |
893 | ||
894 | count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) + | |
895 | (1 << mapping->order) - 1) >> mapping->order; | |
896 | ||
897 | if (order > mapping->order) | |
898 | align = (1 << (order - mapping->order)) - 1; | |
899 | ||
900 | spin_lock_irqsave(&mapping->lock, flags); | |
901 | start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0, | |
902 | count, align); | |
903 | if (start > mapping->bits) { | |
904 | spin_unlock_irqrestore(&mapping->lock, flags); | |
905 | return DMA_ERROR_CODE; | |
906 | } | |
907 | ||
908 | bitmap_set(mapping->bitmap, start, count); | |
909 | spin_unlock_irqrestore(&mapping->lock, flags); | |
910 | ||
911 | return mapping->base + (start << (mapping->order + PAGE_SHIFT)); | |
912 | } | |
913 | ||
914 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
915 | dma_addr_t addr, size_t size) | |
916 | { | |
917 | unsigned int start = (addr - mapping->base) >> | |
918 | (mapping->order + PAGE_SHIFT); | |
919 | unsigned int count = ((size >> PAGE_SHIFT) + | |
920 | (1 << mapping->order) - 1) >> mapping->order; | |
921 | unsigned long flags; | |
922 | ||
923 | spin_lock_irqsave(&mapping->lock, flags); | |
924 | bitmap_clear(mapping->bitmap, start, count); | |
925 | spin_unlock_irqrestore(&mapping->lock, flags); | |
926 | } | |
927 | ||
928 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
929 | { | |
930 | struct page **pages; | |
931 | int count = size >> PAGE_SHIFT; | |
932 | int array_size = count * sizeof(struct page *); | |
933 | int i = 0; | |
934 | ||
935 | if (array_size <= PAGE_SIZE) | |
936 | pages = kzalloc(array_size, gfp); | |
937 | else | |
938 | pages = vzalloc(array_size); | |
939 | if (!pages) | |
940 | return NULL; | |
941 | ||
942 | while (count) { | |
593f4735 | 943 | int j, order = __fls(count); |
4ce63fcd MS |
944 | |
945 | pages[i] = alloc_pages(gfp | __GFP_NOWARN, order); | |
946 | while (!pages[i] && order) | |
947 | pages[i] = alloc_pages(gfp | __GFP_NOWARN, --order); | |
948 | if (!pages[i]) | |
949 | goto error; | |
950 | ||
951 | if (order) | |
952 | split_page(pages[i], order); | |
953 | j = 1 << order; | |
954 | while (--j) | |
955 | pages[i + j] = pages[i] + j; | |
956 | ||
957 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
958 | i += 1 << order; | |
959 | count -= 1 << order; | |
960 | } | |
961 | ||
962 | return pages; | |
963 | error: | |
964 | while (--i) | |
965 | if (pages[i]) | |
966 | __free_pages(pages[i], 0); | |
46c87852 | 967 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
968 | kfree(pages); |
969 | else | |
970 | vfree(pages); | |
971 | return NULL; | |
972 | } | |
973 | ||
974 | static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t size) | |
975 | { | |
976 | int count = size >> PAGE_SHIFT; | |
977 | int array_size = count * sizeof(struct page *); | |
978 | int i; | |
979 | for (i = 0; i < count; i++) | |
980 | if (pages[i]) | |
981 | __free_pages(pages[i], 0); | |
46c87852 | 982 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
983 | kfree(pages); |
984 | else | |
985 | vfree(pages); | |
986 | return 0; | |
987 | } | |
988 | ||
989 | /* | |
990 | * Create a CPU mapping for a specified pages | |
991 | */ | |
992 | static void * | |
e9da6e99 MS |
993 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
994 | const void *caller) | |
4ce63fcd | 995 | { |
e9da6e99 MS |
996 | unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
997 | struct vm_struct *area; | |
998 | unsigned long p; | |
4ce63fcd | 999 | |
e9da6e99 MS |
1000 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, |
1001 | caller); | |
1002 | if (!area) | |
4ce63fcd | 1003 | return NULL; |
4ce63fcd | 1004 | |
e9da6e99 MS |
1005 | area->pages = pages; |
1006 | area->nr_pages = nr_pages; | |
1007 | p = (unsigned long)area->addr; | |
4ce63fcd | 1008 | |
e9da6e99 MS |
1009 | for (i = 0; i < nr_pages; i++) { |
1010 | phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i])); | |
1011 | if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot)) | |
1012 | goto err; | |
1013 | p += PAGE_SIZE; | |
4ce63fcd | 1014 | } |
e9da6e99 MS |
1015 | return area->addr; |
1016 | err: | |
1017 | unmap_kernel_range((unsigned long)area->addr, size); | |
1018 | vunmap(area->addr); | |
4ce63fcd MS |
1019 | return NULL; |
1020 | } | |
1021 | ||
1022 | /* | |
1023 | * Create a mapping in device IO address space for specified pages | |
1024 | */ | |
1025 | static dma_addr_t | |
1026 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1027 | { | |
1028 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1029 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1030 | dma_addr_t dma_addr, iova; | |
1031 | int i, ret = DMA_ERROR_CODE; | |
1032 | ||
1033 | dma_addr = __alloc_iova(mapping, size); | |
1034 | if (dma_addr == DMA_ERROR_CODE) | |
1035 | return dma_addr; | |
1036 | ||
1037 | iova = dma_addr; | |
1038 | for (i = 0; i < count; ) { | |
1039 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; | |
1040 | phys_addr_t phys = page_to_phys(pages[i]); | |
1041 | unsigned int len, j; | |
1042 | ||
1043 | for (j = i + 1; j < count; j++, next_pfn++) | |
1044 | if (page_to_pfn(pages[j]) != next_pfn) | |
1045 | break; | |
1046 | ||
1047 | len = (j - i) << PAGE_SHIFT; | |
1048 | ret = iommu_map(mapping->domain, iova, phys, len, 0); | |
1049 | if (ret < 0) | |
1050 | goto fail; | |
1051 | iova += len; | |
1052 | i = j; | |
1053 | } | |
1054 | return dma_addr; | |
1055 | fail: | |
1056 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1057 | __free_iova(mapping, dma_addr, size); | |
1058 | return DMA_ERROR_CODE; | |
1059 | } | |
1060 | ||
1061 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1062 | { | |
1063 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1064 | ||
1065 | /* | |
1066 | * add optional in-page offset from iova to size and align | |
1067 | * result to page size | |
1068 | */ | |
1069 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1070 | iova &= PAGE_MASK; | |
1071 | ||
1072 | iommu_unmap(mapping->domain, iova, size); | |
1073 | __free_iova(mapping, iova, size); | |
1074 | return 0; | |
1075 | } | |
1076 | ||
e9da6e99 MS |
1077 | static struct page **__iommu_get_pages(void *cpu_addr) |
1078 | { | |
1079 | struct vm_struct *area; | |
1080 | ||
1081 | area = find_vm_area(cpu_addr); | |
1082 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1083 | return area->pages; | |
1084 | return NULL; | |
1085 | } | |
1086 | ||
4ce63fcd MS |
1087 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
1088 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1089 | { | |
1090 | pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); | |
1091 | struct page **pages; | |
1092 | void *addr = NULL; | |
1093 | ||
1094 | *handle = DMA_ERROR_CODE; | |
1095 | size = PAGE_ALIGN(size); | |
1096 | ||
1097 | pages = __iommu_alloc_buffer(dev, size, gfp); | |
1098 | if (!pages) | |
1099 | return NULL; | |
1100 | ||
1101 | *handle = __iommu_create_mapping(dev, pages, size); | |
1102 | if (*handle == DMA_ERROR_CODE) | |
1103 | goto err_buffer; | |
1104 | ||
e9da6e99 MS |
1105 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1106 | __builtin_return_address(0)); | |
4ce63fcd MS |
1107 | if (!addr) |
1108 | goto err_mapping; | |
1109 | ||
1110 | return addr; | |
1111 | ||
1112 | err_mapping: | |
1113 | __iommu_remove_mapping(dev, *handle, size); | |
1114 | err_buffer: | |
1115 | __iommu_free_buffer(dev, pages, size); | |
1116 | return NULL; | |
1117 | } | |
1118 | ||
1119 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1120 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1121 | struct dma_attrs *attrs) | |
1122 | { | |
e9da6e99 MS |
1123 | unsigned long uaddr = vma->vm_start; |
1124 | unsigned long usize = vma->vm_end - vma->vm_start; | |
1125 | struct page **pages = __iommu_get_pages(cpu_addr); | |
4ce63fcd MS |
1126 | |
1127 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
4ce63fcd | 1128 | |
e9da6e99 MS |
1129 | if (!pages) |
1130 | return -ENXIO; | |
4ce63fcd | 1131 | |
e9da6e99 MS |
1132 | do { |
1133 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1134 | if (ret) { | |
1135 | pr_err("Remapping memory failed: %d\n", ret); | |
1136 | return ret; | |
1137 | } | |
1138 | uaddr += PAGE_SIZE; | |
1139 | usize -= PAGE_SIZE; | |
1140 | } while (usize > 0); | |
4ce63fcd | 1141 | |
4ce63fcd MS |
1142 | return 0; |
1143 | } | |
1144 | ||
1145 | /* | |
1146 | * free a page as defined by the above mapping. | |
1147 | * Must not be called with IRQs disabled. | |
1148 | */ | |
1149 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1150 | dma_addr_t handle, struct dma_attrs *attrs) | |
1151 | { | |
e9da6e99 | 1152 | struct page **pages = __iommu_get_pages(cpu_addr); |
4ce63fcd MS |
1153 | size = PAGE_ALIGN(size); |
1154 | ||
e9da6e99 MS |
1155 | if (!pages) { |
1156 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
1157 | return; | |
4ce63fcd | 1158 | } |
e9da6e99 MS |
1159 | |
1160 | unmap_kernel_range((unsigned long)cpu_addr, size); | |
1161 | vunmap(cpu_addr); | |
1162 | ||
1163 | __iommu_remove_mapping(dev, handle, size); | |
1164 | __iommu_free_buffer(dev, pages, size); | |
4ce63fcd MS |
1165 | } |
1166 | ||
1167 | /* | |
1168 | * Map a part of the scatter-gather list into contiguous io address space | |
1169 | */ | |
1170 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1171 | size_t size, dma_addr_t *handle, | |
1172 | enum dma_data_direction dir) | |
1173 | { | |
1174 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1175 | dma_addr_t iova, iova_base; | |
1176 | int ret = 0; | |
1177 | unsigned int count; | |
1178 | struct scatterlist *s; | |
1179 | ||
1180 | size = PAGE_ALIGN(size); | |
1181 | *handle = DMA_ERROR_CODE; | |
1182 | ||
1183 | iova_base = iova = __alloc_iova(mapping, size); | |
1184 | if (iova == DMA_ERROR_CODE) | |
1185 | return -ENOMEM; | |
1186 | ||
1187 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
1188 | phys_addr_t phys = page_to_phys(sg_page(s)); | |
1189 | unsigned int len = PAGE_ALIGN(s->offset + s->length); | |
1190 | ||
1191 | if (!arch_is_coherent()) | |
1192 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); | |
1193 | ||
1194 | ret = iommu_map(mapping->domain, iova, phys, len, 0); | |
1195 | if (ret < 0) | |
1196 | goto fail; | |
1197 | count += len >> PAGE_SHIFT; | |
1198 | iova += len; | |
1199 | } | |
1200 | *handle = iova_base; | |
1201 | ||
1202 | return 0; | |
1203 | fail: | |
1204 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1205 | __free_iova(mapping, iova_base, size); | |
1206 | return ret; | |
1207 | } | |
1208 | ||
1209 | /** | |
1210 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1211 | * @dev: valid struct device pointer | |
1212 | * @sg: list of buffers | |
1213 | * @nents: number of buffers to map | |
1214 | * @dir: DMA transfer direction | |
1215 | * | |
1216 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1217 | * The scatter gather list elements are merged together (if possible) and | |
1218 | * tagged with the appropriate dma address and length. They are obtained via | |
1219 | * sg_dma_{address,length}. | |
1220 | */ | |
1221 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1222 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1223 | { | |
1224 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1225 | int i, count = 0; | |
1226 | unsigned int offset = s->offset; | |
1227 | unsigned int size = s->offset + s->length; | |
1228 | unsigned int max = dma_get_max_seg_size(dev); | |
1229 | ||
1230 | for (i = 1; i < nents; i++) { | |
1231 | s = sg_next(s); | |
1232 | ||
1233 | s->dma_address = DMA_ERROR_CODE; | |
1234 | s->dma_length = 0; | |
1235 | ||
1236 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1237 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
1238 | dir) < 0) | |
1239 | goto bad_mapping; | |
1240 | ||
1241 | dma->dma_address += offset; | |
1242 | dma->dma_length = size - offset; | |
1243 | ||
1244 | size = offset = s->offset; | |
1245 | start = s; | |
1246 | dma = sg_next(dma); | |
1247 | count += 1; | |
1248 | } | |
1249 | size += s->length; | |
1250 | } | |
1251 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir) < 0) | |
1252 | goto bad_mapping; | |
1253 | ||
1254 | dma->dma_address += offset; | |
1255 | dma->dma_length = size - offset; | |
1256 | ||
1257 | return count+1; | |
1258 | ||
1259 | bad_mapping: | |
1260 | for_each_sg(sg, s, count, i) | |
1261 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1262 | return 0; | |
1263 | } | |
1264 | ||
1265 | /** | |
1266 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1267 | * @dev: valid struct device pointer | |
1268 | * @sg: list of buffers | |
1269 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1270 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1271 | * | |
1272 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1273 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1274 | */ | |
1275 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1276 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1277 | { | |
1278 | struct scatterlist *s; | |
1279 | int i; | |
1280 | ||
1281 | for_each_sg(sg, s, nents, i) { | |
1282 | if (sg_dma_len(s)) | |
1283 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1284 | sg_dma_len(s)); | |
1285 | if (!arch_is_coherent()) | |
1286 | __dma_page_dev_to_cpu(sg_page(s), s->offset, | |
1287 | s->length, dir); | |
1288 | } | |
1289 | } | |
1290 | ||
1291 | /** | |
1292 | * arm_iommu_sync_sg_for_cpu | |
1293 | * @dev: valid struct device pointer | |
1294 | * @sg: list of buffers | |
1295 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1296 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1297 | */ | |
1298 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1299 | int nents, enum dma_data_direction dir) | |
1300 | { | |
1301 | struct scatterlist *s; | |
1302 | int i; | |
1303 | ||
1304 | for_each_sg(sg, s, nents, i) | |
1305 | if (!arch_is_coherent()) | |
1306 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); | |
1307 | ||
1308 | } | |
1309 | ||
1310 | /** | |
1311 | * arm_iommu_sync_sg_for_device | |
1312 | * @dev: valid struct device pointer | |
1313 | * @sg: list of buffers | |
1314 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1315 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1316 | */ | |
1317 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1318 | int nents, enum dma_data_direction dir) | |
1319 | { | |
1320 | struct scatterlist *s; | |
1321 | int i; | |
1322 | ||
1323 | for_each_sg(sg, s, nents, i) | |
1324 | if (!arch_is_coherent()) | |
1325 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); | |
1326 | } | |
1327 | ||
1328 | ||
1329 | /** | |
1330 | * arm_iommu_map_page | |
1331 | * @dev: valid struct device pointer | |
1332 | * @page: page that buffer resides in | |
1333 | * @offset: offset into page for start of buffer | |
1334 | * @size: size of buffer to map | |
1335 | * @dir: DMA transfer direction | |
1336 | * | |
1337 | * IOMMU aware version of arm_dma_map_page() | |
1338 | */ | |
1339 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1340 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1341 | struct dma_attrs *attrs) | |
1342 | { | |
1343 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1344 | dma_addr_t dma_addr; | |
1345 | int ret, len = PAGE_ALIGN(size + offset); | |
1346 | ||
1347 | if (!arch_is_coherent()) | |
1348 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1349 | ||
1350 | dma_addr = __alloc_iova(mapping, len); | |
1351 | if (dma_addr == DMA_ERROR_CODE) | |
1352 | return dma_addr; | |
1353 | ||
1354 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0); | |
1355 | if (ret < 0) | |
1356 | goto fail; | |
1357 | ||
1358 | return dma_addr + offset; | |
1359 | fail: | |
1360 | __free_iova(mapping, dma_addr, len); | |
1361 | return DMA_ERROR_CODE; | |
1362 | } | |
1363 | ||
1364 | /** | |
1365 | * arm_iommu_unmap_page | |
1366 | * @dev: valid struct device pointer | |
1367 | * @handle: DMA address of buffer | |
1368 | * @size: size of buffer (same as passed to dma_map_page) | |
1369 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1370 | * | |
1371 | * IOMMU aware version of arm_dma_unmap_page() | |
1372 | */ | |
1373 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1374 | size_t size, enum dma_data_direction dir, | |
1375 | struct dma_attrs *attrs) | |
1376 | { | |
1377 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1378 | dma_addr_t iova = handle & PAGE_MASK; | |
1379 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1380 | int offset = handle & ~PAGE_MASK; | |
1381 | int len = PAGE_ALIGN(size + offset); | |
1382 | ||
1383 | if (!iova) | |
1384 | return; | |
1385 | ||
1386 | if (!arch_is_coherent()) | |
1387 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
1388 | ||
1389 | iommu_unmap(mapping->domain, iova, len); | |
1390 | __free_iova(mapping, iova, len); | |
1391 | } | |
1392 | ||
1393 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1394 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1395 | { | |
1396 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1397 | dma_addr_t iova = handle & PAGE_MASK; | |
1398 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1399 | unsigned int offset = handle & ~PAGE_MASK; | |
1400 | ||
1401 | if (!iova) | |
1402 | return; | |
1403 | ||
1404 | if (!arch_is_coherent()) | |
1405 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
1406 | } | |
1407 | ||
1408 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1409 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1410 | { | |
1411 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1412 | dma_addr_t iova = handle & PAGE_MASK; | |
1413 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1414 | unsigned int offset = handle & ~PAGE_MASK; | |
1415 | ||
1416 | if (!iova) | |
1417 | return; | |
1418 | ||
1419 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1420 | } | |
1421 | ||
1422 | struct dma_map_ops iommu_ops = { | |
1423 | .alloc = arm_iommu_alloc_attrs, | |
1424 | .free = arm_iommu_free_attrs, | |
1425 | .mmap = arm_iommu_mmap_attrs, | |
1426 | ||
1427 | .map_page = arm_iommu_map_page, | |
1428 | .unmap_page = arm_iommu_unmap_page, | |
1429 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1430 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1431 | ||
1432 | .map_sg = arm_iommu_map_sg, | |
1433 | .unmap_sg = arm_iommu_unmap_sg, | |
1434 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1435 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
1436 | }; | |
1437 | ||
1438 | /** | |
1439 | * arm_iommu_create_mapping | |
1440 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
1441 | * @base: start address of the valid IO address space | |
1442 | * @size: size of the valid IO address space | |
1443 | * @order: accuracy of the IO addresses allocations | |
1444 | * | |
1445 | * Creates a mapping structure which holds information about used/unused | |
1446 | * IO address ranges, which is required to perform memory allocation and | |
1447 | * mapping with IOMMU aware functions. | |
1448 | * | |
1449 | * The client device need to be attached to the mapping with | |
1450 | * arm_iommu_attach_device function. | |
1451 | */ | |
1452 | struct dma_iommu_mapping * | |
1453 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size, | |
1454 | int order) | |
1455 | { | |
1456 | unsigned int count = size >> (PAGE_SHIFT + order); | |
1457 | unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long); | |
1458 | struct dma_iommu_mapping *mapping; | |
1459 | int err = -ENOMEM; | |
1460 | ||
1461 | if (!count) | |
1462 | return ERR_PTR(-EINVAL); | |
1463 | ||
1464 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); | |
1465 | if (!mapping) | |
1466 | goto err; | |
1467 | ||
1468 | mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL); | |
1469 | if (!mapping->bitmap) | |
1470 | goto err2; | |
1471 | ||
1472 | mapping->base = base; | |
1473 | mapping->bits = BITS_PER_BYTE * bitmap_size; | |
1474 | mapping->order = order; | |
1475 | spin_lock_init(&mapping->lock); | |
1476 | ||
1477 | mapping->domain = iommu_domain_alloc(bus); | |
1478 | if (!mapping->domain) | |
1479 | goto err3; | |
1480 | ||
1481 | kref_init(&mapping->kref); | |
1482 | return mapping; | |
1483 | err3: | |
1484 | kfree(mapping->bitmap); | |
1485 | err2: | |
1486 | kfree(mapping); | |
1487 | err: | |
1488 | return ERR_PTR(err); | |
1489 | } | |
1490 | ||
1491 | static void release_iommu_mapping(struct kref *kref) | |
1492 | { | |
1493 | struct dma_iommu_mapping *mapping = | |
1494 | container_of(kref, struct dma_iommu_mapping, kref); | |
1495 | ||
1496 | iommu_domain_free(mapping->domain); | |
1497 | kfree(mapping->bitmap); | |
1498 | kfree(mapping); | |
1499 | } | |
1500 | ||
1501 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) | |
1502 | { | |
1503 | if (mapping) | |
1504 | kref_put(&mapping->kref, release_iommu_mapping); | |
1505 | } | |
1506 | ||
1507 | /** | |
1508 | * arm_iommu_attach_device | |
1509 | * @dev: valid struct device pointer | |
1510 | * @mapping: io address space mapping structure (returned from | |
1511 | * arm_iommu_create_mapping) | |
1512 | * | |
1513 | * Attaches specified io address space mapping to the provided device, | |
1514 | * this replaces the dma operations (dma_map_ops pointer) with the | |
1515 | * IOMMU aware version. More than one client might be attached to | |
1516 | * the same io address space mapping. | |
1517 | */ | |
1518 | int arm_iommu_attach_device(struct device *dev, | |
1519 | struct dma_iommu_mapping *mapping) | |
1520 | { | |
1521 | int err; | |
1522 | ||
1523 | err = iommu_attach_device(mapping->domain, dev); | |
1524 | if (err) | |
1525 | return err; | |
1526 | ||
1527 | kref_get(&mapping->kref); | |
1528 | dev->archdata.mapping = mapping; | |
1529 | set_dma_ops(dev, &iommu_ops); | |
1530 | ||
1531 | pr_info("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
1532 | return 0; | |
1533 | } | |
1534 | ||
1535 | #endif |