]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
11a5aa32 | 12 | #include <linux/bootmem.h> |
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/mm.h> | |
5a0e3ad6 | 15 | #include <linux/gfp.h> |
1da177e4 LT |
16 | #include <linux/errno.h> |
17 | #include <linux/list.h> | |
18 | #include <linux/init.h> | |
19 | #include <linux/device.h> | |
20 | #include <linux/dma-mapping.h> | |
c7909509 | 21 | #include <linux/dma-contiguous.h> |
39af22a7 | 22 | #include <linux/highmem.h> |
c7909509 | 23 | #include <linux/memblock.h> |
99d1717d | 24 | #include <linux/slab.h> |
4ce63fcd | 25 | #include <linux/iommu.h> |
e9da6e99 | 26 | #include <linux/io.h> |
4ce63fcd | 27 | #include <linux/vmalloc.h> |
158e8bfe | 28 | #include <linux/sizes.h> |
a254129e | 29 | #include <linux/cma.h> |
1da177e4 | 30 | |
23759dc6 | 31 | #include <asm/memory.h> |
43377453 | 32 | #include <asm/highmem.h> |
1da177e4 | 33 | #include <asm/cacheflush.h> |
1da177e4 | 34 | #include <asm/tlbflush.h> |
99d1717d | 35 | #include <asm/mach/arch.h> |
4ce63fcd | 36 | #include <asm/dma-iommu.h> |
c7909509 MS |
37 | #include <asm/mach/map.h> |
38 | #include <asm/system_info.h> | |
39 | #include <asm/dma-contiguous.h> | |
37134cd5 | 40 | |
022ae537 RK |
41 | #include "mm.h" |
42 | ||
15237e1f MS |
43 | /* |
44 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
45 | * is either exclusively owned by the CPU (and therefore may be accessed | |
46 | * by it) or exclusively owned by the DMA device. These helper functions | |
47 | * represent the transitions between these two ownership states. | |
48 | * | |
49 | * Note, however, that on later ARMs, this notion does not work due to | |
50 | * speculative prefetches. We model our approach on the assumption that | |
51 | * the CPU does do speculative prefetches, which means we clean caches | |
52 | * before transfers and delay cache invalidation until transfer completion. | |
53 | * | |
15237e1f | 54 | */ |
51fde349 | 55 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 56 | size_t, enum dma_data_direction); |
51fde349 | 57 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
58 | size_t, enum dma_data_direction); |
59 | ||
2dc6a016 MS |
60 | /** |
61 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
62 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
63 | * @page: page that buffer resides in | |
64 | * @offset: offset into page for start of buffer | |
65 | * @size: size of buffer to map | |
66 | * @dir: DMA transfer direction | |
67 | * | |
68 | * Ensure that any data held in the cache is appropriately discarded | |
69 | * or written back. | |
70 | * | |
71 | * The device owns this memory once this call has completed. The CPU | |
72 | * can regain ownership by calling dma_unmap_page(). | |
73 | */ | |
51fde349 | 74 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
75 | unsigned long offset, size_t size, enum dma_data_direction dir, |
76 | struct dma_attrs *attrs) | |
77 | { | |
dd37e940 | 78 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
79 | __dma_page_cpu_to_dev(page, offset, size, dir); |
80 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
81 | } |
82 | ||
dd37e940 RH |
83 | static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page, |
84 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
85 | struct dma_attrs *attrs) | |
86 | { | |
87 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
88 | } | |
89 | ||
2dc6a016 MS |
90 | /** |
91 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
92 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
93 | * @handle: DMA address of buffer | |
94 | * @size: size of buffer (same as passed to dma_map_page) | |
95 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
96 | * | |
97 | * Unmap a page streaming mode DMA translation. The handle and size | |
98 | * must match what was provided in the previous dma_map_page() call. | |
99 | * All other usages are undefined. | |
100 | * | |
101 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
102 | * whatever the device wrote there. | |
103 | */ | |
51fde349 | 104 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
105 | size_t size, enum dma_data_direction dir, |
106 | struct dma_attrs *attrs) | |
107 | { | |
dd37e940 | 108 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
109 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
110 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
111 | } |
112 | ||
51fde349 | 113 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
114 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
115 | { | |
116 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
117 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 118 | __dma_page_dev_to_cpu(page, offset, size, dir); |
2dc6a016 MS |
119 | } |
120 | ||
51fde349 | 121 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
122 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
123 | { | |
124 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
125 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 126 | __dma_page_cpu_to_dev(page, offset, size, dir); |
2dc6a016 MS |
127 | } |
128 | ||
2dc6a016 | 129 | struct dma_map_ops arm_dma_ops = { |
f99d6034 MS |
130 | .alloc = arm_dma_alloc, |
131 | .free = arm_dma_free, | |
132 | .mmap = arm_dma_mmap, | |
dc2832e1 | 133 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
134 | .map_page = arm_dma_map_page, |
135 | .unmap_page = arm_dma_unmap_page, | |
136 | .map_sg = arm_dma_map_sg, | |
137 | .unmap_sg = arm_dma_unmap_sg, | |
138 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
139 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
140 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
141 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
142 | .set_dma_mask = arm_dma_set_mask, | |
143 | }; | |
144 | EXPORT_SYMBOL(arm_dma_ops); | |
145 | ||
dd37e940 RH |
146 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, |
147 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs); | |
148 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
149 | dma_addr_t handle, struct dma_attrs *attrs); | |
150 | ||
151 | struct dma_map_ops arm_coherent_dma_ops = { | |
152 | .alloc = arm_coherent_dma_alloc, | |
153 | .free = arm_coherent_dma_free, | |
154 | .mmap = arm_dma_mmap, | |
155 | .get_sgtable = arm_dma_get_sgtable, | |
156 | .map_page = arm_coherent_dma_map_page, | |
157 | .map_sg = arm_dma_map_sg, | |
158 | .set_dma_mask = arm_dma_set_mask, | |
159 | }; | |
160 | EXPORT_SYMBOL(arm_coherent_dma_ops); | |
161 | ||
9f28cde0 RK |
162 | static int __dma_supported(struct device *dev, u64 mask, bool warn) |
163 | { | |
164 | unsigned long max_dma_pfn; | |
165 | ||
166 | /* | |
167 | * If the mask allows for more memory than we can address, | |
168 | * and we actually have that much memory, then we must | |
169 | * indicate that DMA to this device is not supported. | |
170 | */ | |
171 | if (sizeof(mask) != sizeof(dma_addr_t) && | |
172 | mask > (dma_addr_t)~0 && | |
173 | dma_to_pfn(dev, ~0) < max_pfn) { | |
174 | if (warn) { | |
175 | dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", | |
176 | mask); | |
177 | dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n"); | |
178 | } | |
179 | return 0; | |
180 | } | |
181 | ||
182 | max_dma_pfn = min(max_pfn, arm_dma_pfn_limit); | |
183 | ||
184 | /* | |
185 | * Translate the device's DMA mask to a PFN limit. This | |
186 | * PFN number includes the page which we can DMA to. | |
187 | */ | |
188 | if (dma_to_pfn(dev, mask) < max_dma_pfn) { | |
189 | if (warn) | |
190 | dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", | |
191 | mask, | |
192 | dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, | |
193 | max_dma_pfn + 1); | |
194 | return 0; | |
195 | } | |
196 | ||
197 | return 1; | |
198 | } | |
199 | ||
ab6494f0 CM |
200 | static u64 get_coherent_dma_mask(struct device *dev) |
201 | { | |
4dcfa600 | 202 | u64 mask = (u64)DMA_BIT_MASK(32); |
ab6494f0 CM |
203 | |
204 | if (dev) { | |
205 | mask = dev->coherent_dma_mask; | |
206 | ||
207 | /* | |
208 | * Sanity check the DMA mask - it must be non-zero, and | |
209 | * must be able to be satisfied by a DMA allocation. | |
210 | */ | |
211 | if (mask == 0) { | |
212 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
213 | return 0; | |
214 | } | |
215 | ||
9f28cde0 | 216 | if (!__dma_supported(dev, mask, true)) |
ab6494f0 | 217 | return 0; |
ab6494f0 | 218 | } |
1da177e4 | 219 | |
ab6494f0 CM |
220 | return mask; |
221 | } | |
222 | ||
c7909509 MS |
223 | static void __dma_clear_buffer(struct page *page, size_t size) |
224 | { | |
c7909509 MS |
225 | /* |
226 | * Ensure that the allocated pages are zeroed, and that any data | |
227 | * lurking in the kernel direct-mapped region is invalidated. | |
228 | */ | |
9848e48f MS |
229 | if (PageHighMem(page)) { |
230 | phys_addr_t base = __pfn_to_phys(page_to_pfn(page)); | |
231 | phys_addr_t end = base + size; | |
232 | while (size > 0) { | |
233 | void *ptr = kmap_atomic(page); | |
234 | memset(ptr, 0, PAGE_SIZE); | |
235 | dmac_flush_range(ptr, ptr + PAGE_SIZE); | |
236 | kunmap_atomic(ptr); | |
237 | page++; | |
238 | size -= PAGE_SIZE; | |
239 | } | |
240 | outer_flush_range(base, end); | |
241 | } else { | |
242 | void *ptr = page_address(page); | |
4ce63fcd MS |
243 | memset(ptr, 0, size); |
244 | dmac_flush_range(ptr, ptr + size); | |
245 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
246 | } | |
c7909509 MS |
247 | } |
248 | ||
7a9a32a9 RK |
249 | /* |
250 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
251 | * specified gfp mask. Note that 'size' must be page aligned. | |
252 | */ | |
253 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
254 | { | |
255 | unsigned long order = get_order(size); | |
256 | struct page *page, *p, *e; | |
7a9a32a9 RK |
257 | |
258 | page = alloc_pages(gfp, order); | |
259 | if (!page) | |
260 | return NULL; | |
261 | ||
262 | /* | |
263 | * Now split the huge page and free the excess pages | |
264 | */ | |
265 | split_page(page, order); | |
266 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
267 | __free_page(p); | |
268 | ||
c7909509 | 269 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
270 | |
271 | return page; | |
272 | } | |
273 | ||
274 | /* | |
275 | * Free a DMA buffer. 'size' must be page aligned. | |
276 | */ | |
277 | static void __dma_free_buffer(struct page *page, size_t size) | |
278 | { | |
279 | struct page *e = page + (size >> PAGE_SHIFT); | |
280 | ||
281 | while (page < e) { | |
282 | __free_page(page); | |
283 | page++; | |
284 | } | |
285 | } | |
286 | ||
ab6494f0 | 287 | #ifdef CONFIG_MMU |
a5e9d38b | 288 | |
e9da6e99 | 289 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
9848e48f MS |
290 | pgprot_t prot, struct page **ret_page, |
291 | const void *caller); | |
99d1717d | 292 | |
e9da6e99 MS |
293 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
294 | pgprot_t prot, struct page **ret_page, | |
295 | const void *caller); | |
99d1717d | 296 | |
e9da6e99 MS |
297 | static void * |
298 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
299 | const void *caller) | |
99d1717d | 300 | { |
e9da6e99 MS |
301 | /* |
302 | * DMA allocation can be mapped to user space, so lets | |
303 | * set VM_USERMAP flags too. | |
304 | */ | |
513510dd LA |
305 | return dma_common_contiguous_remap(page, size, |
306 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
307 | prot, caller); | |
99d1717d | 308 | } |
1da177e4 | 309 | |
e9da6e99 | 310 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 311 | { |
513510dd LA |
312 | dma_common_free_remap(cpu_addr, size, |
313 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
88c58f3b | 314 | } |
88c58f3b | 315 | |
6e5267aa MS |
316 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
317 | ||
e9da6e99 MS |
318 | struct dma_pool { |
319 | size_t size; | |
320 | spinlock_t lock; | |
321 | unsigned long *bitmap; | |
322 | unsigned long nr_pages; | |
323 | void *vaddr; | |
6b3fe472 | 324 | struct page **pages; |
c7909509 MS |
325 | }; |
326 | ||
e9da6e99 | 327 | static struct dma_pool atomic_pool = { |
6e5267aa | 328 | .size = DEFAULT_DMA_COHERENT_POOL_SIZE, |
e9da6e99 | 329 | }; |
c7909509 MS |
330 | |
331 | static int __init early_coherent_pool(char *p) | |
332 | { | |
e9da6e99 | 333 | atomic_pool.size = memparse(p, &p); |
c7909509 MS |
334 | return 0; |
335 | } | |
336 | early_param("coherent_pool", early_coherent_pool); | |
337 | ||
6e5267aa MS |
338 | void __init init_dma_coherent_pool_size(unsigned long size) |
339 | { | |
340 | /* | |
341 | * Catch any attempt to set the pool size too late. | |
342 | */ | |
343 | BUG_ON(atomic_pool.vaddr); | |
344 | ||
345 | /* | |
346 | * Set architecture specific coherent pool size only if | |
347 | * it has not been changed by kernel command line parameter. | |
348 | */ | |
349 | if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE) | |
350 | atomic_pool.size = size; | |
351 | } | |
352 | ||
c7909509 MS |
353 | /* |
354 | * Initialise the coherent pool for atomic allocations. | |
355 | */ | |
e9da6e99 | 356 | static int __init atomic_pool_init(void) |
c7909509 | 357 | { |
e9da6e99 | 358 | struct dma_pool *pool = &atomic_pool; |
71b55663 | 359 | pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); |
9d1400cf | 360 | gfp_t gfp = GFP_KERNEL | GFP_DMA; |
e9da6e99 MS |
361 | unsigned long nr_pages = pool->size >> PAGE_SHIFT; |
362 | unsigned long *bitmap; | |
c7909509 | 363 | struct page *page; |
6b3fe472 | 364 | struct page **pages; |
c7909509 | 365 | void *ptr; |
e9da6e99 | 366 | int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long); |
c7909509 | 367 | |
e9da6e99 MS |
368 | bitmap = kzalloc(bitmap_size, GFP_KERNEL); |
369 | if (!bitmap) | |
370 | goto no_bitmap; | |
c7909509 | 371 | |
6b3fe472 HD |
372 | pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL); |
373 | if (!pages) | |
374 | goto no_pages; | |
375 | ||
e464ef16 | 376 | if (dev_get_cma_area(NULL)) |
9848e48f MS |
377 | ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page, |
378 | atomic_pool_init); | |
e9da6e99 | 379 | else |
9d1400cf MS |
380 | ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page, |
381 | atomic_pool_init); | |
c7909509 | 382 | if (ptr) { |
6b3fe472 HD |
383 | int i; |
384 | ||
385 | for (i = 0; i < nr_pages; i++) | |
386 | pages[i] = page + i; | |
387 | ||
e9da6e99 MS |
388 | spin_lock_init(&pool->lock); |
389 | pool->vaddr = ptr; | |
6b3fe472 | 390 | pool->pages = pages; |
e9da6e99 MS |
391 | pool->bitmap = bitmap; |
392 | pool->nr_pages = nr_pages; | |
393 | pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n", | |
394 | (unsigned)pool->size / 1024); | |
c7909509 MS |
395 | return 0; |
396 | } | |
ec10665c SK |
397 | |
398 | kfree(pages); | |
6b3fe472 | 399 | no_pages: |
e9da6e99 MS |
400 | kfree(bitmap); |
401 | no_bitmap: | |
402 | pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n", | |
403 | (unsigned)pool->size / 1024); | |
c7909509 MS |
404 | return -ENOMEM; |
405 | } | |
406 | /* | |
407 | * CMA is activated by core_initcall, so we must be called after it. | |
408 | */ | |
e9da6e99 | 409 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
410 | |
411 | struct dma_contig_early_reserve { | |
412 | phys_addr_t base; | |
413 | unsigned long size; | |
414 | }; | |
415 | ||
416 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
417 | ||
418 | static int dma_mmu_remap_num __initdata; | |
419 | ||
420 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
421 | { | |
422 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
423 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
424 | dma_mmu_remap_num++; | |
425 | } | |
426 | ||
427 | void __init dma_contiguous_remap(void) | |
428 | { | |
429 | int i; | |
430 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
431 | phys_addr_t start = dma_mmu_remap[i].base; | |
432 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
433 | struct map_desc map; | |
434 | unsigned long addr; | |
435 | ||
436 | if (end > arm_lowmem_limit) | |
437 | end = arm_lowmem_limit; | |
438 | if (start >= end) | |
39f78e70 | 439 | continue; |
c7909509 MS |
440 | |
441 | map.pfn = __phys_to_pfn(start); | |
442 | map.virtual = __phys_to_virt(start); | |
443 | map.length = end - start; | |
444 | map.type = MT_MEMORY_DMA_READY; | |
445 | ||
446 | /* | |
6b076991 RK |
447 | * Clear previous low-memory mapping to ensure that the |
448 | * TLB does not see any conflicting entries, then flush | |
449 | * the TLB of the old entries before creating new mappings. | |
450 | * | |
451 | * This ensures that any speculatively loaded TLB entries | |
452 | * (even though they may be rare) can not cause any problems, | |
453 | * and ensures that this code is architecturally compliant. | |
c7909509 MS |
454 | */ |
455 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 456 | addr += PMD_SIZE) |
c7909509 MS |
457 | pmd_clear(pmd_off_k(addr)); |
458 | ||
6b076991 RK |
459 | flush_tlb_kernel_range(__phys_to_virt(start), |
460 | __phys_to_virt(end)); | |
461 | ||
c7909509 MS |
462 | iotable_init(&map, 1); |
463 | } | |
464 | } | |
465 | ||
c7909509 MS |
466 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
467 | void *data) | |
468 | { | |
469 | struct page *page = virt_to_page(addr); | |
470 | pgprot_t prot = *(pgprot_t *)data; | |
471 | ||
472 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
473 | return 0; | |
474 | } | |
475 | ||
476 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
477 | { | |
478 | unsigned long start = (unsigned long) page_address(page); | |
479 | unsigned end = start + size; | |
480 | ||
481 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
c7909509 MS |
482 | flush_tlb_kernel_range(start, end); |
483 | } | |
484 | ||
485 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
486 | pgprot_t prot, struct page **ret_page, | |
487 | const void *caller) | |
488 | { | |
489 | struct page *page; | |
490 | void *ptr; | |
491 | page = __dma_alloc_buffer(dev, size, gfp); | |
492 | if (!page) | |
493 | return NULL; | |
494 | ||
495 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
496 | if (!ptr) { | |
497 | __dma_free_buffer(page, size); | |
498 | return NULL; | |
499 | } | |
500 | ||
501 | *ret_page = page; | |
502 | return ptr; | |
503 | } | |
504 | ||
e9da6e99 | 505 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 506 | { |
e9da6e99 MS |
507 | struct dma_pool *pool = &atomic_pool; |
508 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
509 | unsigned int pageno; | |
510 | unsigned long flags; | |
511 | void *ptr = NULL; | |
e4ea6918 | 512 | unsigned long align_mask; |
c7909509 | 513 | |
e9da6e99 MS |
514 | if (!pool->vaddr) { |
515 | WARN(1, "coherent pool not initialised!\n"); | |
c7909509 MS |
516 | return NULL; |
517 | } | |
518 | ||
519 | /* | |
520 | * Align the region allocation - allocations from pool are rather | |
521 | * small, so align them to their order in pages, minimum is a page | |
522 | * size. This helps reduce fragmentation of the DMA space. | |
523 | */ | |
e4ea6918 | 524 | align_mask = (1 << get_order(size)) - 1; |
e9da6e99 MS |
525 | |
526 | spin_lock_irqsave(&pool->lock, flags); | |
527 | pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages, | |
e4ea6918 | 528 | 0, count, align_mask); |
e9da6e99 MS |
529 | if (pageno < pool->nr_pages) { |
530 | bitmap_set(pool->bitmap, pageno, count); | |
531 | ptr = pool->vaddr + PAGE_SIZE * pageno; | |
6b3fe472 | 532 | *ret_page = pool->pages[pageno]; |
fb71285f MS |
533 | } else { |
534 | pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n" | |
535 | "Please increase it with coherent_pool= kernel parameter!\n", | |
536 | (unsigned)pool->size / 1024); | |
c7909509 | 537 | } |
e9da6e99 MS |
538 | spin_unlock_irqrestore(&pool->lock, flags); |
539 | ||
540 | return ptr; | |
c7909509 MS |
541 | } |
542 | ||
21d0a759 HD |
543 | static bool __in_atomic_pool(void *start, size_t size) |
544 | { | |
545 | struct dma_pool *pool = &atomic_pool; | |
546 | void *end = start + size; | |
547 | void *pool_start = pool->vaddr; | |
548 | void *pool_end = pool->vaddr + pool->size; | |
549 | ||
f3d87524 | 550 | if (start < pool_start || start >= pool_end) |
21d0a759 HD |
551 | return false; |
552 | ||
553 | if (end <= pool_end) | |
554 | return true; | |
555 | ||
556 | WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n", | |
557 | start, end - 1, pool_start, pool_end - 1); | |
558 | ||
559 | return false; | |
560 | } | |
561 | ||
e9da6e99 | 562 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 563 | { |
e9da6e99 MS |
564 | struct dma_pool *pool = &atomic_pool; |
565 | unsigned long pageno, count; | |
566 | unsigned long flags; | |
c7909509 | 567 | |
21d0a759 | 568 | if (!__in_atomic_pool(start, size)) |
c7909509 MS |
569 | return 0; |
570 | ||
e9da6e99 MS |
571 | pageno = (start - pool->vaddr) >> PAGE_SHIFT; |
572 | count = size >> PAGE_SHIFT; | |
573 | ||
574 | spin_lock_irqsave(&pool->lock, flags); | |
575 | bitmap_clear(pool->bitmap, pageno, count); | |
576 | spin_unlock_irqrestore(&pool->lock, flags); | |
577 | ||
c7909509 MS |
578 | return 1; |
579 | } | |
580 | ||
581 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
9848e48f MS |
582 | pgprot_t prot, struct page **ret_page, |
583 | const void *caller) | |
c7909509 MS |
584 | { |
585 | unsigned long order = get_order(size); | |
586 | size_t count = size >> PAGE_SHIFT; | |
587 | struct page *page; | |
9848e48f | 588 | void *ptr; |
c7909509 MS |
589 | |
590 | page = dma_alloc_from_contiguous(dev, count, order); | |
591 | if (!page) | |
592 | return NULL; | |
593 | ||
594 | __dma_clear_buffer(page, size); | |
c7909509 | 595 | |
9848e48f MS |
596 | if (PageHighMem(page)) { |
597 | ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller); | |
598 | if (!ptr) { | |
599 | dma_release_from_contiguous(dev, page, count); | |
600 | return NULL; | |
601 | } | |
602 | } else { | |
603 | __dma_remap(page, size, prot); | |
604 | ptr = page_address(page); | |
605 | } | |
c7909509 | 606 | *ret_page = page; |
9848e48f | 607 | return ptr; |
c7909509 MS |
608 | } |
609 | ||
610 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
9848e48f | 611 | void *cpu_addr, size_t size) |
c7909509 | 612 | { |
9848e48f MS |
613 | if (PageHighMem(page)) |
614 | __dma_free_remap(cpu_addr, size); | |
615 | else | |
71b55663 | 616 | __dma_remap(page, size, PAGE_KERNEL); |
c7909509 MS |
617 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); |
618 | } | |
619 | ||
f99d6034 MS |
620 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
621 | { | |
622 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
623 | pgprot_writecombine(prot) : | |
624 | pgprot_dmacoherent(prot); | |
625 | return prot; | |
626 | } | |
627 | ||
c7909509 MS |
628 | #define nommu() 0 |
629 | ||
ab6494f0 | 630 | #else /* !CONFIG_MMU */ |
695ae0af | 631 | |
c7909509 MS |
632 | #define nommu() 1 |
633 | ||
f99d6034 | 634 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
c7909509 | 635 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL |
e9da6e99 | 636 | #define __alloc_from_pool(size, ret_page) NULL |
9848e48f | 637 | #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL |
c7909509 | 638 | #define __free_from_pool(cpu_addr, size) 0 |
9848e48f | 639 | #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0) |
c7909509 | 640 | #define __dma_free_remap(cpu_addr, size) do { } while (0) |
31ebf944 RK |
641 | |
642 | #endif /* CONFIG_MMU */ | |
643 | ||
c7909509 MS |
644 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
645 | struct page **ret_page) | |
ab6494f0 | 646 | { |
c7909509 MS |
647 | struct page *page; |
648 | page = __dma_alloc_buffer(dev, size, gfp); | |
649 | if (!page) | |
650 | return NULL; | |
651 | ||
652 | *ret_page = page; | |
653 | return page_address(page); | |
654 | } | |
655 | ||
656 | ||
657 | ||
658 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
dd37e940 | 659 | gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller) |
c7909509 MS |
660 | { |
661 | u64 mask = get_coherent_dma_mask(dev); | |
3dd7ea92 | 662 | struct page *page = NULL; |
31ebf944 | 663 | void *addr; |
ab6494f0 | 664 | |
c7909509 MS |
665 | #ifdef CONFIG_DMA_API_DEBUG |
666 | u64 limit = (mask + 1) & ~mask; | |
667 | if (limit && size >= limit) { | |
668 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
669 | size, mask); | |
670 | return NULL; | |
671 | } | |
672 | #endif | |
673 | ||
674 | if (!mask) | |
675 | return NULL; | |
676 | ||
677 | if (mask < 0xffffffffULL) | |
678 | gfp |= GFP_DMA; | |
679 | ||
ea2e7057 SB |
680 | /* |
681 | * Following is a work-around (a.k.a. hack) to prevent pages | |
682 | * with __GFP_COMP being passed to split_page() which cannot | |
683 | * handle them. The real problem is that this flag probably | |
684 | * should be 0 on ARM as it is not supported on this | |
685 | * platform; see CONFIG_HUGETLBFS. | |
686 | */ | |
687 | gfp &= ~(__GFP_COMP); | |
688 | ||
553ac788 | 689 | *handle = DMA_ERROR_CODE; |
04da5694 | 690 | size = PAGE_ALIGN(size); |
ab6494f0 | 691 | |
dd37e940 | 692 | if (is_coherent || nommu()) |
c7909509 | 693 | addr = __alloc_simple_buffer(dev, size, gfp, &page); |
633dc92a | 694 | else if (!(gfp & __GFP_WAIT)) |
e9da6e99 | 695 | addr = __alloc_from_pool(size, &page); |
e464ef16 | 696 | else if (!dev_get_cma_area(dev)) |
c7909509 | 697 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller); |
31ebf944 | 698 | else |
9848e48f | 699 | addr = __alloc_from_contiguous(dev, size, prot, &page, caller); |
695ae0af | 700 | |
31ebf944 | 701 | if (addr) |
9eedd963 | 702 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
695ae0af | 703 | |
31ebf944 RK |
704 | return addr; |
705 | } | |
1da177e4 LT |
706 | |
707 | /* | |
708 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
709 | * virtual and bus address for that space. | |
710 | */ | |
f99d6034 MS |
711 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
712 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 713 | { |
0ea1ec71 | 714 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
1fe53268 DB |
715 | void *memory; |
716 | ||
717 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
718 | return memory; | |
719 | ||
dd37e940 RH |
720 | return __dma_alloc(dev, size, handle, gfp, prot, false, |
721 | __builtin_return_address(0)); | |
722 | } | |
723 | ||
724 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, | |
725 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
726 | { | |
0ea1ec71 | 727 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
dd37e940 RH |
728 | void *memory; |
729 | ||
730 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
731 | return memory; | |
732 | ||
733 | return __dma_alloc(dev, size, handle, gfp, prot, true, | |
45cd5290 | 734 | __builtin_return_address(0)); |
1da177e4 | 735 | } |
1da177e4 LT |
736 | |
737 | /* | |
f99d6034 | 738 | * Create userspace mapping for the DMA-coherent memory. |
1da177e4 | 739 | */ |
f99d6034 MS |
740 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
741 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
742 | struct dma_attrs *attrs) | |
1da177e4 | 743 | { |
ab6494f0 CM |
744 | int ret = -ENXIO; |
745 | #ifdef CONFIG_MMU | |
50262a4b MS |
746 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
747 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 748 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
749 | unsigned long off = vma->vm_pgoff; |
750 | ||
f99d6034 MS |
751 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
752 | ||
47142f07 MS |
753 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
754 | return ret; | |
755 | ||
50262a4b MS |
756 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
757 | ret = remap_pfn_range(vma, vma->vm_start, | |
758 | pfn + off, | |
759 | vma->vm_end - vma->vm_start, | |
760 | vma->vm_page_prot); | |
761 | } | |
ab6494f0 | 762 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
763 | |
764 | return ret; | |
765 | } | |
766 | ||
1da177e4 | 767 | /* |
c7909509 | 768 | * Free a buffer as defined by the above mapping. |
1da177e4 | 769 | */ |
dd37e940 RH |
770 | static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
771 | dma_addr_t handle, struct dma_attrs *attrs, | |
772 | bool is_coherent) | |
1da177e4 | 773 | { |
c7909509 | 774 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
5edf71ae | 775 | |
1fe53268 DB |
776 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
777 | return; | |
778 | ||
3e82d012 RK |
779 | size = PAGE_ALIGN(size); |
780 | ||
dd37e940 | 781 | if (is_coherent || nommu()) { |
c7909509 | 782 | __dma_free_buffer(page, size); |
d9e0d149 AK |
783 | } else if (__free_from_pool(cpu_addr, size)) { |
784 | return; | |
e464ef16 | 785 | } else if (!dev_get_cma_area(dev)) { |
695ae0af | 786 | __dma_free_remap(cpu_addr, size); |
c7909509 MS |
787 | __dma_free_buffer(page, size); |
788 | } else { | |
c7909509 MS |
789 | /* |
790 | * Non-atomic allocations cannot be freed with IRQs disabled | |
791 | */ | |
792 | WARN_ON(irqs_disabled()); | |
9848e48f | 793 | __free_from_contiguous(dev, page, cpu_addr, size); |
c7909509 | 794 | } |
1da177e4 | 795 | } |
afd1a321 | 796 | |
dd37e940 RH |
797 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
798 | dma_addr_t handle, struct dma_attrs *attrs) | |
799 | { | |
800 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, false); | |
801 | } | |
802 | ||
803 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
804 | dma_addr_t handle, struct dma_attrs *attrs) | |
805 | { | |
806 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, true); | |
807 | } | |
808 | ||
dc2832e1 MS |
809 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
810 | void *cpu_addr, dma_addr_t handle, size_t size, | |
811 | struct dma_attrs *attrs) | |
812 | { | |
813 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
814 | int ret; | |
815 | ||
816 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
817 | if (unlikely(ret)) | |
818 | return ret; | |
819 | ||
820 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
821 | return 0; | |
822 | } | |
823 | ||
4ea0d737 | 824 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
825 | size_t size, enum dma_data_direction dir, |
826 | void (*op)(const void *, size_t, int)) | |
43377453 | 827 | { |
15653371 RK |
828 | unsigned long pfn; |
829 | size_t left = size; | |
830 | ||
831 | pfn = page_to_pfn(page) + offset / PAGE_SIZE; | |
832 | offset %= PAGE_SIZE; | |
833 | ||
43377453 NP |
834 | /* |
835 | * A single sg entry may refer to multiple physically contiguous | |
836 | * pages. But we still need to process highmem pages individually. | |
837 | * If highmem is not configured then the bulk of this loop gets | |
838 | * optimized out. | |
839 | */ | |
43377453 NP |
840 | do { |
841 | size_t len = left; | |
93f1d629 RK |
842 | void *vaddr; |
843 | ||
15653371 RK |
844 | page = pfn_to_page(pfn); |
845 | ||
93f1d629 | 846 | if (PageHighMem(page)) { |
15653371 | 847 | if (len + offset > PAGE_SIZE) |
93f1d629 | 848 | len = PAGE_SIZE - offset; |
dd0f67f4 JK |
849 | |
850 | if (cache_is_vipt_nonaliasing()) { | |
39af22a7 | 851 | vaddr = kmap_atomic(page); |
7e5a69e8 | 852 | op(vaddr + offset, len, dir); |
39af22a7 | 853 | kunmap_atomic(vaddr); |
dd0f67f4 JK |
854 | } else { |
855 | vaddr = kmap_high_get(page); | |
856 | if (vaddr) { | |
857 | op(vaddr + offset, len, dir); | |
858 | kunmap_high(page); | |
859 | } | |
43377453 | 860 | } |
93f1d629 RK |
861 | } else { |
862 | vaddr = page_address(page) + offset; | |
a9c9147e | 863 | op(vaddr, len, dir); |
43377453 | 864 | } |
43377453 | 865 | offset = 0; |
15653371 | 866 | pfn++; |
43377453 NP |
867 | left -= len; |
868 | } while (left); | |
869 | } | |
4ea0d737 | 870 | |
51fde349 MS |
871 | /* |
872 | * Make an area consistent for devices. | |
873 | * Note: Drivers should NOT use this function directly, as it will break | |
874 | * platforms with CONFIG_DMABOUNCE. | |
875 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
876 | */ | |
877 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
878 | size_t size, enum dma_data_direction dir) |
879 | { | |
2161c248 | 880 | phys_addr_t paddr; |
65af191a | 881 | |
a9c9147e | 882 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
883 | |
884 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
885 | if (dir == DMA_FROM_DEVICE) { |
886 | outer_inv_range(paddr, paddr + size); | |
887 | } else { | |
888 | outer_clean_range(paddr, paddr + size); | |
889 | } | |
890 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 891 | } |
4ea0d737 | 892 | |
51fde349 | 893 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
894 | size_t size, enum dma_data_direction dir) |
895 | { | |
2161c248 | 896 | phys_addr_t paddr = page_to_phys(page) + off; |
2ffe2da3 RK |
897 | |
898 | /* FIXME: non-speculating: not required */ | |
deace4a6 RK |
899 | /* in any case, don't bother invalidating if DMA to device */ |
900 | if (dir != DMA_TO_DEVICE) { | |
2ffe2da3 RK |
901 | outer_inv_range(paddr, paddr + size); |
902 | ||
deace4a6 RK |
903 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
904 | } | |
c0177800 CM |
905 | |
906 | /* | |
b2a234ed | 907 | * Mark the D-cache clean for these pages to avoid extra flushing. |
c0177800 | 908 | */ |
b2a234ed ML |
909 | if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) { |
910 | unsigned long pfn; | |
911 | size_t left = size; | |
912 | ||
913 | pfn = page_to_pfn(page) + off / PAGE_SIZE; | |
914 | off %= PAGE_SIZE; | |
915 | if (off) { | |
916 | pfn++; | |
917 | left -= PAGE_SIZE - off; | |
918 | } | |
919 | while (left >= PAGE_SIZE) { | |
920 | page = pfn_to_page(pfn++); | |
921 | set_bit(PG_dcache_clean, &page->flags); | |
922 | left -= PAGE_SIZE; | |
923 | } | |
924 | } | |
4ea0d737 | 925 | } |
43377453 | 926 | |
afd1a321 | 927 | /** |
2a550e73 | 928 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
929 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
930 | * @sg: list of buffers | |
931 | * @nents: number of buffers to map | |
932 | * @dir: DMA transfer direction | |
933 | * | |
934 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
935 | * This is the scatter-gather version of the dma_map_single interface. | |
936 | * Here the scatter gather list elements are each tagged with the | |
937 | * appropriate dma address and length. They are obtained via | |
938 | * sg_dma_{address,length}. | |
939 | * | |
940 | * Device ownership issues as mentioned for dma_map_single are the same | |
941 | * here. | |
942 | */ | |
2dc6a016 MS |
943 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
944 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 945 | { |
2a550e73 | 946 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 947 | struct scatterlist *s; |
01135d92 | 948 | int i, j; |
afd1a321 RK |
949 | |
950 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
951 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
952 | s->dma_length = s->length; | |
953 | #endif | |
2a550e73 MS |
954 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
955 | s->length, dir, attrs); | |
01135d92 RK |
956 | if (dma_mapping_error(dev, s->dma_address)) |
957 | goto bad_mapping; | |
afd1a321 | 958 | } |
afd1a321 | 959 | return nents; |
01135d92 RK |
960 | |
961 | bad_mapping: | |
962 | for_each_sg(sg, s, i, j) | |
2a550e73 | 963 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 964 | return 0; |
afd1a321 | 965 | } |
afd1a321 RK |
966 | |
967 | /** | |
2a550e73 | 968 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
969 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
970 | * @sg: list of buffers | |
0adfca6f | 971 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
972 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
973 | * | |
974 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
975 | * rules concerning calls here are the same as for dma_unmap_single(). | |
976 | */ | |
2dc6a016 MS |
977 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
978 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 979 | { |
2a550e73 | 980 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 981 | struct scatterlist *s; |
01135d92 | 982 | |
01135d92 | 983 | int i; |
24056f52 | 984 | |
01135d92 | 985 | for_each_sg(sg, s, nents, i) |
2a550e73 | 986 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 987 | } |
afd1a321 RK |
988 | |
989 | /** | |
2a550e73 | 990 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
991 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
992 | * @sg: list of buffers | |
993 | * @nents: number of buffers to map (returned from dma_map_sg) | |
994 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
995 | */ | |
2dc6a016 | 996 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
997 | int nents, enum dma_data_direction dir) |
998 | { | |
2a550e73 | 999 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1000 | struct scatterlist *s; |
1001 | int i; | |
1002 | ||
2a550e73 MS |
1003 | for_each_sg(sg, s, nents, i) |
1004 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
1005 | dir); | |
afd1a321 | 1006 | } |
afd1a321 RK |
1007 | |
1008 | /** | |
2a550e73 | 1009 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
1010 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1011 | * @sg: list of buffers | |
1012 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1013 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1014 | */ | |
2dc6a016 | 1015 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1016 | int nents, enum dma_data_direction dir) |
1017 | { | |
2a550e73 | 1018 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1019 | struct scatterlist *s; |
1020 | int i; | |
1021 | ||
2a550e73 MS |
1022 | for_each_sg(sg, s, nents, i) |
1023 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
1024 | dir); | |
afd1a321 | 1025 | } |
24056f52 | 1026 | |
022ae537 RK |
1027 | /* |
1028 | * Return whether the given device DMA address mask can be supported | |
1029 | * properly. For example, if your device can only drive the low 24-bits | |
1030 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
1031 | * to this function. | |
1032 | */ | |
1033 | int dma_supported(struct device *dev, u64 mask) | |
1034 | { | |
9f28cde0 | 1035 | return __dma_supported(dev, mask, false); |
022ae537 RK |
1036 | } |
1037 | EXPORT_SYMBOL(dma_supported); | |
1038 | ||
87b54e78 | 1039 | int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
1040 | { |
1041 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
1042 | return -EIO; | |
1043 | ||
022ae537 | 1044 | *dev->dma_mask = dma_mask; |
022ae537 RK |
1045 | |
1046 | return 0; | |
1047 | } | |
022ae537 | 1048 | |
24056f52 RK |
1049 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
1050 | ||
1051 | static int __init dma_debug_do_init(void) | |
1052 | { | |
1053 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
1054 | return 0; | |
1055 | } | |
1056 | fs_initcall(dma_debug_do_init); | |
4ce63fcd MS |
1057 | |
1058 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
1059 | ||
1060 | /* IOMMU */ | |
1061 | ||
4d852ef8 AH |
1062 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping); |
1063 | ||
4ce63fcd MS |
1064 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, |
1065 | size_t size) | |
1066 | { | |
1067 | unsigned int order = get_order(size); | |
1068 | unsigned int align = 0; | |
1069 | unsigned int count, start; | |
006f841d | 1070 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1071 | unsigned long flags; |
4d852ef8 AH |
1072 | dma_addr_t iova; |
1073 | int i; | |
4ce63fcd | 1074 | |
60460abf SWK |
1075 | if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT) |
1076 | order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT; | |
1077 | ||
68efd7d2 MS |
1078 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1079 | align = (1 << order) - 1; | |
4ce63fcd MS |
1080 | |
1081 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 AH |
1082 | for (i = 0; i < mapping->nr_bitmaps; i++) { |
1083 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1084 | mapping->bits, 0, count, align); | |
1085 | ||
1086 | if (start > mapping->bits) | |
1087 | continue; | |
1088 | ||
1089 | bitmap_set(mapping->bitmaps[i], start, count); | |
1090 | break; | |
4ce63fcd MS |
1091 | } |
1092 | ||
4d852ef8 AH |
1093 | /* |
1094 | * No unused range found. Try to extend the existing mapping | |
1095 | * and perform a second attempt to reserve an IO virtual | |
1096 | * address range of size bytes. | |
1097 | */ | |
1098 | if (i == mapping->nr_bitmaps) { | |
1099 | if (extend_iommu_mapping(mapping)) { | |
1100 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1101 | return DMA_ERROR_CODE; | |
1102 | } | |
1103 | ||
1104 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1105 | mapping->bits, 0, count, align); | |
1106 | ||
1107 | if (start > mapping->bits) { | |
1108 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1109 | return DMA_ERROR_CODE; | |
1110 | } | |
1111 | ||
1112 | bitmap_set(mapping->bitmaps[i], start, count); | |
1113 | } | |
4ce63fcd MS |
1114 | spin_unlock_irqrestore(&mapping->lock, flags); |
1115 | ||
006f841d | 1116 | iova = mapping->base + (mapping_size * i); |
68efd7d2 | 1117 | iova += start << PAGE_SHIFT; |
4d852ef8 AH |
1118 | |
1119 | return iova; | |
4ce63fcd MS |
1120 | } |
1121 | ||
1122 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
1123 | dma_addr_t addr, size_t size) | |
1124 | { | |
4d852ef8 | 1125 | unsigned int start, count; |
006f841d | 1126 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1127 | unsigned long flags; |
4d852ef8 AH |
1128 | dma_addr_t bitmap_base; |
1129 | u32 bitmap_index; | |
1130 | ||
1131 | if (!size) | |
1132 | return; | |
1133 | ||
006f841d | 1134 | bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size; |
4d852ef8 AH |
1135 | BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions); |
1136 | ||
006f841d | 1137 | bitmap_base = mapping->base + mapping_size * bitmap_index; |
4d852ef8 | 1138 | |
68efd7d2 | 1139 | start = (addr - bitmap_base) >> PAGE_SHIFT; |
4d852ef8 | 1140 | |
006f841d | 1141 | if (addr + size > bitmap_base + mapping_size) { |
4d852ef8 AH |
1142 | /* |
1143 | * The address range to be freed reaches into the iova | |
1144 | * range of the next bitmap. This should not happen as | |
1145 | * we don't allow this in __alloc_iova (at the | |
1146 | * moment). | |
1147 | */ | |
1148 | BUG(); | |
1149 | } else | |
68efd7d2 | 1150 | count = size >> PAGE_SHIFT; |
4ce63fcd MS |
1151 | |
1152 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 | 1153 | bitmap_clear(mapping->bitmaps[bitmap_index], start, count); |
4ce63fcd MS |
1154 | spin_unlock_irqrestore(&mapping->lock, flags); |
1155 | } | |
1156 | ||
549a17e4 MS |
1157 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, |
1158 | gfp_t gfp, struct dma_attrs *attrs) | |
4ce63fcd MS |
1159 | { |
1160 | struct page **pages; | |
1161 | int count = size >> PAGE_SHIFT; | |
1162 | int array_size = count * sizeof(struct page *); | |
1163 | int i = 0; | |
1164 | ||
1165 | if (array_size <= PAGE_SIZE) | |
1166 | pages = kzalloc(array_size, gfp); | |
1167 | else | |
1168 | pages = vzalloc(array_size); | |
1169 | if (!pages) | |
1170 | return NULL; | |
1171 | ||
549a17e4 MS |
1172 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) |
1173 | { | |
1174 | unsigned long order = get_order(size); | |
1175 | struct page *page; | |
1176 | ||
1177 | page = dma_alloc_from_contiguous(dev, count, order); | |
1178 | if (!page) | |
1179 | goto error; | |
1180 | ||
1181 | __dma_clear_buffer(page, size); | |
1182 | ||
1183 | for (i = 0; i < count; i++) | |
1184 | pages[i] = page + i; | |
1185 | ||
1186 | return pages; | |
1187 | } | |
1188 | ||
f8669bef MS |
1189 | /* |
1190 | * IOMMU can map any pages, so himem can also be used here | |
1191 | */ | |
1192 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
1193 | ||
4ce63fcd | 1194 | while (count) { |
593f4735 | 1195 | int j, order = __fls(count); |
4ce63fcd | 1196 | |
f8669bef | 1197 | pages[i] = alloc_pages(gfp, order); |
4ce63fcd | 1198 | while (!pages[i] && order) |
f8669bef | 1199 | pages[i] = alloc_pages(gfp, --order); |
4ce63fcd MS |
1200 | if (!pages[i]) |
1201 | goto error; | |
1202 | ||
5a796eeb | 1203 | if (order) { |
4ce63fcd | 1204 | split_page(pages[i], order); |
5a796eeb HD |
1205 | j = 1 << order; |
1206 | while (--j) | |
1207 | pages[i + j] = pages[i] + j; | |
1208 | } | |
4ce63fcd MS |
1209 | |
1210 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
1211 | i += 1 << order; | |
1212 | count -= 1 << order; | |
1213 | } | |
1214 | ||
1215 | return pages; | |
1216 | error: | |
9fa8af91 | 1217 | while (i--) |
4ce63fcd MS |
1218 | if (pages[i]) |
1219 | __free_pages(pages[i], 0); | |
46c87852 | 1220 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1221 | kfree(pages); |
1222 | else | |
1223 | vfree(pages); | |
1224 | return NULL; | |
1225 | } | |
1226 | ||
549a17e4 MS |
1227 | static int __iommu_free_buffer(struct device *dev, struct page **pages, |
1228 | size_t size, struct dma_attrs *attrs) | |
4ce63fcd MS |
1229 | { |
1230 | int count = size >> PAGE_SHIFT; | |
1231 | int array_size = count * sizeof(struct page *); | |
1232 | int i; | |
549a17e4 MS |
1233 | |
1234 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) { | |
1235 | dma_release_from_contiguous(dev, pages[0], count); | |
1236 | } else { | |
1237 | for (i = 0; i < count; i++) | |
1238 | if (pages[i]) | |
1239 | __free_pages(pages[i], 0); | |
1240 | } | |
1241 | ||
46c87852 | 1242 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1243 | kfree(pages); |
1244 | else | |
1245 | vfree(pages); | |
1246 | return 0; | |
1247 | } | |
1248 | ||
1249 | /* | |
1250 | * Create a CPU mapping for a specified pages | |
1251 | */ | |
1252 | static void * | |
e9da6e99 MS |
1253 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1254 | const void *caller) | |
4ce63fcd | 1255 | { |
513510dd LA |
1256 | return dma_common_pages_remap(pages, size, |
1257 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller); | |
4ce63fcd MS |
1258 | return NULL; |
1259 | } | |
1260 | ||
1261 | /* | |
1262 | * Create a mapping in device IO address space for specified pages | |
1263 | */ | |
1264 | static dma_addr_t | |
1265 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1266 | { | |
1267 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1268 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1269 | dma_addr_t dma_addr, iova; | |
1270 | int i, ret = DMA_ERROR_CODE; | |
1271 | ||
1272 | dma_addr = __alloc_iova(mapping, size); | |
1273 | if (dma_addr == DMA_ERROR_CODE) | |
1274 | return dma_addr; | |
1275 | ||
1276 | iova = dma_addr; | |
1277 | for (i = 0; i < count; ) { | |
1278 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; | |
1279 | phys_addr_t phys = page_to_phys(pages[i]); | |
1280 | unsigned int len, j; | |
1281 | ||
1282 | for (j = i + 1; j < count; j++, next_pfn++) | |
1283 | if (page_to_pfn(pages[j]) != next_pfn) | |
1284 | break; | |
1285 | ||
1286 | len = (j - i) << PAGE_SHIFT; | |
c9b24996 AH |
1287 | ret = iommu_map(mapping->domain, iova, phys, len, |
1288 | IOMMU_READ|IOMMU_WRITE); | |
4ce63fcd MS |
1289 | if (ret < 0) |
1290 | goto fail; | |
1291 | iova += len; | |
1292 | i = j; | |
1293 | } | |
1294 | return dma_addr; | |
1295 | fail: | |
1296 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1297 | __free_iova(mapping, dma_addr, size); | |
1298 | return DMA_ERROR_CODE; | |
1299 | } | |
1300 | ||
1301 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1302 | { | |
1303 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1304 | ||
1305 | /* | |
1306 | * add optional in-page offset from iova to size and align | |
1307 | * result to page size | |
1308 | */ | |
1309 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1310 | iova &= PAGE_MASK; | |
1311 | ||
1312 | iommu_unmap(mapping->domain, iova, size); | |
1313 | __free_iova(mapping, iova, size); | |
1314 | return 0; | |
1315 | } | |
1316 | ||
665bad7b HD |
1317 | static struct page **__atomic_get_pages(void *addr) |
1318 | { | |
1319 | struct dma_pool *pool = &atomic_pool; | |
1320 | struct page **pages = pool->pages; | |
1321 | int offs = (addr - pool->vaddr) >> PAGE_SHIFT; | |
1322 | ||
1323 | return pages + offs; | |
1324 | } | |
1325 | ||
955c757e | 1326 | static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) |
e9da6e99 MS |
1327 | { |
1328 | struct vm_struct *area; | |
1329 | ||
665bad7b HD |
1330 | if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) |
1331 | return __atomic_get_pages(cpu_addr); | |
1332 | ||
955c757e MS |
1333 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1334 | return cpu_addr; | |
1335 | ||
e9da6e99 MS |
1336 | area = find_vm_area(cpu_addr); |
1337 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1338 | return area->pages; | |
1339 | return NULL; | |
1340 | } | |
1341 | ||
479ed93a HD |
1342 | static void *__iommu_alloc_atomic(struct device *dev, size_t size, |
1343 | dma_addr_t *handle) | |
1344 | { | |
1345 | struct page *page; | |
1346 | void *addr; | |
1347 | ||
1348 | addr = __alloc_from_pool(size, &page); | |
1349 | if (!addr) | |
1350 | return NULL; | |
1351 | ||
1352 | *handle = __iommu_create_mapping(dev, &page, size); | |
1353 | if (*handle == DMA_ERROR_CODE) | |
1354 | goto err_mapping; | |
1355 | ||
1356 | return addr; | |
1357 | ||
1358 | err_mapping: | |
1359 | __free_from_pool(addr, size); | |
1360 | return NULL; | |
1361 | } | |
1362 | ||
d5898291 | 1363 | static void __iommu_free_atomic(struct device *dev, void *cpu_addr, |
479ed93a HD |
1364 | dma_addr_t handle, size_t size) |
1365 | { | |
1366 | __iommu_remove_mapping(dev, handle, size); | |
d5898291 | 1367 | __free_from_pool(cpu_addr, size); |
479ed93a HD |
1368 | } |
1369 | ||
4ce63fcd MS |
1370 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
1371 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1372 | { | |
71b55663 | 1373 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
4ce63fcd MS |
1374 | struct page **pages; |
1375 | void *addr = NULL; | |
1376 | ||
1377 | *handle = DMA_ERROR_CODE; | |
1378 | size = PAGE_ALIGN(size); | |
1379 | ||
10c8562f | 1380 | if (!(gfp & __GFP_WAIT)) |
479ed93a HD |
1381 | return __iommu_alloc_atomic(dev, size, handle); |
1382 | ||
5b91a98c RZ |
1383 | /* |
1384 | * Following is a work-around (a.k.a. hack) to prevent pages | |
1385 | * with __GFP_COMP being passed to split_page() which cannot | |
1386 | * handle them. The real problem is that this flag probably | |
1387 | * should be 0 on ARM as it is not supported on this | |
1388 | * platform; see CONFIG_HUGETLBFS. | |
1389 | */ | |
1390 | gfp &= ~(__GFP_COMP); | |
1391 | ||
549a17e4 | 1392 | pages = __iommu_alloc_buffer(dev, size, gfp, attrs); |
4ce63fcd MS |
1393 | if (!pages) |
1394 | return NULL; | |
1395 | ||
1396 | *handle = __iommu_create_mapping(dev, pages, size); | |
1397 | if (*handle == DMA_ERROR_CODE) | |
1398 | goto err_buffer; | |
1399 | ||
955c757e MS |
1400 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1401 | return pages; | |
1402 | ||
e9da6e99 MS |
1403 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1404 | __builtin_return_address(0)); | |
4ce63fcd MS |
1405 | if (!addr) |
1406 | goto err_mapping; | |
1407 | ||
1408 | return addr; | |
1409 | ||
1410 | err_mapping: | |
1411 | __iommu_remove_mapping(dev, *handle, size); | |
1412 | err_buffer: | |
549a17e4 | 1413 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1414 | return NULL; |
1415 | } | |
1416 | ||
1417 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1418 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1419 | struct dma_attrs *attrs) | |
1420 | { | |
e9da6e99 MS |
1421 | unsigned long uaddr = vma->vm_start; |
1422 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1423 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1424 | |
1425 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
4ce63fcd | 1426 | |
e9da6e99 MS |
1427 | if (!pages) |
1428 | return -ENXIO; | |
4ce63fcd | 1429 | |
e9da6e99 MS |
1430 | do { |
1431 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1432 | if (ret) { | |
1433 | pr_err("Remapping memory failed: %d\n", ret); | |
1434 | return ret; | |
1435 | } | |
1436 | uaddr += PAGE_SIZE; | |
1437 | usize -= PAGE_SIZE; | |
1438 | } while (usize > 0); | |
4ce63fcd | 1439 | |
4ce63fcd MS |
1440 | return 0; |
1441 | } | |
1442 | ||
1443 | /* | |
1444 | * free a page as defined by the above mapping. | |
1445 | * Must not be called with IRQs disabled. | |
1446 | */ | |
1447 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1448 | dma_addr_t handle, struct dma_attrs *attrs) | |
1449 | { | |
836bfa0d | 1450 | struct page **pages; |
4ce63fcd MS |
1451 | size = PAGE_ALIGN(size); |
1452 | ||
836bfa0d YC |
1453 | if (__in_atomic_pool(cpu_addr, size)) { |
1454 | __iommu_free_atomic(dev, cpu_addr, handle, size); | |
e9da6e99 | 1455 | return; |
4ce63fcd | 1456 | } |
e9da6e99 | 1457 | |
836bfa0d YC |
1458 | pages = __iommu_get_pages(cpu_addr, attrs); |
1459 | if (!pages) { | |
1460 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
479ed93a HD |
1461 | return; |
1462 | } | |
1463 | ||
955c757e | 1464 | if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { |
513510dd LA |
1465 | dma_common_free_remap(cpu_addr, size, |
1466 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
955c757e | 1467 | } |
e9da6e99 MS |
1468 | |
1469 | __iommu_remove_mapping(dev, handle, size); | |
549a17e4 | 1470 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1471 | } |
1472 | ||
dc2832e1 MS |
1473 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1474 | void *cpu_addr, dma_addr_t dma_addr, | |
1475 | size_t size, struct dma_attrs *attrs) | |
1476 | { | |
1477 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1478 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1479 | ||
1480 | if (!pages) | |
1481 | return -ENXIO; | |
1482 | ||
1483 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1484 | GFP_KERNEL); | |
4ce63fcd MS |
1485 | } |
1486 | ||
c9b24996 AH |
1487 | static int __dma_direction_to_prot(enum dma_data_direction dir) |
1488 | { | |
1489 | int prot; | |
1490 | ||
1491 | switch (dir) { | |
1492 | case DMA_BIDIRECTIONAL: | |
1493 | prot = IOMMU_READ | IOMMU_WRITE; | |
1494 | break; | |
1495 | case DMA_TO_DEVICE: | |
1496 | prot = IOMMU_READ; | |
1497 | break; | |
1498 | case DMA_FROM_DEVICE: | |
1499 | prot = IOMMU_WRITE; | |
1500 | break; | |
1501 | default: | |
1502 | prot = 0; | |
1503 | } | |
1504 | ||
1505 | return prot; | |
1506 | } | |
1507 | ||
4ce63fcd MS |
1508 | /* |
1509 | * Map a part of the scatter-gather list into contiguous io address space | |
1510 | */ | |
1511 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1512 | size_t size, dma_addr_t *handle, | |
0fa478df RH |
1513 | enum dma_data_direction dir, struct dma_attrs *attrs, |
1514 | bool is_coherent) | |
4ce63fcd MS |
1515 | { |
1516 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1517 | dma_addr_t iova, iova_base; | |
1518 | int ret = 0; | |
1519 | unsigned int count; | |
1520 | struct scatterlist *s; | |
c9b24996 | 1521 | int prot; |
4ce63fcd MS |
1522 | |
1523 | size = PAGE_ALIGN(size); | |
1524 | *handle = DMA_ERROR_CODE; | |
1525 | ||
1526 | iova_base = iova = __alloc_iova(mapping, size); | |
1527 | if (iova == DMA_ERROR_CODE) | |
1528 | return -ENOMEM; | |
1529 | ||
1530 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
1531 | phys_addr_t phys = page_to_phys(sg_page(s)); | |
1532 | unsigned int len = PAGE_ALIGN(s->offset + s->length); | |
1533 | ||
0fa478df RH |
1534 | if (!is_coherent && |
1535 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1536 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1537 | ||
c9b24996 AH |
1538 | prot = __dma_direction_to_prot(dir); |
1539 | ||
1540 | ret = iommu_map(mapping->domain, iova, phys, len, prot); | |
4ce63fcd MS |
1541 | if (ret < 0) |
1542 | goto fail; | |
1543 | count += len >> PAGE_SHIFT; | |
1544 | iova += len; | |
1545 | } | |
1546 | *handle = iova_base; | |
1547 | ||
1548 | return 0; | |
1549 | fail: | |
1550 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1551 | __free_iova(mapping, iova_base, size); | |
1552 | return ret; | |
1553 | } | |
1554 | ||
0fa478df RH |
1555 | static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
1556 | enum dma_data_direction dir, struct dma_attrs *attrs, | |
1557 | bool is_coherent) | |
4ce63fcd MS |
1558 | { |
1559 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1560 | int i, count = 0; | |
1561 | unsigned int offset = s->offset; | |
1562 | unsigned int size = s->offset + s->length; | |
1563 | unsigned int max = dma_get_max_seg_size(dev); | |
1564 | ||
1565 | for (i = 1; i < nents; i++) { | |
1566 | s = sg_next(s); | |
1567 | ||
1568 | s->dma_address = DMA_ERROR_CODE; | |
1569 | s->dma_length = 0; | |
1570 | ||
1571 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1572 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
0fa478df | 1573 | dir, attrs, is_coherent) < 0) |
4ce63fcd MS |
1574 | goto bad_mapping; |
1575 | ||
1576 | dma->dma_address += offset; | |
1577 | dma->dma_length = size - offset; | |
1578 | ||
1579 | size = offset = s->offset; | |
1580 | start = s; | |
1581 | dma = sg_next(dma); | |
1582 | count += 1; | |
1583 | } | |
1584 | size += s->length; | |
1585 | } | |
0fa478df RH |
1586 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs, |
1587 | is_coherent) < 0) | |
4ce63fcd MS |
1588 | goto bad_mapping; |
1589 | ||
1590 | dma->dma_address += offset; | |
1591 | dma->dma_length = size - offset; | |
1592 | ||
1593 | return count+1; | |
1594 | ||
1595 | bad_mapping: | |
1596 | for_each_sg(sg, s, count, i) | |
1597 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1598 | return 0; | |
1599 | } | |
1600 | ||
1601 | /** | |
0fa478df | 1602 | * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA |
4ce63fcd MS |
1603 | * @dev: valid struct device pointer |
1604 | * @sg: list of buffers | |
0fa478df RH |
1605 | * @nents: number of buffers to map |
1606 | * @dir: DMA transfer direction | |
4ce63fcd | 1607 | * |
0fa478df RH |
1608 | * Map a set of i/o coherent buffers described by scatterlist in streaming |
1609 | * mode for DMA. The scatter gather list elements are merged together (if | |
1610 | * possible) and tagged with the appropriate dma address and length. They are | |
1611 | * obtained via sg_dma_{address,length}. | |
4ce63fcd | 1612 | */ |
0fa478df RH |
1613 | int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg, |
1614 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1615 | { | |
1616 | return __iommu_map_sg(dev, sg, nents, dir, attrs, true); | |
1617 | } | |
1618 | ||
1619 | /** | |
1620 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1621 | * @dev: valid struct device pointer | |
1622 | * @sg: list of buffers | |
1623 | * @nents: number of buffers to map | |
1624 | * @dir: DMA transfer direction | |
1625 | * | |
1626 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1627 | * The scatter gather list elements are merged together (if possible) and | |
1628 | * tagged with the appropriate dma address and length. They are obtained via | |
1629 | * sg_dma_{address,length}. | |
1630 | */ | |
1631 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, | |
1632 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1633 | { | |
1634 | return __iommu_map_sg(dev, sg, nents, dir, attrs, false); | |
1635 | } | |
1636 | ||
1637 | static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1638 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs, | |
1639 | bool is_coherent) | |
4ce63fcd MS |
1640 | { |
1641 | struct scatterlist *s; | |
1642 | int i; | |
1643 | ||
1644 | for_each_sg(sg, s, nents, i) { | |
1645 | if (sg_dma_len(s)) | |
1646 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1647 | sg_dma_len(s)); | |
0fa478df | 1648 | if (!is_coherent && |
97ef952a | 1649 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1650 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1651 | s->length, dir); | |
1652 | } | |
1653 | } | |
1654 | ||
0fa478df RH |
1655 | /** |
1656 | * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1657 | * @dev: valid struct device pointer | |
1658 | * @sg: list of buffers | |
1659 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1660 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1661 | * | |
1662 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1663 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1664 | */ | |
1665 | void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1666 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1667 | { | |
1668 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, true); | |
1669 | } | |
1670 | ||
1671 | /** | |
1672 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1673 | * @dev: valid struct device pointer | |
1674 | * @sg: list of buffers | |
1675 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1676 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1677 | * | |
1678 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1679 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1680 | */ | |
1681 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1682 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1683 | { | |
1684 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, false); | |
1685 | } | |
1686 | ||
4ce63fcd MS |
1687 | /** |
1688 | * arm_iommu_sync_sg_for_cpu | |
1689 | * @dev: valid struct device pointer | |
1690 | * @sg: list of buffers | |
1691 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1692 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1693 | */ | |
1694 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1695 | int nents, enum dma_data_direction dir) | |
1696 | { | |
1697 | struct scatterlist *s; | |
1698 | int i; | |
1699 | ||
1700 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1701 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1702 | |
1703 | } | |
1704 | ||
1705 | /** | |
1706 | * arm_iommu_sync_sg_for_device | |
1707 | * @dev: valid struct device pointer | |
1708 | * @sg: list of buffers | |
1709 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1710 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1711 | */ | |
1712 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1713 | int nents, enum dma_data_direction dir) | |
1714 | { | |
1715 | struct scatterlist *s; | |
1716 | int i; | |
1717 | ||
1718 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1719 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1720 | } |
1721 | ||
1722 | ||
1723 | /** | |
0fa478df | 1724 | * arm_coherent_iommu_map_page |
4ce63fcd MS |
1725 | * @dev: valid struct device pointer |
1726 | * @page: page that buffer resides in | |
1727 | * @offset: offset into page for start of buffer | |
1728 | * @size: size of buffer to map | |
1729 | * @dir: DMA transfer direction | |
1730 | * | |
0fa478df | 1731 | * Coherent IOMMU aware version of arm_dma_map_page() |
4ce63fcd | 1732 | */ |
0fa478df | 1733 | static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page, |
4ce63fcd MS |
1734 | unsigned long offset, size_t size, enum dma_data_direction dir, |
1735 | struct dma_attrs *attrs) | |
1736 | { | |
1737 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1738 | dma_addr_t dma_addr; | |
13987d68 | 1739 | int ret, prot, len = PAGE_ALIGN(size + offset); |
4ce63fcd | 1740 | |
4ce63fcd MS |
1741 | dma_addr = __alloc_iova(mapping, len); |
1742 | if (dma_addr == DMA_ERROR_CODE) | |
1743 | return dma_addr; | |
1744 | ||
c9b24996 | 1745 | prot = __dma_direction_to_prot(dir); |
13987d68 WD |
1746 | |
1747 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot); | |
4ce63fcd MS |
1748 | if (ret < 0) |
1749 | goto fail; | |
1750 | ||
1751 | return dma_addr + offset; | |
1752 | fail: | |
1753 | __free_iova(mapping, dma_addr, len); | |
1754 | return DMA_ERROR_CODE; | |
1755 | } | |
1756 | ||
0fa478df RH |
1757 | /** |
1758 | * arm_iommu_map_page | |
1759 | * @dev: valid struct device pointer | |
1760 | * @page: page that buffer resides in | |
1761 | * @offset: offset into page for start of buffer | |
1762 | * @size: size of buffer to map | |
1763 | * @dir: DMA transfer direction | |
1764 | * | |
1765 | * IOMMU aware version of arm_dma_map_page() | |
1766 | */ | |
1767 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1768 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1769 | struct dma_attrs *attrs) | |
1770 | { | |
1771 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
1772 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1773 | ||
1774 | return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs); | |
1775 | } | |
1776 | ||
1777 | /** | |
1778 | * arm_coherent_iommu_unmap_page | |
1779 | * @dev: valid struct device pointer | |
1780 | * @handle: DMA address of buffer | |
1781 | * @size: size of buffer (same as passed to dma_map_page) | |
1782 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1783 | * | |
1784 | * Coherent IOMMU aware version of arm_dma_unmap_page() | |
1785 | */ | |
1786 | static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1787 | size_t size, enum dma_data_direction dir, | |
1788 | struct dma_attrs *attrs) | |
1789 | { | |
1790 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1791 | dma_addr_t iova = handle & PAGE_MASK; | |
0fa478df RH |
1792 | int offset = handle & ~PAGE_MASK; |
1793 | int len = PAGE_ALIGN(size + offset); | |
1794 | ||
1795 | if (!iova) | |
1796 | return; | |
1797 | ||
1798 | iommu_unmap(mapping->domain, iova, len); | |
1799 | __free_iova(mapping, iova, len); | |
1800 | } | |
1801 | ||
4ce63fcd MS |
1802 | /** |
1803 | * arm_iommu_unmap_page | |
1804 | * @dev: valid struct device pointer | |
1805 | * @handle: DMA address of buffer | |
1806 | * @size: size of buffer (same as passed to dma_map_page) | |
1807 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1808 | * | |
1809 | * IOMMU aware version of arm_dma_unmap_page() | |
1810 | */ | |
1811 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1812 | size_t size, enum dma_data_direction dir, | |
1813 | struct dma_attrs *attrs) | |
1814 | { | |
1815 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1816 | dma_addr_t iova = handle & PAGE_MASK; | |
1817 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1818 | int offset = handle & ~PAGE_MASK; | |
1819 | int len = PAGE_ALIGN(size + offset); | |
1820 | ||
1821 | if (!iova) | |
1822 | return; | |
1823 | ||
0fa478df | 1824 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1825 | __dma_page_dev_to_cpu(page, offset, size, dir); |
1826 | ||
1827 | iommu_unmap(mapping->domain, iova, len); | |
1828 | __free_iova(mapping, iova, len); | |
1829 | } | |
1830 | ||
1831 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1832 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1833 | { | |
1834 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1835 | dma_addr_t iova = handle & PAGE_MASK; | |
1836 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1837 | unsigned int offset = handle & ~PAGE_MASK; | |
1838 | ||
1839 | if (!iova) | |
1840 | return; | |
1841 | ||
0fa478df | 1842 | __dma_page_dev_to_cpu(page, offset, size, dir); |
4ce63fcd MS |
1843 | } |
1844 | ||
1845 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1846 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1847 | { | |
1848 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1849 | dma_addr_t iova = handle & PAGE_MASK; | |
1850 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1851 | unsigned int offset = handle & ~PAGE_MASK; | |
1852 | ||
1853 | if (!iova) | |
1854 | return; | |
1855 | ||
1856 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1857 | } | |
1858 | ||
1859 | struct dma_map_ops iommu_ops = { | |
1860 | .alloc = arm_iommu_alloc_attrs, | |
1861 | .free = arm_iommu_free_attrs, | |
1862 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 1863 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
1864 | |
1865 | .map_page = arm_iommu_map_page, | |
1866 | .unmap_page = arm_iommu_unmap_page, | |
1867 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1868 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1869 | ||
1870 | .map_sg = arm_iommu_map_sg, | |
1871 | .unmap_sg = arm_iommu_unmap_sg, | |
1872 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1873 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
d09e1333 HD |
1874 | |
1875 | .set_dma_mask = arm_dma_set_mask, | |
4ce63fcd MS |
1876 | }; |
1877 | ||
0fa478df RH |
1878 | struct dma_map_ops iommu_coherent_ops = { |
1879 | .alloc = arm_iommu_alloc_attrs, | |
1880 | .free = arm_iommu_free_attrs, | |
1881 | .mmap = arm_iommu_mmap_attrs, | |
1882 | .get_sgtable = arm_iommu_get_sgtable, | |
1883 | ||
1884 | .map_page = arm_coherent_iommu_map_page, | |
1885 | .unmap_page = arm_coherent_iommu_unmap_page, | |
1886 | ||
1887 | .map_sg = arm_coherent_iommu_map_sg, | |
1888 | .unmap_sg = arm_coherent_iommu_unmap_sg, | |
d09e1333 HD |
1889 | |
1890 | .set_dma_mask = arm_dma_set_mask, | |
0fa478df RH |
1891 | }; |
1892 | ||
4ce63fcd MS |
1893 | /** |
1894 | * arm_iommu_create_mapping | |
1895 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
1896 | * @base: start address of the valid IO address space | |
68efd7d2 | 1897 | * @size: maximum size of the valid IO address space |
4ce63fcd MS |
1898 | * |
1899 | * Creates a mapping structure which holds information about used/unused | |
1900 | * IO address ranges, which is required to perform memory allocation and | |
1901 | * mapping with IOMMU aware functions. | |
1902 | * | |
1903 | * The client device need to be attached to the mapping with | |
1904 | * arm_iommu_attach_device function. | |
1905 | */ | |
1906 | struct dma_iommu_mapping * | |
68efd7d2 | 1907 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size) |
4ce63fcd | 1908 | { |
68efd7d2 MS |
1909 | unsigned int bits = size >> PAGE_SHIFT; |
1910 | unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); | |
4ce63fcd | 1911 | struct dma_iommu_mapping *mapping; |
68efd7d2 | 1912 | int extensions = 1; |
4ce63fcd MS |
1913 | int err = -ENOMEM; |
1914 | ||
68efd7d2 | 1915 | if (!bitmap_size) |
4ce63fcd MS |
1916 | return ERR_PTR(-EINVAL); |
1917 | ||
68efd7d2 MS |
1918 | if (bitmap_size > PAGE_SIZE) { |
1919 | extensions = bitmap_size / PAGE_SIZE; | |
1920 | bitmap_size = PAGE_SIZE; | |
1921 | } | |
1922 | ||
4ce63fcd MS |
1923 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); |
1924 | if (!mapping) | |
1925 | goto err; | |
1926 | ||
68efd7d2 MS |
1927 | mapping->bitmap_size = bitmap_size; |
1928 | mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *), | |
4d852ef8 AH |
1929 | GFP_KERNEL); |
1930 | if (!mapping->bitmaps) | |
4ce63fcd MS |
1931 | goto err2; |
1932 | ||
68efd7d2 | 1933 | mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL); |
4d852ef8 AH |
1934 | if (!mapping->bitmaps[0]) |
1935 | goto err3; | |
1936 | ||
1937 | mapping->nr_bitmaps = 1; | |
1938 | mapping->extensions = extensions; | |
4ce63fcd | 1939 | mapping->base = base; |
68efd7d2 | 1940 | mapping->bits = BITS_PER_BYTE * bitmap_size; |
4d852ef8 | 1941 | |
4ce63fcd MS |
1942 | spin_lock_init(&mapping->lock); |
1943 | ||
1944 | mapping->domain = iommu_domain_alloc(bus); | |
1945 | if (!mapping->domain) | |
4d852ef8 | 1946 | goto err4; |
4ce63fcd MS |
1947 | |
1948 | kref_init(&mapping->kref); | |
1949 | return mapping; | |
4d852ef8 AH |
1950 | err4: |
1951 | kfree(mapping->bitmaps[0]); | |
4ce63fcd | 1952 | err3: |
4d852ef8 | 1953 | kfree(mapping->bitmaps); |
4ce63fcd MS |
1954 | err2: |
1955 | kfree(mapping); | |
1956 | err: | |
1957 | return ERR_PTR(err); | |
1958 | } | |
18177d12 | 1959 | EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); |
4ce63fcd MS |
1960 | |
1961 | static void release_iommu_mapping(struct kref *kref) | |
1962 | { | |
4d852ef8 | 1963 | int i; |
4ce63fcd MS |
1964 | struct dma_iommu_mapping *mapping = |
1965 | container_of(kref, struct dma_iommu_mapping, kref); | |
1966 | ||
1967 | iommu_domain_free(mapping->domain); | |
4d852ef8 AH |
1968 | for (i = 0; i < mapping->nr_bitmaps; i++) |
1969 | kfree(mapping->bitmaps[i]); | |
1970 | kfree(mapping->bitmaps); | |
4ce63fcd MS |
1971 | kfree(mapping); |
1972 | } | |
1973 | ||
4d852ef8 AH |
1974 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) |
1975 | { | |
1976 | int next_bitmap; | |
1977 | ||
1978 | if (mapping->nr_bitmaps > mapping->extensions) | |
1979 | return -EINVAL; | |
1980 | ||
1981 | next_bitmap = mapping->nr_bitmaps; | |
1982 | mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size, | |
1983 | GFP_ATOMIC); | |
1984 | if (!mapping->bitmaps[next_bitmap]) | |
1985 | return -ENOMEM; | |
1986 | ||
1987 | mapping->nr_bitmaps++; | |
1988 | ||
1989 | return 0; | |
1990 | } | |
1991 | ||
4ce63fcd MS |
1992 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) |
1993 | { | |
1994 | if (mapping) | |
1995 | kref_put(&mapping->kref, release_iommu_mapping); | |
1996 | } | |
18177d12 | 1997 | EXPORT_SYMBOL_GPL(arm_iommu_release_mapping); |
4ce63fcd MS |
1998 | |
1999 | /** | |
2000 | * arm_iommu_attach_device | |
2001 | * @dev: valid struct device pointer | |
2002 | * @mapping: io address space mapping structure (returned from | |
2003 | * arm_iommu_create_mapping) | |
2004 | * | |
2005 | * Attaches specified io address space mapping to the provided device, | |
2006 | * this replaces the dma operations (dma_map_ops pointer) with the | |
2007 | * IOMMU aware version. More than one client might be attached to | |
2008 | * the same io address space mapping. | |
2009 | */ | |
2010 | int arm_iommu_attach_device(struct device *dev, | |
2011 | struct dma_iommu_mapping *mapping) | |
2012 | { | |
2013 | int err; | |
2014 | ||
2015 | err = iommu_attach_device(mapping->domain, dev); | |
2016 | if (err) | |
2017 | return err; | |
2018 | ||
2019 | kref_get(&mapping->kref); | |
2020 | dev->archdata.mapping = mapping; | |
2021 | set_dma_ops(dev, &iommu_ops); | |
2022 | ||
75c59716 | 2023 | pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev)); |
4ce63fcd MS |
2024 | return 0; |
2025 | } | |
18177d12 | 2026 | EXPORT_SYMBOL_GPL(arm_iommu_attach_device); |
4ce63fcd | 2027 | |
6fe36758 HD |
2028 | /** |
2029 | * arm_iommu_detach_device | |
2030 | * @dev: valid struct device pointer | |
2031 | * | |
2032 | * Detaches the provided device from a previously attached map. | |
2033 | * This voids the dma operations (dma_map_ops pointer) | |
2034 | */ | |
2035 | void arm_iommu_detach_device(struct device *dev) | |
2036 | { | |
2037 | struct dma_iommu_mapping *mapping; | |
2038 | ||
2039 | mapping = to_dma_iommu_mapping(dev); | |
2040 | if (!mapping) { | |
2041 | dev_warn(dev, "Not attached\n"); | |
2042 | return; | |
2043 | } | |
2044 | ||
2045 | iommu_detach_device(mapping->domain, dev); | |
2046 | kref_put(&mapping->kref, release_iommu_mapping); | |
9e4b259d | 2047 | dev->archdata.mapping = NULL; |
6fe36758 HD |
2048 | set_dma_ops(dev, NULL); |
2049 | ||
2050 | pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev)); | |
2051 | } | |
18177d12 | 2052 | EXPORT_SYMBOL_GPL(arm_iommu_detach_device); |
6fe36758 | 2053 | |
4ce63fcd | 2054 | #endif |