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Commit | Line | Data |
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1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
1da177e4 LT |
15 | #include <linux/errno.h> |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
c7909509 | 20 | #include <linux/dma-contiguous.h> |
39af22a7 | 21 | #include <linux/highmem.h> |
c7909509 | 22 | #include <linux/memblock.h> |
99d1717d | 23 | #include <linux/slab.h> |
1da177e4 | 24 | |
23759dc6 | 25 | #include <asm/memory.h> |
43377453 | 26 | #include <asm/highmem.h> |
1da177e4 | 27 | #include <asm/cacheflush.h> |
1da177e4 | 28 | #include <asm/tlbflush.h> |
37134cd5 | 29 | #include <asm/sizes.h> |
99d1717d | 30 | #include <asm/mach/arch.h> |
c7909509 MS |
31 | #include <asm/mach/map.h> |
32 | #include <asm/system_info.h> | |
33 | #include <asm/dma-contiguous.h> | |
37134cd5 | 34 | |
022ae537 RK |
35 | #include "mm.h" |
36 | ||
ab6494f0 CM |
37 | static u64 get_coherent_dma_mask(struct device *dev) |
38 | { | |
022ae537 | 39 | u64 mask = (u64)arm_dma_limit; |
ab6494f0 CM |
40 | |
41 | if (dev) { | |
42 | mask = dev->coherent_dma_mask; | |
43 | ||
44 | /* | |
45 | * Sanity check the DMA mask - it must be non-zero, and | |
46 | * must be able to be satisfied by a DMA allocation. | |
47 | */ | |
48 | if (mask == 0) { | |
49 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
50 | return 0; | |
51 | } | |
52 | ||
022ae537 | 53 | if ((~mask) & (u64)arm_dma_limit) { |
ab6494f0 CM |
54 | dev_warn(dev, "coherent DMA mask %#llx is smaller " |
55 | "than system GFP_DMA mask %#llx\n", | |
022ae537 | 56 | mask, (u64)arm_dma_limit); |
ab6494f0 CM |
57 | return 0; |
58 | } | |
59 | } | |
1da177e4 | 60 | |
ab6494f0 CM |
61 | return mask; |
62 | } | |
63 | ||
c7909509 MS |
64 | static void __dma_clear_buffer(struct page *page, size_t size) |
65 | { | |
66 | void *ptr; | |
67 | /* | |
68 | * Ensure that the allocated pages are zeroed, and that any data | |
69 | * lurking in the kernel direct-mapped region is invalidated. | |
70 | */ | |
71 | ptr = page_address(page); | |
72 | memset(ptr, 0, size); | |
73 | dmac_flush_range(ptr, ptr + size); | |
74 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
75 | } | |
76 | ||
7a9a32a9 RK |
77 | /* |
78 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
79 | * specified gfp mask. Note that 'size' must be page aligned. | |
80 | */ | |
81 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
82 | { | |
83 | unsigned long order = get_order(size); | |
84 | struct page *page, *p, *e; | |
7a9a32a9 RK |
85 | |
86 | page = alloc_pages(gfp, order); | |
87 | if (!page) | |
88 | return NULL; | |
89 | ||
90 | /* | |
91 | * Now split the huge page and free the excess pages | |
92 | */ | |
93 | split_page(page, order); | |
94 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
95 | __free_page(p); | |
96 | ||
c7909509 | 97 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
98 | |
99 | return page; | |
100 | } | |
101 | ||
102 | /* | |
103 | * Free a DMA buffer. 'size' must be page aligned. | |
104 | */ | |
105 | static void __dma_free_buffer(struct page *page, size_t size) | |
106 | { | |
107 | struct page *e = page + (size >> PAGE_SHIFT); | |
108 | ||
109 | while (page < e) { | |
110 | __free_page(page); | |
111 | page++; | |
112 | } | |
113 | } | |
114 | ||
ab6494f0 | 115 | #ifdef CONFIG_MMU |
a5e9d38b | 116 | |
99d1717d | 117 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT) |
1fdb24e9 | 118 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PMD_SHIFT) |
a5e9d38b | 119 | |
1da177e4 | 120 | /* |
37134cd5 | 121 | * These are the page tables (2MB each) covering uncached, DMA consistent allocations |
1da177e4 | 122 | */ |
99d1717d JM |
123 | static pte_t **consistent_pte; |
124 | ||
99d1717d | 125 | #define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M |
99d1717d JM |
126 | |
127 | unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE; | |
128 | ||
129 | void __init init_consistent_dma_size(unsigned long size) | |
130 | { | |
131 | unsigned long base = CONSISTENT_END - ALIGN(size, SZ_2M); | |
132 | ||
133 | BUG_ON(consistent_pte); /* Check we're called before DMA region init */ | |
134 | BUG_ON(base < VMALLOC_END); | |
135 | ||
136 | /* Grow region to accommodate specified size */ | |
137 | if (base < consistent_base) | |
138 | consistent_base = base; | |
139 | } | |
1da177e4 | 140 | |
13ccf3ad | 141 | #include "vmregion.h" |
1da177e4 | 142 | |
13ccf3ad RK |
143 | static struct arm_vmregion_head consistent_head = { |
144 | .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock), | |
1da177e4 | 145 | .vm_list = LIST_HEAD_INIT(consistent_head.vm_list), |
1da177e4 LT |
146 | .vm_end = CONSISTENT_END, |
147 | }; | |
148 | ||
1da177e4 LT |
149 | #ifdef CONFIG_HUGETLB_PAGE |
150 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
151 | #endif | |
152 | ||
88c58f3b RK |
153 | /* |
154 | * Initialise the consistent memory allocation. | |
155 | */ | |
156 | static int __init consistent_init(void) | |
157 | { | |
158 | int ret = 0; | |
159 | pgd_t *pgd; | |
516295e5 | 160 | pud_t *pud; |
88c58f3b RK |
161 | pmd_t *pmd; |
162 | pte_t *pte; | |
163 | int i = 0; | |
99d1717d | 164 | unsigned long base = consistent_base; |
53cbcbcf | 165 | unsigned long num_ptes = (CONSISTENT_END - base) >> PMD_SHIFT; |
99d1717d | 166 | |
c7909509 MS |
167 | if (cpu_architecture() >= CPU_ARCH_ARMv6) |
168 | return 0; | |
169 | ||
99d1717d JM |
170 | consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL); |
171 | if (!consistent_pte) { | |
172 | pr_err("%s: no memory\n", __func__); | |
173 | return -ENOMEM; | |
174 | } | |
175 | ||
176 | pr_debug("DMA memory: 0x%08lx - 0x%08lx:\n", base, CONSISTENT_END); | |
177 | consistent_head.vm_start = base; | |
88c58f3b RK |
178 | |
179 | do { | |
180 | pgd = pgd_offset(&init_mm, base); | |
516295e5 RK |
181 | |
182 | pud = pud_alloc(&init_mm, pgd, base); | |
183 | if (!pud) { | |
184 | printk(KERN_ERR "%s: no pud tables\n", __func__); | |
185 | ret = -ENOMEM; | |
186 | break; | |
187 | } | |
188 | ||
189 | pmd = pmd_alloc(&init_mm, pud, base); | |
88c58f3b RK |
190 | if (!pmd) { |
191 | printk(KERN_ERR "%s: no pmd tables\n", __func__); | |
192 | ret = -ENOMEM; | |
193 | break; | |
194 | } | |
195 | WARN_ON(!pmd_none(*pmd)); | |
196 | ||
197 | pte = pte_alloc_kernel(pmd, base); | |
198 | if (!pte) { | |
199 | printk(KERN_ERR "%s: no pte tables\n", __func__); | |
200 | ret = -ENOMEM; | |
201 | break; | |
202 | } | |
203 | ||
204 | consistent_pte[i++] = pte; | |
e73fc88e | 205 | base += PMD_SIZE; |
88c58f3b RK |
206 | } while (base < CONSISTENT_END); |
207 | ||
208 | return ret; | |
209 | } | |
88c58f3b RK |
210 | core_initcall(consistent_init); |
211 | ||
c7909509 MS |
212 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
213 | pgprot_t prot, struct page **ret_page); | |
214 | ||
215 | static struct arm_vmregion_head coherent_head = { | |
216 | .vm_lock = __SPIN_LOCK_UNLOCKED(&coherent_head.vm_lock), | |
217 | .vm_list = LIST_HEAD_INIT(coherent_head.vm_list), | |
218 | }; | |
219 | ||
220 | size_t coherent_pool_size = DEFAULT_CONSISTENT_DMA_SIZE / 8; | |
221 | ||
222 | static int __init early_coherent_pool(char *p) | |
223 | { | |
224 | coherent_pool_size = memparse(p, &p); | |
225 | return 0; | |
226 | } | |
227 | early_param("coherent_pool", early_coherent_pool); | |
228 | ||
229 | /* | |
230 | * Initialise the coherent pool for atomic allocations. | |
231 | */ | |
232 | static int __init coherent_init(void) | |
233 | { | |
234 | pgprot_t prot = pgprot_dmacoherent(pgprot_kernel); | |
235 | size_t size = coherent_pool_size; | |
236 | struct page *page; | |
237 | void *ptr; | |
238 | ||
239 | if (cpu_architecture() < CPU_ARCH_ARMv6) | |
240 | return 0; | |
241 | ||
242 | ptr = __alloc_from_contiguous(NULL, size, prot, &page); | |
243 | if (ptr) { | |
244 | coherent_head.vm_start = (unsigned long) ptr; | |
245 | coherent_head.vm_end = (unsigned long) ptr + size; | |
246 | printk(KERN_INFO "DMA: preallocated %u KiB pool for atomic coherent allocations\n", | |
247 | (unsigned)size / 1024); | |
248 | return 0; | |
249 | } | |
250 | printk(KERN_ERR "DMA: failed to allocate %u KiB pool for atomic coherent allocation\n", | |
251 | (unsigned)size / 1024); | |
252 | return -ENOMEM; | |
253 | } | |
254 | /* | |
255 | * CMA is activated by core_initcall, so we must be called after it. | |
256 | */ | |
257 | postcore_initcall(coherent_init); | |
258 | ||
259 | struct dma_contig_early_reserve { | |
260 | phys_addr_t base; | |
261 | unsigned long size; | |
262 | }; | |
263 | ||
264 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
265 | ||
266 | static int dma_mmu_remap_num __initdata; | |
267 | ||
268 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
269 | { | |
270 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
271 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
272 | dma_mmu_remap_num++; | |
273 | } | |
274 | ||
275 | void __init dma_contiguous_remap(void) | |
276 | { | |
277 | int i; | |
278 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
279 | phys_addr_t start = dma_mmu_remap[i].base; | |
280 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
281 | struct map_desc map; | |
282 | unsigned long addr; | |
283 | ||
284 | if (end > arm_lowmem_limit) | |
285 | end = arm_lowmem_limit; | |
286 | if (start >= end) | |
287 | return; | |
288 | ||
289 | map.pfn = __phys_to_pfn(start); | |
290 | map.virtual = __phys_to_virt(start); | |
291 | map.length = end - start; | |
292 | map.type = MT_MEMORY_DMA_READY; | |
293 | ||
294 | /* | |
295 | * Clear previous low-memory mapping | |
296 | */ | |
297 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
298 | addr += PGDIR_SIZE) | |
299 | pmd_clear(pmd_off_k(addr)); | |
300 | ||
301 | iotable_init(&map, 1); | |
302 | } | |
303 | } | |
304 | ||
1da177e4 | 305 | static void * |
45cd5290 RK |
306 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, |
307 | const void *caller) | |
1da177e4 | 308 | { |
13ccf3ad | 309 | struct arm_vmregion *c; |
5bc23d32 RK |
310 | size_t align; |
311 | int bit; | |
1da177e4 | 312 | |
99d1717d | 313 | if (!consistent_pte) { |
ebd7a845 RK |
314 | printk(KERN_ERR "%s: not initialised\n", __func__); |
315 | dump_stack(); | |
ebd7a845 RK |
316 | return NULL; |
317 | } | |
318 | ||
5bc23d32 RK |
319 | /* |
320 | * Align the virtual region allocation - maximum alignment is | |
321 | * a section size, minimum is a page size. This helps reduce | |
322 | * fragmentation of the DMA space, and also prevents allocations | |
323 | * smaller than a section from crossing a section boundary. | |
324 | */ | |
c947f69f | 325 | bit = fls(size - 1); |
5bc23d32 RK |
326 | if (bit > SECTION_SHIFT) |
327 | bit = SECTION_SHIFT; | |
328 | align = 1 << bit; | |
329 | ||
1da177e4 LT |
330 | /* |
331 | * Allocate a virtual address in the consistent mapping region. | |
332 | */ | |
5bc23d32 | 333 | c = arm_vmregion_alloc(&consistent_head, align, size, |
45cd5290 | 334 | gfp & ~(__GFP_DMA | __GFP_HIGHMEM), caller); |
1da177e4 | 335 | if (c) { |
37134cd5 | 336 | pte_t *pte; |
37134cd5 KH |
337 | int idx = CONSISTENT_PTE_INDEX(c->vm_start); |
338 | u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
1da177e4 | 339 | |
37134cd5 | 340 | pte = consistent_pte[idx] + off; |
1da177e4 LT |
341 | c->vm_pages = page; |
342 | ||
1da177e4 LT |
343 | do { |
344 | BUG_ON(!pte_none(*pte)); | |
345 | ||
ad1ae2fe | 346 | set_pte_ext(pte, mk_pte(page, prot), 0); |
1da177e4 LT |
347 | page++; |
348 | pte++; | |
37134cd5 KH |
349 | off++; |
350 | if (off >= PTRS_PER_PTE) { | |
351 | off = 0; | |
352 | pte = consistent_pte[++idx]; | |
353 | } | |
1da177e4 LT |
354 | } while (size -= PAGE_SIZE); |
355 | ||
2be23c47 RK |
356 | dsb(); |
357 | ||
1da177e4 LT |
358 | return (void *)c->vm_start; |
359 | } | |
1da177e4 LT |
360 | return NULL; |
361 | } | |
695ae0af RK |
362 | |
363 | static void __dma_free_remap(void *cpu_addr, size_t size) | |
364 | { | |
365 | struct arm_vmregion *c; | |
366 | unsigned long addr; | |
367 | pte_t *ptep; | |
368 | int idx; | |
369 | u32 off; | |
370 | ||
371 | c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr); | |
372 | if (!c) { | |
373 | printk(KERN_ERR "%s: trying to free invalid coherent area: %p\n", | |
374 | __func__, cpu_addr); | |
375 | dump_stack(); | |
376 | return; | |
377 | } | |
378 | ||
379 | if ((c->vm_end - c->vm_start) != size) { | |
380 | printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n", | |
381 | __func__, c->vm_end - c->vm_start, size); | |
382 | dump_stack(); | |
383 | size = c->vm_end - c->vm_start; | |
384 | } | |
385 | ||
386 | idx = CONSISTENT_PTE_INDEX(c->vm_start); | |
387 | off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
388 | ptep = consistent_pte[idx] + off; | |
389 | addr = c->vm_start; | |
390 | do { | |
391 | pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep); | |
695ae0af RK |
392 | |
393 | ptep++; | |
394 | addr += PAGE_SIZE; | |
395 | off++; | |
396 | if (off >= PTRS_PER_PTE) { | |
397 | off = 0; | |
398 | ptep = consistent_pte[++idx]; | |
399 | } | |
400 | ||
acaac256 RK |
401 | if (pte_none(pte) || !pte_present(pte)) |
402 | printk(KERN_CRIT "%s: bad page in kernel page table\n", | |
403 | __func__); | |
695ae0af RK |
404 | } while (size -= PAGE_SIZE); |
405 | ||
406 | flush_tlb_kernel_range(c->vm_start, c->vm_end); | |
407 | ||
408 | arm_vmregion_free(&consistent_head, c); | |
409 | } | |
410 | ||
c7909509 MS |
411 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
412 | void *data) | |
413 | { | |
414 | struct page *page = virt_to_page(addr); | |
415 | pgprot_t prot = *(pgprot_t *)data; | |
416 | ||
417 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
418 | return 0; | |
419 | } | |
420 | ||
421 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
422 | { | |
423 | unsigned long start = (unsigned long) page_address(page); | |
424 | unsigned end = start + size; | |
425 | ||
426 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
427 | dsb(); | |
428 | flush_tlb_kernel_range(start, end); | |
429 | } | |
430 | ||
431 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
432 | pgprot_t prot, struct page **ret_page, | |
433 | const void *caller) | |
434 | { | |
435 | struct page *page; | |
436 | void *ptr; | |
437 | page = __dma_alloc_buffer(dev, size, gfp); | |
438 | if (!page) | |
439 | return NULL; | |
440 | ||
441 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
442 | if (!ptr) { | |
443 | __dma_free_buffer(page, size); | |
444 | return NULL; | |
445 | } | |
446 | ||
447 | *ret_page = page; | |
448 | return ptr; | |
449 | } | |
450 | ||
451 | static void *__alloc_from_pool(struct device *dev, size_t size, | |
452 | struct page **ret_page, const void *caller) | |
453 | { | |
454 | struct arm_vmregion *c; | |
455 | size_t align; | |
456 | ||
457 | if (!coherent_head.vm_start) { | |
458 | printk(KERN_ERR "%s: coherent pool not initialised!\n", | |
459 | __func__); | |
460 | dump_stack(); | |
461 | return NULL; | |
462 | } | |
463 | ||
464 | /* | |
465 | * Align the region allocation - allocations from pool are rather | |
466 | * small, so align them to their order in pages, minimum is a page | |
467 | * size. This helps reduce fragmentation of the DMA space. | |
468 | */ | |
469 | align = PAGE_SIZE << get_order(size); | |
470 | c = arm_vmregion_alloc(&coherent_head, align, size, 0, caller); | |
471 | if (c) { | |
472 | void *ptr = (void *)c->vm_start; | |
473 | struct page *page = virt_to_page(ptr); | |
474 | *ret_page = page; | |
475 | return ptr; | |
476 | } | |
477 | return NULL; | |
478 | } | |
479 | ||
480 | static int __free_from_pool(void *cpu_addr, size_t size) | |
481 | { | |
482 | unsigned long start = (unsigned long)cpu_addr; | |
483 | unsigned long end = start + size; | |
484 | struct arm_vmregion *c; | |
485 | ||
486 | if (start < coherent_head.vm_start || end > coherent_head.vm_end) | |
487 | return 0; | |
488 | ||
489 | c = arm_vmregion_find_remove(&coherent_head, (unsigned long)start); | |
490 | ||
491 | if ((c->vm_end - c->vm_start) != size) { | |
492 | printk(KERN_ERR "%s: freeing wrong coherent size (%ld != %d)\n", | |
493 | __func__, c->vm_end - c->vm_start, size); | |
494 | dump_stack(); | |
495 | size = c->vm_end - c->vm_start; | |
496 | } | |
497 | ||
498 | arm_vmregion_free(&coherent_head, c); | |
499 | return 1; | |
500 | } | |
501 | ||
502 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
503 | pgprot_t prot, struct page **ret_page) | |
504 | { | |
505 | unsigned long order = get_order(size); | |
506 | size_t count = size >> PAGE_SHIFT; | |
507 | struct page *page; | |
508 | ||
509 | page = dma_alloc_from_contiguous(dev, count, order); | |
510 | if (!page) | |
511 | return NULL; | |
512 | ||
513 | __dma_clear_buffer(page, size); | |
514 | __dma_remap(page, size, prot); | |
515 | ||
516 | *ret_page = page; | |
517 | return page_address(page); | |
518 | } | |
519 | ||
520 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
521 | size_t size) | |
522 | { | |
523 | __dma_remap(page, size, pgprot_kernel); | |
524 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); | |
525 | } | |
526 | ||
527 | #define nommu() 0 | |
528 | ||
ab6494f0 | 529 | #else /* !CONFIG_MMU */ |
695ae0af | 530 | |
c7909509 MS |
531 | #define nommu() 1 |
532 | ||
533 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL | |
534 | #define __alloc_from_pool(dev, size, ret_page, c) NULL | |
535 | #define __alloc_from_contiguous(dev, size, prot, ret) NULL | |
536 | #define __free_from_pool(cpu_addr, size) 0 | |
537 | #define __free_from_contiguous(dev, page, size) do { } while (0) | |
538 | #define __dma_free_remap(cpu_addr, size) do { } while (0) | |
31ebf944 RK |
539 | |
540 | #endif /* CONFIG_MMU */ | |
541 | ||
c7909509 MS |
542 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
543 | struct page **ret_page) | |
ab6494f0 | 544 | { |
c7909509 MS |
545 | struct page *page; |
546 | page = __dma_alloc_buffer(dev, size, gfp); | |
547 | if (!page) | |
548 | return NULL; | |
549 | ||
550 | *ret_page = page; | |
551 | return page_address(page); | |
552 | } | |
553 | ||
554 | ||
555 | ||
556 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
557 | gfp_t gfp, pgprot_t prot, const void *caller) | |
558 | { | |
559 | u64 mask = get_coherent_dma_mask(dev); | |
04da5694 | 560 | struct page *page; |
31ebf944 | 561 | void *addr; |
ab6494f0 | 562 | |
c7909509 MS |
563 | #ifdef CONFIG_DMA_API_DEBUG |
564 | u64 limit = (mask + 1) & ~mask; | |
565 | if (limit && size >= limit) { | |
566 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
567 | size, mask); | |
568 | return NULL; | |
569 | } | |
570 | #endif | |
571 | ||
572 | if (!mask) | |
573 | return NULL; | |
574 | ||
575 | if (mask < 0xffffffffULL) | |
576 | gfp |= GFP_DMA; | |
577 | ||
ea2e7057 SB |
578 | /* |
579 | * Following is a work-around (a.k.a. hack) to prevent pages | |
580 | * with __GFP_COMP being passed to split_page() which cannot | |
581 | * handle them. The real problem is that this flag probably | |
582 | * should be 0 on ARM as it is not supported on this | |
583 | * platform; see CONFIG_HUGETLBFS. | |
584 | */ | |
585 | gfp &= ~(__GFP_COMP); | |
586 | ||
04da5694 RK |
587 | *handle = ~0; |
588 | size = PAGE_ALIGN(size); | |
ab6494f0 | 589 | |
c7909509 MS |
590 | if (arch_is_coherent() || nommu()) |
591 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
592 | else if (cpu_architecture() < CPU_ARCH_ARMv6) | |
593 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller); | |
594 | else if (gfp & GFP_ATOMIC) | |
595 | addr = __alloc_from_pool(dev, size, &page, caller); | |
31ebf944 | 596 | else |
c7909509 | 597 | addr = __alloc_from_contiguous(dev, size, prot, &page); |
695ae0af | 598 | |
31ebf944 | 599 | if (addr) |
9eedd963 | 600 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
695ae0af | 601 | |
31ebf944 RK |
602 | return addr; |
603 | } | |
1da177e4 LT |
604 | |
605 | /* | |
606 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
607 | * virtual and bus address for that space. | |
608 | */ | |
c7909509 MS |
609 | void *dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *handle, |
610 | gfp_t gfp) | |
1da177e4 | 611 | { |
1fe53268 DES |
612 | void *memory; |
613 | ||
614 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
615 | return memory; | |
616 | ||
1da177e4 | 617 | return __dma_alloc(dev, size, handle, gfp, |
45cd5290 RK |
618 | pgprot_dmacoherent(pgprot_kernel), |
619 | __builtin_return_address(0)); | |
1da177e4 LT |
620 | } |
621 | EXPORT_SYMBOL(dma_alloc_coherent); | |
622 | ||
623 | /* | |
624 | * Allocate a writecombining region, in much the same way as | |
625 | * dma_alloc_coherent above. | |
626 | */ | |
627 | void * | |
f9e3214a | 628 | dma_alloc_writecombine(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp) |
1da177e4 LT |
629 | { |
630 | return __dma_alloc(dev, size, handle, gfp, | |
45cd5290 RK |
631 | pgprot_writecombine(pgprot_kernel), |
632 | __builtin_return_address(0)); | |
1da177e4 LT |
633 | } |
634 | EXPORT_SYMBOL(dma_alloc_writecombine); | |
635 | ||
636 | static int dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
637 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
638 | { | |
ab6494f0 CM |
639 | int ret = -ENXIO; |
640 | #ifdef CONFIG_MMU | |
c7909509 MS |
641 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
642 | ret = remap_pfn_range(vma, vma->vm_start, | |
643 | pfn + vma->vm_pgoff, | |
644 | vma->vm_end - vma->vm_start, | |
645 | vma->vm_page_prot); | |
ab6494f0 | 646 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
647 | |
648 | return ret; | |
649 | } | |
650 | ||
651 | int dma_mmap_coherent(struct device *dev, struct vm_area_struct *vma, | |
652 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
653 | { | |
26a26d32 | 654 | vma->vm_page_prot = pgprot_dmacoherent(vma->vm_page_prot); |
1da177e4 LT |
655 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); |
656 | } | |
657 | EXPORT_SYMBOL(dma_mmap_coherent); | |
658 | ||
659 | int dma_mmap_writecombine(struct device *dev, struct vm_area_struct *vma, | |
660 | void *cpu_addr, dma_addr_t dma_addr, size_t size) | |
661 | { | |
662 | vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot); | |
663 | return dma_mmap(dev, vma, cpu_addr, dma_addr, size); | |
664 | } | |
665 | EXPORT_SYMBOL(dma_mmap_writecombine); | |
666 | ||
c7909509 | 667 | |
1da177e4 | 668 | /* |
c7909509 | 669 | * Free a buffer as defined by the above mapping. |
1da177e4 LT |
670 | */ |
671 | void dma_free_coherent(struct device *dev, size_t size, void *cpu_addr, dma_addr_t handle) | |
672 | { | |
c7909509 | 673 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
5edf71ae | 674 | |
1fe53268 DES |
675 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
676 | return; | |
677 | ||
3e82d012 RK |
678 | size = PAGE_ALIGN(size); |
679 | ||
c7909509 MS |
680 | if (arch_is_coherent() || nommu()) { |
681 | __dma_free_buffer(page, size); | |
682 | } else if (cpu_architecture() < CPU_ARCH_ARMv6) { | |
695ae0af | 683 | __dma_free_remap(cpu_addr, size); |
c7909509 MS |
684 | __dma_free_buffer(page, size); |
685 | } else { | |
686 | if (__free_from_pool(cpu_addr, size)) | |
687 | return; | |
688 | /* | |
689 | * Non-atomic allocations cannot be freed with IRQs disabled | |
690 | */ | |
691 | WARN_ON(irqs_disabled()); | |
692 | __free_from_contiguous(dev, page, size); | |
693 | } | |
1da177e4 LT |
694 | } |
695 | EXPORT_SYMBOL(dma_free_coherent); | |
696 | ||
1da177e4 LT |
697 | /* |
698 | * Make an area consistent for devices. | |
105ef9a0 DW |
699 | * Note: Drivers should NOT use this function directly, as it will break |
700 | * platforms with CONFIG_DMABOUNCE. | |
701 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
1da177e4 | 702 | */ |
4ea0d737 RK |
703 | void ___dma_single_cpu_to_dev(const void *kaddr, size_t size, |
704 | enum dma_data_direction dir) | |
705 | { | |
2ffe2da3 RK |
706 | unsigned long paddr; |
707 | ||
a9c9147e RK |
708 | BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1)); |
709 | ||
710 | dmac_map_area(kaddr, size, dir); | |
2ffe2da3 RK |
711 | |
712 | paddr = __pa(kaddr); | |
713 | if (dir == DMA_FROM_DEVICE) { | |
714 | outer_inv_range(paddr, paddr + size); | |
715 | } else { | |
716 | outer_clean_range(paddr, paddr + size); | |
717 | } | |
718 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 RK |
719 | } |
720 | EXPORT_SYMBOL(___dma_single_cpu_to_dev); | |
721 | ||
722 | void ___dma_single_dev_to_cpu(const void *kaddr, size_t size, | |
723 | enum dma_data_direction dir) | |
724 | { | |
a9c9147e RK |
725 | BUG_ON(!virt_addr_valid(kaddr) || !virt_addr_valid(kaddr + size - 1)); |
726 | ||
2ffe2da3 RK |
727 | /* FIXME: non-speculating: not required */ |
728 | /* don't bother invalidating if DMA to device */ | |
729 | if (dir != DMA_TO_DEVICE) { | |
730 | unsigned long paddr = __pa(kaddr); | |
731 | outer_inv_range(paddr, paddr + size); | |
732 | } | |
733 | ||
a9c9147e | 734 | dmac_unmap_area(kaddr, size, dir); |
4ea0d737 RK |
735 | } |
736 | EXPORT_SYMBOL(___dma_single_dev_to_cpu); | |
afd1a321 | 737 | |
4ea0d737 | 738 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
739 | size_t size, enum dma_data_direction dir, |
740 | void (*op)(const void *, size_t, int)) | |
43377453 NP |
741 | { |
742 | /* | |
743 | * A single sg entry may refer to multiple physically contiguous | |
744 | * pages. But we still need to process highmem pages individually. | |
745 | * If highmem is not configured then the bulk of this loop gets | |
746 | * optimized out. | |
747 | */ | |
748 | size_t left = size; | |
749 | do { | |
750 | size_t len = left; | |
93f1d629 RK |
751 | void *vaddr; |
752 | ||
753 | if (PageHighMem(page)) { | |
754 | if (len + offset > PAGE_SIZE) { | |
755 | if (offset >= PAGE_SIZE) { | |
756 | page += offset / PAGE_SIZE; | |
757 | offset %= PAGE_SIZE; | |
758 | } | |
759 | len = PAGE_SIZE - offset; | |
760 | } | |
761 | vaddr = kmap_high_get(page); | |
762 | if (vaddr) { | |
763 | vaddr += offset; | |
a9c9147e | 764 | op(vaddr, len, dir); |
93f1d629 | 765 | kunmap_high(page); |
7e5a69e8 | 766 | } else if (cache_is_vipt()) { |
39af22a7 NP |
767 | /* unmapped pages might still be cached */ |
768 | vaddr = kmap_atomic(page); | |
7e5a69e8 | 769 | op(vaddr + offset, len, dir); |
39af22a7 | 770 | kunmap_atomic(vaddr); |
43377453 | 771 | } |
93f1d629 RK |
772 | } else { |
773 | vaddr = page_address(page) + offset; | |
a9c9147e | 774 | op(vaddr, len, dir); |
43377453 | 775 | } |
43377453 NP |
776 | offset = 0; |
777 | page++; | |
778 | left -= len; | |
779 | } while (left); | |
780 | } | |
4ea0d737 RK |
781 | |
782 | void ___dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
783 | size_t size, enum dma_data_direction dir) | |
784 | { | |
65af191a | 785 | unsigned long paddr; |
65af191a | 786 | |
a9c9147e | 787 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
788 | |
789 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
790 | if (dir == DMA_FROM_DEVICE) { |
791 | outer_inv_range(paddr, paddr + size); | |
792 | } else { | |
793 | outer_clean_range(paddr, paddr + size); | |
794 | } | |
795 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 RK |
796 | } |
797 | EXPORT_SYMBOL(___dma_page_cpu_to_dev); | |
798 | ||
799 | void ___dma_page_dev_to_cpu(struct page *page, unsigned long off, | |
800 | size_t size, enum dma_data_direction dir) | |
801 | { | |
2ffe2da3 RK |
802 | unsigned long paddr = page_to_phys(page) + off; |
803 | ||
804 | /* FIXME: non-speculating: not required */ | |
805 | /* don't bother invalidating if DMA to device */ | |
806 | if (dir != DMA_TO_DEVICE) | |
807 | outer_inv_range(paddr, paddr + size); | |
808 | ||
a9c9147e | 809 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
c0177800 CM |
810 | |
811 | /* | |
812 | * Mark the D-cache clean for this page to avoid extra flushing. | |
813 | */ | |
814 | if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE) | |
815 | set_bit(PG_dcache_clean, &page->flags); | |
4ea0d737 RK |
816 | } |
817 | EXPORT_SYMBOL(___dma_page_dev_to_cpu); | |
43377453 | 818 | |
afd1a321 RK |
819 | /** |
820 | * dma_map_sg - map a set of SG buffers for streaming mode DMA | |
821 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
822 | * @sg: list of buffers | |
823 | * @nents: number of buffers to map | |
824 | * @dir: DMA transfer direction | |
825 | * | |
826 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
827 | * This is the scatter-gather version of the dma_map_single interface. | |
828 | * Here the scatter gather list elements are each tagged with the | |
829 | * appropriate dma address and length. They are obtained via | |
830 | * sg_dma_{address,length}. | |
831 | * | |
832 | * Device ownership issues as mentioned for dma_map_single are the same | |
833 | * here. | |
834 | */ | |
835 | int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
836 | enum dma_data_direction dir) | |
837 | { | |
838 | struct scatterlist *s; | |
01135d92 | 839 | int i, j; |
afd1a321 | 840 | |
24056f52 RK |
841 | BUG_ON(!valid_dma_direction(dir)); |
842 | ||
afd1a321 | 843 | for_each_sg(sg, s, nents, i) { |
24056f52 | 844 | s->dma_address = __dma_map_page(dev, sg_page(s), s->offset, |
01135d92 RK |
845 | s->length, dir); |
846 | if (dma_mapping_error(dev, s->dma_address)) | |
847 | goto bad_mapping; | |
afd1a321 | 848 | } |
24056f52 | 849 | debug_dma_map_sg(dev, sg, nents, nents, dir); |
afd1a321 | 850 | return nents; |
01135d92 RK |
851 | |
852 | bad_mapping: | |
853 | for_each_sg(sg, s, i, j) | |
24056f52 | 854 | __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); |
01135d92 | 855 | return 0; |
afd1a321 RK |
856 | } |
857 | EXPORT_SYMBOL(dma_map_sg); | |
858 | ||
859 | /** | |
860 | * dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
861 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
862 | * @sg: list of buffers | |
0adfca6f | 863 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
864 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
865 | * | |
866 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
867 | * rules concerning calls here are the same as for dma_unmap_single(). | |
868 | */ | |
869 | void dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
870 | enum dma_data_direction dir) | |
871 | { | |
01135d92 RK |
872 | struct scatterlist *s; |
873 | int i; | |
874 | ||
24056f52 RK |
875 | debug_dma_unmap_sg(dev, sg, nents, dir); |
876 | ||
01135d92 | 877 | for_each_sg(sg, s, nents, i) |
24056f52 | 878 | __dma_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir); |
afd1a321 RK |
879 | } |
880 | EXPORT_SYMBOL(dma_unmap_sg); | |
881 | ||
882 | /** | |
883 | * dma_sync_sg_for_cpu | |
884 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
885 | * @sg: list of buffers | |
886 | * @nents: number of buffers to map (returned from dma_map_sg) | |
887 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
888 | */ | |
889 | void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
890 | int nents, enum dma_data_direction dir) | |
891 | { | |
892 | struct scatterlist *s; | |
893 | int i; | |
894 | ||
895 | for_each_sg(sg, s, nents, i) { | |
18eabe23 RK |
896 | if (!dmabounce_sync_for_cpu(dev, sg_dma_address(s), 0, |
897 | sg_dma_len(s), dir)) | |
898 | continue; | |
899 | ||
900 | __dma_page_dev_to_cpu(sg_page(s), s->offset, | |
901 | s->length, dir); | |
afd1a321 | 902 | } |
24056f52 RK |
903 | |
904 | debug_dma_sync_sg_for_cpu(dev, sg, nents, dir); | |
afd1a321 RK |
905 | } |
906 | EXPORT_SYMBOL(dma_sync_sg_for_cpu); | |
907 | ||
908 | /** | |
909 | * dma_sync_sg_for_device | |
910 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
911 | * @sg: list of buffers | |
912 | * @nents: number of buffers to map (returned from dma_map_sg) | |
913 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
914 | */ | |
915 | void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
916 | int nents, enum dma_data_direction dir) | |
917 | { | |
918 | struct scatterlist *s; | |
919 | int i; | |
920 | ||
921 | for_each_sg(sg, s, nents, i) { | |
2638b4db RK |
922 | if (!dmabounce_sync_for_device(dev, sg_dma_address(s), 0, |
923 | sg_dma_len(s), dir)) | |
924 | continue; | |
925 | ||
18eabe23 RK |
926 | __dma_page_cpu_to_dev(sg_page(s), s->offset, |
927 | s->length, dir); | |
afd1a321 | 928 | } |
24056f52 RK |
929 | |
930 | debug_dma_sync_sg_for_device(dev, sg, nents, dir); | |
afd1a321 RK |
931 | } |
932 | EXPORT_SYMBOL(dma_sync_sg_for_device); | |
24056f52 | 933 | |
022ae537 RK |
934 | /* |
935 | * Return whether the given device DMA address mask can be supported | |
936 | * properly. For example, if your device can only drive the low 24-bits | |
937 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
938 | * to this function. | |
939 | */ | |
940 | int dma_supported(struct device *dev, u64 mask) | |
941 | { | |
942 | if (mask < (u64)arm_dma_limit) | |
943 | return 0; | |
944 | return 1; | |
945 | } | |
946 | EXPORT_SYMBOL(dma_supported); | |
947 | ||
948 | int dma_set_mask(struct device *dev, u64 dma_mask) | |
949 | { | |
950 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
951 | return -EIO; | |
952 | ||
953 | #ifndef CONFIG_DMABOUNCE | |
954 | *dev->dma_mask = dma_mask; | |
955 | #endif | |
956 | ||
957 | return 0; | |
958 | } | |
959 | EXPORT_SYMBOL(dma_set_mask); | |
960 | ||
24056f52 RK |
961 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
962 | ||
963 | static int __init dma_debug_do_init(void) | |
964 | { | |
45cd5290 RK |
965 | #ifdef CONFIG_MMU |
966 | arm_vmregion_create_proc("dma-mappings", &consistent_head); | |
967 | #endif | |
24056f52 RK |
968 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); |
969 | return 0; | |
970 | } | |
971 | fs_initcall(dma_debug_do_init); |