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Commit | Line | Data |
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1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
11a5aa32 | 12 | #include <linux/bootmem.h> |
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/mm.h> | |
36d0fd21 | 15 | #include <linux/genalloc.h> |
5a0e3ad6 | 16 | #include <linux/gfp.h> |
1da177e4 LT |
17 | #include <linux/errno.h> |
18 | #include <linux/list.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/dma-mapping.h> | |
c7909509 | 22 | #include <linux/dma-contiguous.h> |
39af22a7 | 23 | #include <linux/highmem.h> |
c7909509 | 24 | #include <linux/memblock.h> |
99d1717d | 25 | #include <linux/slab.h> |
4ce63fcd | 26 | #include <linux/iommu.h> |
e9da6e99 | 27 | #include <linux/io.h> |
4ce63fcd | 28 | #include <linux/vmalloc.h> |
158e8bfe | 29 | #include <linux/sizes.h> |
a254129e | 30 | #include <linux/cma.h> |
1da177e4 | 31 | |
23759dc6 | 32 | #include <asm/memory.h> |
43377453 | 33 | #include <asm/highmem.h> |
1da177e4 | 34 | #include <asm/cacheflush.h> |
1da177e4 | 35 | #include <asm/tlbflush.h> |
99d1717d | 36 | #include <asm/mach/arch.h> |
4ce63fcd | 37 | #include <asm/dma-iommu.h> |
c7909509 MS |
38 | #include <asm/mach/map.h> |
39 | #include <asm/system_info.h> | |
40 | #include <asm/dma-contiguous.h> | |
37134cd5 | 41 | |
1234e3fd | 42 | #include "dma.h" |
022ae537 RK |
43 | #include "mm.h" |
44 | ||
b4268676 RV |
45 | struct arm_dma_alloc_args { |
46 | struct device *dev; | |
47 | size_t size; | |
48 | gfp_t gfp; | |
49 | pgprot_t prot; | |
50 | const void *caller; | |
51 | bool want_vaddr; | |
f1270896 | 52 | int coherent_flag; |
b4268676 RV |
53 | }; |
54 | ||
55 | struct arm_dma_free_args { | |
56 | struct device *dev; | |
57 | size_t size; | |
58 | void *cpu_addr; | |
59 | struct page *page; | |
60 | bool want_vaddr; | |
61 | }; | |
62 | ||
f1270896 GC |
63 | #define NORMAL 0 |
64 | #define COHERENT 1 | |
65 | ||
b4268676 RV |
66 | struct arm_dma_allocator { |
67 | void *(*alloc)(struct arm_dma_alloc_args *args, | |
68 | struct page **ret_page); | |
69 | void (*free)(struct arm_dma_free_args *args); | |
70 | }; | |
71 | ||
19e6e5e5 RV |
72 | struct arm_dma_buffer { |
73 | struct list_head list; | |
74 | void *virt; | |
b4268676 | 75 | struct arm_dma_allocator *allocator; |
19e6e5e5 RV |
76 | }; |
77 | ||
78 | static LIST_HEAD(arm_dma_bufs); | |
79 | static DEFINE_SPINLOCK(arm_dma_bufs_lock); | |
80 | ||
81 | static struct arm_dma_buffer *arm_dma_buffer_find(void *virt) | |
82 | { | |
83 | struct arm_dma_buffer *buf, *found = NULL; | |
84 | unsigned long flags; | |
85 | ||
86 | spin_lock_irqsave(&arm_dma_bufs_lock, flags); | |
87 | list_for_each_entry(buf, &arm_dma_bufs, list) { | |
88 | if (buf->virt == virt) { | |
89 | list_del(&buf->list); | |
90 | found = buf; | |
91 | break; | |
92 | } | |
93 | } | |
94 | spin_unlock_irqrestore(&arm_dma_bufs_lock, flags); | |
95 | return found; | |
96 | } | |
97 | ||
15237e1f MS |
98 | /* |
99 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
100 | * is either exclusively owned by the CPU (and therefore may be accessed | |
101 | * by it) or exclusively owned by the DMA device. These helper functions | |
102 | * represent the transitions between these two ownership states. | |
103 | * | |
104 | * Note, however, that on later ARMs, this notion does not work due to | |
105 | * speculative prefetches. We model our approach on the assumption that | |
106 | * the CPU does do speculative prefetches, which means we clean caches | |
107 | * before transfers and delay cache invalidation until transfer completion. | |
108 | * | |
15237e1f | 109 | */ |
51fde349 | 110 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 111 | size_t, enum dma_data_direction); |
51fde349 | 112 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
113 | size_t, enum dma_data_direction); |
114 | ||
2dc6a016 MS |
115 | /** |
116 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
117 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
118 | * @page: page that buffer resides in | |
119 | * @offset: offset into page for start of buffer | |
120 | * @size: size of buffer to map | |
121 | * @dir: DMA transfer direction | |
122 | * | |
123 | * Ensure that any data held in the cache is appropriately discarded | |
124 | * or written back. | |
125 | * | |
126 | * The device owns this memory once this call has completed. The CPU | |
127 | * can regain ownership by calling dma_unmap_page(). | |
128 | */ | |
51fde349 | 129 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 | 130 | unsigned long offset, size_t size, enum dma_data_direction dir, |
00085f1e | 131 | unsigned long attrs) |
2dc6a016 | 132 | { |
00085f1e | 133 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
51fde349 MS |
134 | __dma_page_cpu_to_dev(page, offset, size, dir); |
135 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
136 | } |
137 | ||
dd37e940 RH |
138 | static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page, |
139 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
00085f1e | 140 | unsigned long attrs) |
dd37e940 RH |
141 | { |
142 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
143 | } | |
144 | ||
2dc6a016 MS |
145 | /** |
146 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
147 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
148 | * @handle: DMA address of buffer | |
149 | * @size: size of buffer (same as passed to dma_map_page) | |
150 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
151 | * | |
152 | * Unmap a page streaming mode DMA translation. The handle and size | |
153 | * must match what was provided in the previous dma_map_page() call. | |
154 | * All other usages are undefined. | |
155 | * | |
156 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
157 | * whatever the device wrote there. | |
158 | */ | |
51fde349 | 159 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
00085f1e | 160 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
2dc6a016 | 161 | { |
00085f1e | 162 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
51fde349 MS |
163 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
164 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
165 | } |
166 | ||
51fde349 | 167 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
168 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
169 | { | |
170 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
171 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 172 | __dma_page_dev_to_cpu(page, offset, size, dir); |
2dc6a016 MS |
173 | } |
174 | ||
51fde349 | 175 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
176 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
177 | { | |
178 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
179 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 180 | __dma_page_cpu_to_dev(page, offset, size, dir); |
2dc6a016 MS |
181 | } |
182 | ||
5299709d | 183 | const struct dma_map_ops arm_dma_ops = { |
f99d6034 MS |
184 | .alloc = arm_dma_alloc, |
185 | .free = arm_dma_free, | |
186 | .mmap = arm_dma_mmap, | |
dc2832e1 | 187 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
188 | .map_page = arm_dma_map_page, |
189 | .unmap_page = arm_dma_unmap_page, | |
190 | .map_sg = arm_dma_map_sg, | |
191 | .unmap_sg = arm_dma_unmap_sg, | |
192 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
193 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
194 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
195 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
2dc6a016 MS |
196 | }; |
197 | EXPORT_SYMBOL(arm_dma_ops); | |
198 | ||
dd37e940 | 199 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, |
00085f1e | 200 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs); |
dd37e940 | 201 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 202 | dma_addr_t handle, unsigned long attrs); |
55af8a91 ML |
203 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
204 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
00085f1e | 205 | unsigned long attrs); |
dd37e940 | 206 | |
5299709d | 207 | const struct dma_map_ops arm_coherent_dma_ops = { |
dd37e940 RH |
208 | .alloc = arm_coherent_dma_alloc, |
209 | .free = arm_coherent_dma_free, | |
55af8a91 | 210 | .mmap = arm_coherent_dma_mmap, |
dd37e940 RH |
211 | .get_sgtable = arm_dma_get_sgtable, |
212 | .map_page = arm_coherent_dma_map_page, | |
213 | .map_sg = arm_dma_map_sg, | |
dd37e940 RH |
214 | }; |
215 | EXPORT_SYMBOL(arm_coherent_dma_ops); | |
216 | ||
9f28cde0 RK |
217 | static int __dma_supported(struct device *dev, u64 mask, bool warn) |
218 | { | |
219 | unsigned long max_dma_pfn; | |
220 | ||
221 | /* | |
222 | * If the mask allows for more memory than we can address, | |
223 | * and we actually have that much memory, then we must | |
224 | * indicate that DMA to this device is not supported. | |
225 | */ | |
226 | if (sizeof(mask) != sizeof(dma_addr_t) && | |
227 | mask > (dma_addr_t)~0 && | |
8bf1268f | 228 | dma_to_pfn(dev, ~0) < max_pfn - 1) { |
9f28cde0 RK |
229 | if (warn) { |
230 | dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", | |
231 | mask); | |
232 | dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n"); | |
233 | } | |
234 | return 0; | |
235 | } | |
236 | ||
237 | max_dma_pfn = min(max_pfn, arm_dma_pfn_limit); | |
238 | ||
239 | /* | |
240 | * Translate the device's DMA mask to a PFN limit. This | |
241 | * PFN number includes the page which we can DMA to. | |
242 | */ | |
243 | if (dma_to_pfn(dev, mask) < max_dma_pfn) { | |
244 | if (warn) | |
245 | dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", | |
246 | mask, | |
247 | dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, | |
248 | max_dma_pfn + 1); | |
249 | return 0; | |
250 | } | |
251 | ||
252 | return 1; | |
253 | } | |
254 | ||
ab6494f0 CM |
255 | static u64 get_coherent_dma_mask(struct device *dev) |
256 | { | |
4dcfa600 | 257 | u64 mask = (u64)DMA_BIT_MASK(32); |
ab6494f0 CM |
258 | |
259 | if (dev) { | |
260 | mask = dev->coherent_dma_mask; | |
261 | ||
262 | /* | |
263 | * Sanity check the DMA mask - it must be non-zero, and | |
264 | * must be able to be satisfied by a DMA allocation. | |
265 | */ | |
266 | if (mask == 0) { | |
267 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
268 | return 0; | |
269 | } | |
270 | ||
9f28cde0 | 271 | if (!__dma_supported(dev, mask, true)) |
ab6494f0 | 272 | return 0; |
ab6494f0 | 273 | } |
1da177e4 | 274 | |
ab6494f0 CM |
275 | return mask; |
276 | } | |
277 | ||
f1270896 | 278 | static void __dma_clear_buffer(struct page *page, size_t size, int coherent_flag) |
c7909509 | 279 | { |
c7909509 MS |
280 | /* |
281 | * Ensure that the allocated pages are zeroed, and that any data | |
282 | * lurking in the kernel direct-mapped region is invalidated. | |
283 | */ | |
9848e48f MS |
284 | if (PageHighMem(page)) { |
285 | phys_addr_t base = __pfn_to_phys(page_to_pfn(page)); | |
286 | phys_addr_t end = base + size; | |
287 | while (size > 0) { | |
288 | void *ptr = kmap_atomic(page); | |
289 | memset(ptr, 0, PAGE_SIZE); | |
f1270896 GC |
290 | if (coherent_flag != COHERENT) |
291 | dmac_flush_range(ptr, ptr + PAGE_SIZE); | |
9848e48f MS |
292 | kunmap_atomic(ptr); |
293 | page++; | |
294 | size -= PAGE_SIZE; | |
295 | } | |
f1270896 GC |
296 | if (coherent_flag != COHERENT) |
297 | outer_flush_range(base, end); | |
9848e48f MS |
298 | } else { |
299 | void *ptr = page_address(page); | |
4ce63fcd | 300 | memset(ptr, 0, size); |
f1270896 GC |
301 | if (coherent_flag != COHERENT) { |
302 | dmac_flush_range(ptr, ptr + size); | |
303 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
304 | } | |
4ce63fcd | 305 | } |
c7909509 MS |
306 | } |
307 | ||
7a9a32a9 RK |
308 | /* |
309 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
310 | * specified gfp mask. Note that 'size' must be page aligned. | |
311 | */ | |
f1270896 GC |
312 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, |
313 | gfp_t gfp, int coherent_flag) | |
7a9a32a9 RK |
314 | { |
315 | unsigned long order = get_order(size); | |
316 | struct page *page, *p, *e; | |
7a9a32a9 RK |
317 | |
318 | page = alloc_pages(gfp, order); | |
319 | if (!page) | |
320 | return NULL; | |
321 | ||
322 | /* | |
323 | * Now split the huge page and free the excess pages | |
324 | */ | |
325 | split_page(page, order); | |
326 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
327 | __free_page(p); | |
328 | ||
f1270896 | 329 | __dma_clear_buffer(page, size, coherent_flag); |
7a9a32a9 RK |
330 | |
331 | return page; | |
332 | } | |
333 | ||
334 | /* | |
335 | * Free a DMA buffer. 'size' must be page aligned. | |
336 | */ | |
337 | static void __dma_free_buffer(struct page *page, size_t size) | |
338 | { | |
339 | struct page *e = page + (size >> PAGE_SHIFT); | |
340 | ||
341 | while (page < e) { | |
342 | __free_page(page); | |
343 | page++; | |
344 | } | |
345 | } | |
346 | ||
ab6494f0 | 347 | #ifdef CONFIG_MMU |
a5e9d38b | 348 | |
e9da6e99 | 349 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
9848e48f | 350 | pgprot_t prot, struct page **ret_page, |
f1270896 | 351 | const void *caller, bool want_vaddr, |
712c604d | 352 | int coherent_flag, gfp_t gfp); |
99d1717d | 353 | |
e9da6e99 MS |
354 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
355 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 356 | const void *caller, bool want_vaddr); |
99d1717d | 357 | |
e9da6e99 MS |
358 | static void * |
359 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
360 | const void *caller) | |
99d1717d | 361 | { |
e9da6e99 MS |
362 | /* |
363 | * DMA allocation can be mapped to user space, so lets | |
364 | * set VM_USERMAP flags too. | |
365 | */ | |
513510dd LA |
366 | return dma_common_contiguous_remap(page, size, |
367 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
368 | prot, caller); | |
99d1717d | 369 | } |
1da177e4 | 370 | |
e9da6e99 | 371 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 372 | { |
513510dd LA |
373 | dma_common_free_remap(cpu_addr, size, |
374 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
88c58f3b | 375 | } |
88c58f3b | 376 | |
6e5267aa | 377 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
36d0fd21 | 378 | static struct gen_pool *atomic_pool; |
6e5267aa | 379 | |
36d0fd21 | 380 | static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE; |
c7909509 MS |
381 | |
382 | static int __init early_coherent_pool(char *p) | |
383 | { | |
36d0fd21 | 384 | atomic_pool_size = memparse(p, &p); |
c7909509 MS |
385 | return 0; |
386 | } | |
387 | early_param("coherent_pool", early_coherent_pool); | |
388 | ||
6e5267aa MS |
389 | void __init init_dma_coherent_pool_size(unsigned long size) |
390 | { | |
391 | /* | |
392 | * Catch any attempt to set the pool size too late. | |
393 | */ | |
36d0fd21 | 394 | BUG_ON(atomic_pool); |
6e5267aa MS |
395 | |
396 | /* | |
397 | * Set architecture specific coherent pool size only if | |
398 | * it has not been changed by kernel command line parameter. | |
399 | */ | |
36d0fd21 LA |
400 | if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE) |
401 | atomic_pool_size = size; | |
6e5267aa MS |
402 | } |
403 | ||
c7909509 MS |
404 | /* |
405 | * Initialise the coherent pool for atomic allocations. | |
406 | */ | |
e9da6e99 | 407 | static int __init atomic_pool_init(void) |
c7909509 | 408 | { |
71b55663 | 409 | pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); |
9d1400cf | 410 | gfp_t gfp = GFP_KERNEL | GFP_DMA; |
c7909509 MS |
411 | struct page *page; |
412 | void *ptr; | |
c7909509 | 413 | |
36d0fd21 LA |
414 | atomic_pool = gen_pool_create(PAGE_SHIFT, -1); |
415 | if (!atomic_pool) | |
416 | goto out; | |
f1270896 GC |
417 | /* |
418 | * The atomic pool is only used for non-coherent allocations | |
419 | * so we must pass NORMAL for coherent_flag. | |
420 | */ | |
e464ef16 | 421 | if (dev_get_cma_area(NULL)) |
36d0fd21 | 422 | ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot, |
712c604d LS |
423 | &page, atomic_pool_init, true, NORMAL, |
424 | GFP_KERNEL); | |
e9da6e99 | 425 | else |
36d0fd21 | 426 | ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot, |
6e8266e3 | 427 | &page, atomic_pool_init, true); |
c7909509 | 428 | if (ptr) { |
36d0fd21 LA |
429 | int ret; |
430 | ||
431 | ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr, | |
432 | page_to_phys(page), | |
433 | atomic_pool_size, -1); | |
434 | if (ret) | |
435 | goto destroy_genpool; | |
436 | ||
437 | gen_pool_set_algo(atomic_pool, | |
438 | gen_pool_first_fit_order_align, | |
439 | (void *)PAGE_SHIFT); | |
bf31c5e0 | 440 | pr_info("DMA: preallocated %zu KiB pool for atomic coherent allocations\n", |
36d0fd21 | 441 | atomic_pool_size / 1024); |
c7909509 MS |
442 | return 0; |
443 | } | |
ec10665c | 444 | |
36d0fd21 LA |
445 | destroy_genpool: |
446 | gen_pool_destroy(atomic_pool); | |
447 | atomic_pool = NULL; | |
448 | out: | |
bf31c5e0 | 449 | pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n", |
36d0fd21 | 450 | atomic_pool_size / 1024); |
c7909509 MS |
451 | return -ENOMEM; |
452 | } | |
453 | /* | |
454 | * CMA is activated by core_initcall, so we must be called after it. | |
455 | */ | |
e9da6e99 | 456 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
457 | |
458 | struct dma_contig_early_reserve { | |
459 | phys_addr_t base; | |
460 | unsigned long size; | |
461 | }; | |
462 | ||
463 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
464 | ||
465 | static int dma_mmu_remap_num __initdata; | |
466 | ||
467 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
468 | { | |
469 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
470 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
471 | dma_mmu_remap_num++; | |
472 | } | |
473 | ||
474 | void __init dma_contiguous_remap(void) | |
475 | { | |
476 | int i; | |
477 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
478 | phys_addr_t start = dma_mmu_remap[i].base; | |
479 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
480 | struct map_desc map; | |
481 | unsigned long addr; | |
482 | ||
483 | if (end > arm_lowmem_limit) | |
484 | end = arm_lowmem_limit; | |
485 | if (start >= end) | |
39f78e70 | 486 | continue; |
c7909509 MS |
487 | |
488 | map.pfn = __phys_to_pfn(start); | |
489 | map.virtual = __phys_to_virt(start); | |
490 | map.length = end - start; | |
491 | map.type = MT_MEMORY_DMA_READY; | |
492 | ||
493 | /* | |
6b076991 RK |
494 | * Clear previous low-memory mapping to ensure that the |
495 | * TLB does not see any conflicting entries, then flush | |
496 | * the TLB of the old entries before creating new mappings. | |
497 | * | |
498 | * This ensures that any speculatively loaded TLB entries | |
499 | * (even though they may be rare) can not cause any problems, | |
500 | * and ensures that this code is architecturally compliant. | |
c7909509 MS |
501 | */ |
502 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 503 | addr += PMD_SIZE) |
c7909509 MS |
504 | pmd_clear(pmd_off_k(addr)); |
505 | ||
6b076991 RK |
506 | flush_tlb_kernel_range(__phys_to_virt(start), |
507 | __phys_to_virt(end)); | |
508 | ||
c7909509 MS |
509 | iotable_init(&map, 1); |
510 | } | |
511 | } | |
512 | ||
c7909509 MS |
513 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
514 | void *data) | |
515 | { | |
516 | struct page *page = virt_to_page(addr); | |
517 | pgprot_t prot = *(pgprot_t *)data; | |
518 | ||
519 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
520 | return 0; | |
521 | } | |
522 | ||
523 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
524 | { | |
525 | unsigned long start = (unsigned long) page_address(page); | |
526 | unsigned end = start + size; | |
527 | ||
528 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
c7909509 MS |
529 | flush_tlb_kernel_range(start, end); |
530 | } | |
531 | ||
532 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
533 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 534 | const void *caller, bool want_vaddr) |
c7909509 MS |
535 | { |
536 | struct page *page; | |
6e8266e3 | 537 | void *ptr = NULL; |
f1270896 GC |
538 | /* |
539 | * __alloc_remap_buffer is only called when the device is | |
540 | * non-coherent | |
541 | */ | |
542 | page = __dma_alloc_buffer(dev, size, gfp, NORMAL); | |
c7909509 MS |
543 | if (!page) |
544 | return NULL; | |
6e8266e3 CC |
545 | if (!want_vaddr) |
546 | goto out; | |
c7909509 MS |
547 | |
548 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
549 | if (!ptr) { | |
550 | __dma_free_buffer(page, size); | |
551 | return NULL; | |
552 | } | |
553 | ||
6e8266e3 | 554 | out: |
c7909509 MS |
555 | *ret_page = page; |
556 | return ptr; | |
557 | } | |
558 | ||
e9da6e99 | 559 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 560 | { |
36d0fd21 | 561 | unsigned long val; |
e9da6e99 | 562 | void *ptr = NULL; |
c7909509 | 563 | |
36d0fd21 | 564 | if (!atomic_pool) { |
e9da6e99 | 565 | WARN(1, "coherent pool not initialised!\n"); |
c7909509 MS |
566 | return NULL; |
567 | } | |
568 | ||
36d0fd21 LA |
569 | val = gen_pool_alloc(atomic_pool, size); |
570 | if (val) { | |
571 | phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val); | |
572 | ||
573 | *ret_page = phys_to_page(phys); | |
574 | ptr = (void *)val; | |
c7909509 | 575 | } |
e9da6e99 MS |
576 | |
577 | return ptr; | |
c7909509 MS |
578 | } |
579 | ||
21d0a759 HD |
580 | static bool __in_atomic_pool(void *start, size_t size) |
581 | { | |
36d0fd21 | 582 | return addr_in_gen_pool(atomic_pool, (unsigned long)start, size); |
21d0a759 HD |
583 | } |
584 | ||
e9da6e99 | 585 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 586 | { |
21d0a759 | 587 | if (!__in_atomic_pool(start, size)) |
c7909509 MS |
588 | return 0; |
589 | ||
36d0fd21 | 590 | gen_pool_free(atomic_pool, (unsigned long)start, size); |
e9da6e99 | 591 | |
c7909509 MS |
592 | return 1; |
593 | } | |
594 | ||
595 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
9848e48f | 596 | pgprot_t prot, struct page **ret_page, |
f1270896 | 597 | const void *caller, bool want_vaddr, |
712c604d | 598 | int coherent_flag, gfp_t gfp) |
c7909509 MS |
599 | { |
600 | unsigned long order = get_order(size); | |
601 | size_t count = size >> PAGE_SHIFT; | |
602 | struct page *page; | |
6e8266e3 | 603 | void *ptr = NULL; |
c7909509 | 604 | |
712c604d | 605 | page = dma_alloc_from_contiguous(dev, count, order, gfp); |
c7909509 MS |
606 | if (!page) |
607 | return NULL; | |
608 | ||
f1270896 | 609 | __dma_clear_buffer(page, size, coherent_flag); |
c7909509 | 610 | |
6e8266e3 CC |
611 | if (!want_vaddr) |
612 | goto out; | |
613 | ||
9848e48f MS |
614 | if (PageHighMem(page)) { |
615 | ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller); | |
616 | if (!ptr) { | |
617 | dma_release_from_contiguous(dev, page, count); | |
618 | return NULL; | |
619 | } | |
620 | } else { | |
621 | __dma_remap(page, size, prot); | |
622 | ptr = page_address(page); | |
623 | } | |
6e8266e3 CC |
624 | |
625 | out: | |
c7909509 | 626 | *ret_page = page; |
9848e48f | 627 | return ptr; |
c7909509 MS |
628 | } |
629 | ||
630 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
6e8266e3 | 631 | void *cpu_addr, size_t size, bool want_vaddr) |
c7909509 | 632 | { |
6e8266e3 CC |
633 | if (want_vaddr) { |
634 | if (PageHighMem(page)) | |
635 | __dma_free_remap(cpu_addr, size); | |
636 | else | |
637 | __dma_remap(page, size, PAGE_KERNEL); | |
638 | } | |
c7909509 MS |
639 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); |
640 | } | |
641 | ||
00085f1e | 642 | static inline pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot) |
f99d6034 | 643 | { |
00085f1e KK |
644 | prot = (attrs & DMA_ATTR_WRITE_COMBINE) ? |
645 | pgprot_writecombine(prot) : | |
646 | pgprot_dmacoherent(prot); | |
f99d6034 MS |
647 | return prot; |
648 | } | |
649 | ||
c7909509 MS |
650 | #define nommu() 0 |
651 | ||
ab6494f0 | 652 | #else /* !CONFIG_MMU */ |
695ae0af | 653 | |
c7909509 MS |
654 | #define nommu() 1 |
655 | ||
6e8266e3 CC |
656 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
657 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL | |
e9da6e99 | 658 | #define __alloc_from_pool(size, ret_page) NULL |
712c604d | 659 | #define __alloc_from_contiguous(dev, size, prot, ret, c, wv, coherent_flag, gfp) NULL |
b4268676 | 660 | #define __free_from_pool(cpu_addr, size) do { } while (0) |
6e8266e3 | 661 | #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0) |
c7909509 | 662 | #define __dma_free_remap(cpu_addr, size) do { } while (0) |
31ebf944 RK |
663 | |
664 | #endif /* CONFIG_MMU */ | |
665 | ||
c7909509 MS |
666 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
667 | struct page **ret_page) | |
ab6494f0 | 668 | { |
c7909509 | 669 | struct page *page; |
f1270896 GC |
670 | /* __alloc_simple_buffer is only called when the device is coherent */ |
671 | page = __dma_alloc_buffer(dev, size, gfp, COHERENT); | |
c7909509 MS |
672 | if (!page) |
673 | return NULL; | |
674 | ||
675 | *ret_page = page; | |
676 | return page_address(page); | |
677 | } | |
678 | ||
b4268676 RV |
679 | static void *simple_allocator_alloc(struct arm_dma_alloc_args *args, |
680 | struct page **ret_page) | |
681 | { | |
682 | return __alloc_simple_buffer(args->dev, args->size, args->gfp, | |
683 | ret_page); | |
684 | } | |
c7909509 | 685 | |
b4268676 RV |
686 | static void simple_allocator_free(struct arm_dma_free_args *args) |
687 | { | |
688 | __dma_free_buffer(args->page, args->size); | |
689 | } | |
690 | ||
691 | static struct arm_dma_allocator simple_allocator = { | |
692 | .alloc = simple_allocator_alloc, | |
693 | .free = simple_allocator_free, | |
694 | }; | |
695 | ||
696 | static void *cma_allocator_alloc(struct arm_dma_alloc_args *args, | |
697 | struct page **ret_page) | |
698 | { | |
699 | return __alloc_from_contiguous(args->dev, args->size, args->prot, | |
700 | ret_page, args->caller, | |
712c604d LS |
701 | args->want_vaddr, args->coherent_flag, |
702 | args->gfp); | |
b4268676 RV |
703 | } |
704 | ||
705 | static void cma_allocator_free(struct arm_dma_free_args *args) | |
706 | { | |
707 | __free_from_contiguous(args->dev, args->page, args->cpu_addr, | |
708 | args->size, args->want_vaddr); | |
709 | } | |
710 | ||
711 | static struct arm_dma_allocator cma_allocator = { | |
712 | .alloc = cma_allocator_alloc, | |
713 | .free = cma_allocator_free, | |
714 | }; | |
715 | ||
716 | static void *pool_allocator_alloc(struct arm_dma_alloc_args *args, | |
717 | struct page **ret_page) | |
718 | { | |
719 | return __alloc_from_pool(args->size, ret_page); | |
720 | } | |
721 | ||
722 | static void pool_allocator_free(struct arm_dma_free_args *args) | |
723 | { | |
724 | __free_from_pool(args->cpu_addr, args->size); | |
725 | } | |
726 | ||
727 | static struct arm_dma_allocator pool_allocator = { | |
728 | .alloc = pool_allocator_alloc, | |
729 | .free = pool_allocator_free, | |
730 | }; | |
731 | ||
732 | static void *remap_allocator_alloc(struct arm_dma_alloc_args *args, | |
733 | struct page **ret_page) | |
734 | { | |
735 | return __alloc_remap_buffer(args->dev, args->size, args->gfp, | |
736 | args->prot, ret_page, args->caller, | |
737 | args->want_vaddr); | |
738 | } | |
739 | ||
740 | static void remap_allocator_free(struct arm_dma_free_args *args) | |
741 | { | |
742 | if (args->want_vaddr) | |
743 | __dma_free_remap(args->cpu_addr, args->size); | |
744 | ||
745 | __dma_free_buffer(args->page, args->size); | |
746 | } | |
747 | ||
748 | static struct arm_dma_allocator remap_allocator = { | |
749 | .alloc = remap_allocator_alloc, | |
750 | .free = remap_allocator_free, | |
751 | }; | |
c7909509 MS |
752 | |
753 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
6e8266e3 | 754 | gfp_t gfp, pgprot_t prot, bool is_coherent, |
00085f1e | 755 | unsigned long attrs, const void *caller) |
c7909509 MS |
756 | { |
757 | u64 mask = get_coherent_dma_mask(dev); | |
3dd7ea92 | 758 | struct page *page = NULL; |
31ebf944 | 759 | void *addr; |
b4268676 | 760 | bool allowblock, cma; |
19e6e5e5 | 761 | struct arm_dma_buffer *buf; |
b4268676 RV |
762 | struct arm_dma_alloc_args args = { |
763 | .dev = dev, | |
764 | .size = PAGE_ALIGN(size), | |
765 | .gfp = gfp, | |
766 | .prot = prot, | |
767 | .caller = caller, | |
00085f1e | 768 | .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0), |
f1270896 | 769 | .coherent_flag = is_coherent ? COHERENT : NORMAL, |
b4268676 | 770 | }; |
ab6494f0 | 771 | |
c7909509 MS |
772 | #ifdef CONFIG_DMA_API_DEBUG |
773 | u64 limit = (mask + 1) & ~mask; | |
774 | if (limit && size >= limit) { | |
775 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
776 | size, mask); | |
777 | return NULL; | |
778 | } | |
779 | #endif | |
780 | ||
781 | if (!mask) | |
782 | return NULL; | |
783 | ||
9c18fcf7 AC |
784 | buf = kzalloc(sizeof(*buf), |
785 | gfp & ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM)); | |
19e6e5e5 RV |
786 | if (!buf) |
787 | return NULL; | |
788 | ||
c7909509 MS |
789 | if (mask < 0xffffffffULL) |
790 | gfp |= GFP_DMA; | |
791 | ||
ea2e7057 SB |
792 | /* |
793 | * Following is a work-around (a.k.a. hack) to prevent pages | |
794 | * with __GFP_COMP being passed to split_page() which cannot | |
795 | * handle them. The real problem is that this flag probably | |
796 | * should be 0 on ARM as it is not supported on this | |
797 | * platform; see CONFIG_HUGETLBFS. | |
798 | */ | |
799 | gfp &= ~(__GFP_COMP); | |
b4268676 | 800 | args.gfp = gfp; |
ea2e7057 | 801 | |
553ac788 | 802 | *handle = DMA_ERROR_CODE; |
b4268676 RV |
803 | allowblock = gfpflags_allow_blocking(gfp); |
804 | cma = allowblock ? dev_get_cma_area(dev) : false; | |
805 | ||
806 | if (cma) | |
807 | buf->allocator = &cma_allocator; | |
808 | else if (nommu() || is_coherent) | |
809 | buf->allocator = &simple_allocator; | |
810 | else if (allowblock) | |
811 | buf->allocator = &remap_allocator; | |
31ebf944 | 812 | else |
b4268676 RV |
813 | buf->allocator = &pool_allocator; |
814 | ||
815 | addr = buf->allocator->alloc(&args, &page); | |
695ae0af | 816 | |
19e6e5e5 RV |
817 | if (page) { |
818 | unsigned long flags; | |
819 | ||
9eedd963 | 820 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
b4268676 | 821 | buf->virt = args.want_vaddr ? addr : page; |
19e6e5e5 RV |
822 | |
823 | spin_lock_irqsave(&arm_dma_bufs_lock, flags); | |
824 | list_add(&buf->list, &arm_dma_bufs); | |
825 | spin_unlock_irqrestore(&arm_dma_bufs_lock, flags); | |
826 | } else { | |
827 | kfree(buf); | |
828 | } | |
695ae0af | 829 | |
b4268676 | 830 | return args.want_vaddr ? addr : page; |
31ebf944 | 831 | } |
1da177e4 LT |
832 | |
833 | /* | |
834 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
835 | * virtual and bus address for that space. | |
836 | */ | |
f99d6034 | 837 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
00085f1e | 838 | gfp_t gfp, unsigned long attrs) |
1da177e4 | 839 | { |
0ea1ec71 | 840 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
1fe53268 | 841 | |
dd37e940 | 842 | return __dma_alloc(dev, size, handle, gfp, prot, false, |
6e8266e3 | 843 | attrs, __builtin_return_address(0)); |
dd37e940 RH |
844 | } |
845 | ||
846 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, | |
00085f1e | 847 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs) |
dd37e940 | 848 | { |
21caf3a7 | 849 | return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true, |
6e8266e3 | 850 | attrs, __builtin_return_address(0)); |
1da177e4 | 851 | } |
1da177e4 | 852 | |
55af8a91 | 853 | static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
f99d6034 | 854 | void *cpu_addr, dma_addr_t dma_addr, size_t size, |
00085f1e | 855 | unsigned long attrs) |
1da177e4 | 856 | { |
ab6494f0 CM |
857 | int ret = -ENXIO; |
858 | #ifdef CONFIG_MMU | |
50262a4b MS |
859 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
860 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 861 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
862 | unsigned long off = vma->vm_pgoff; |
863 | ||
47142f07 MS |
864 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
865 | return ret; | |
866 | ||
50262a4b MS |
867 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
868 | ret = remap_pfn_range(vma, vma->vm_start, | |
869 | pfn + off, | |
870 | vma->vm_end - vma->vm_start, | |
871 | vma->vm_page_prot); | |
872 | } | |
79964a1c BG |
873 | #else |
874 | ret = vm_iomap_memory(vma, vma->vm_start, | |
875 | (vma->vm_end - vma->vm_start)); | |
ab6494f0 | 876 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
877 | |
878 | return ret; | |
879 | } | |
880 | ||
55af8a91 ML |
881 | /* |
882 | * Create userspace mapping for the DMA-coherent memory. | |
883 | */ | |
884 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
885 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
00085f1e | 886 | unsigned long attrs) |
55af8a91 ML |
887 | { |
888 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
889 | } | |
890 | ||
891 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
892 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
00085f1e | 893 | unsigned long attrs) |
55af8a91 ML |
894 | { |
895 | #ifdef CONFIG_MMU | |
896 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
897 | #endif /* CONFIG_MMU */ | |
898 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
899 | } | |
900 | ||
1da177e4 | 901 | /* |
c7909509 | 902 | * Free a buffer as defined by the above mapping. |
1da177e4 | 903 | */ |
dd37e940 | 904 | static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 905 | dma_addr_t handle, unsigned long attrs, |
dd37e940 | 906 | bool is_coherent) |
1da177e4 | 907 | { |
c7909509 | 908 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
19e6e5e5 | 909 | struct arm_dma_buffer *buf; |
b4268676 RV |
910 | struct arm_dma_free_args args = { |
911 | .dev = dev, | |
912 | .size = PAGE_ALIGN(size), | |
913 | .cpu_addr = cpu_addr, | |
914 | .page = page, | |
00085f1e | 915 | .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0), |
b4268676 | 916 | }; |
19e6e5e5 RV |
917 | |
918 | buf = arm_dma_buffer_find(cpu_addr); | |
919 | if (WARN(!buf, "Freeing invalid buffer %p\n", cpu_addr)) | |
920 | return; | |
5edf71ae | 921 | |
b4268676 | 922 | buf->allocator->free(&args); |
19e6e5e5 | 923 | kfree(buf); |
1da177e4 | 924 | } |
afd1a321 | 925 | |
dd37e940 | 926 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 927 | dma_addr_t handle, unsigned long attrs) |
dd37e940 RH |
928 | { |
929 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, false); | |
930 | } | |
931 | ||
932 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
00085f1e | 933 | dma_addr_t handle, unsigned long attrs) |
dd37e940 RH |
934 | { |
935 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, true); | |
936 | } | |
937 | ||
916a008b RK |
938 | /* |
939 | * The whole dma_get_sgtable() idea is fundamentally unsafe - it seems | |
940 | * that the intention is to allow exporting memory allocated via the | |
941 | * coherent DMA APIs through the dma_buf API, which only accepts a | |
942 | * scattertable. This presents a couple of problems: | |
943 | * 1. Not all memory allocated via the coherent DMA APIs is backed by | |
944 | * a struct page | |
945 | * 2. Passing coherent DMA memory into the streaming APIs is not allowed | |
946 | * as we will try to flush the memory through a different alias to that | |
947 | * actually being used (and the flushes are redundant.) | |
948 | */ | |
dc2832e1 MS |
949 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
950 | void *cpu_addr, dma_addr_t handle, size_t size, | |
00085f1e | 951 | unsigned long attrs) |
dc2832e1 | 952 | { |
916a008b RK |
953 | unsigned long pfn = dma_to_pfn(dev, handle); |
954 | struct page *page; | |
dc2832e1 MS |
955 | int ret; |
956 | ||
916a008b RK |
957 | /* If the PFN is not valid, we do not have a struct page */ |
958 | if (!pfn_valid(pfn)) | |
959 | return -ENXIO; | |
960 | ||
961 | page = pfn_to_page(pfn); | |
962 | ||
dc2832e1 MS |
963 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); |
964 | if (unlikely(ret)) | |
965 | return ret; | |
966 | ||
967 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
968 | return 0; | |
969 | } | |
970 | ||
4ea0d737 | 971 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
972 | size_t size, enum dma_data_direction dir, |
973 | void (*op)(const void *, size_t, int)) | |
43377453 | 974 | { |
15653371 RK |
975 | unsigned long pfn; |
976 | size_t left = size; | |
977 | ||
978 | pfn = page_to_pfn(page) + offset / PAGE_SIZE; | |
979 | offset %= PAGE_SIZE; | |
980 | ||
43377453 NP |
981 | /* |
982 | * A single sg entry may refer to multiple physically contiguous | |
983 | * pages. But we still need to process highmem pages individually. | |
984 | * If highmem is not configured then the bulk of this loop gets | |
985 | * optimized out. | |
986 | */ | |
43377453 NP |
987 | do { |
988 | size_t len = left; | |
93f1d629 RK |
989 | void *vaddr; |
990 | ||
15653371 RK |
991 | page = pfn_to_page(pfn); |
992 | ||
93f1d629 | 993 | if (PageHighMem(page)) { |
15653371 | 994 | if (len + offset > PAGE_SIZE) |
93f1d629 | 995 | len = PAGE_SIZE - offset; |
dd0f67f4 JK |
996 | |
997 | if (cache_is_vipt_nonaliasing()) { | |
39af22a7 | 998 | vaddr = kmap_atomic(page); |
7e5a69e8 | 999 | op(vaddr + offset, len, dir); |
39af22a7 | 1000 | kunmap_atomic(vaddr); |
dd0f67f4 JK |
1001 | } else { |
1002 | vaddr = kmap_high_get(page); | |
1003 | if (vaddr) { | |
1004 | op(vaddr + offset, len, dir); | |
1005 | kunmap_high(page); | |
1006 | } | |
43377453 | 1007 | } |
93f1d629 RK |
1008 | } else { |
1009 | vaddr = page_address(page) + offset; | |
a9c9147e | 1010 | op(vaddr, len, dir); |
43377453 | 1011 | } |
43377453 | 1012 | offset = 0; |
15653371 | 1013 | pfn++; |
43377453 NP |
1014 | left -= len; |
1015 | } while (left); | |
1016 | } | |
4ea0d737 | 1017 | |
51fde349 MS |
1018 | /* |
1019 | * Make an area consistent for devices. | |
1020 | * Note: Drivers should NOT use this function directly, as it will break | |
1021 | * platforms with CONFIG_DMABOUNCE. | |
1022 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
1023 | */ | |
1024 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
1025 | size_t size, enum dma_data_direction dir) |
1026 | { | |
2161c248 | 1027 | phys_addr_t paddr; |
65af191a | 1028 | |
a9c9147e | 1029 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
1030 | |
1031 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
1032 | if (dir == DMA_FROM_DEVICE) { |
1033 | outer_inv_range(paddr, paddr + size); | |
1034 | } else { | |
1035 | outer_clean_range(paddr, paddr + size); | |
1036 | } | |
1037 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 1038 | } |
4ea0d737 | 1039 | |
51fde349 | 1040 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
1041 | size_t size, enum dma_data_direction dir) |
1042 | { | |
2161c248 | 1043 | phys_addr_t paddr = page_to_phys(page) + off; |
2ffe2da3 RK |
1044 | |
1045 | /* FIXME: non-speculating: not required */ | |
deace4a6 RK |
1046 | /* in any case, don't bother invalidating if DMA to device */ |
1047 | if (dir != DMA_TO_DEVICE) { | |
2ffe2da3 RK |
1048 | outer_inv_range(paddr, paddr + size); |
1049 | ||
deace4a6 RK |
1050 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
1051 | } | |
c0177800 CM |
1052 | |
1053 | /* | |
b2a234ed | 1054 | * Mark the D-cache clean for these pages to avoid extra flushing. |
c0177800 | 1055 | */ |
b2a234ed ML |
1056 | if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) { |
1057 | unsigned long pfn; | |
1058 | size_t left = size; | |
1059 | ||
1060 | pfn = page_to_pfn(page) + off / PAGE_SIZE; | |
1061 | off %= PAGE_SIZE; | |
1062 | if (off) { | |
1063 | pfn++; | |
1064 | left -= PAGE_SIZE - off; | |
1065 | } | |
1066 | while (left >= PAGE_SIZE) { | |
1067 | page = pfn_to_page(pfn++); | |
1068 | set_bit(PG_dcache_clean, &page->flags); | |
1069 | left -= PAGE_SIZE; | |
1070 | } | |
1071 | } | |
4ea0d737 | 1072 | } |
43377453 | 1073 | |
afd1a321 | 1074 | /** |
2a550e73 | 1075 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
1076 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1077 | * @sg: list of buffers | |
1078 | * @nents: number of buffers to map | |
1079 | * @dir: DMA transfer direction | |
1080 | * | |
1081 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1082 | * This is the scatter-gather version of the dma_map_single interface. | |
1083 | * Here the scatter gather list elements are each tagged with the | |
1084 | * appropriate dma address and length. They are obtained via | |
1085 | * sg_dma_{address,length}. | |
1086 | * | |
1087 | * Device ownership issues as mentioned for dma_map_single are the same | |
1088 | * here. | |
1089 | */ | |
2dc6a016 | 1090 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
00085f1e | 1091 | enum dma_data_direction dir, unsigned long attrs) |
afd1a321 | 1092 | { |
5299709d | 1093 | const struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 1094 | struct scatterlist *s; |
01135d92 | 1095 | int i, j; |
afd1a321 RK |
1096 | |
1097 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
1098 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
1099 | s->dma_length = s->length; | |
1100 | #endif | |
2a550e73 MS |
1101 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
1102 | s->length, dir, attrs); | |
01135d92 RK |
1103 | if (dma_mapping_error(dev, s->dma_address)) |
1104 | goto bad_mapping; | |
afd1a321 | 1105 | } |
afd1a321 | 1106 | return nents; |
01135d92 RK |
1107 | |
1108 | bad_mapping: | |
1109 | for_each_sg(sg, s, i, j) | |
2a550e73 | 1110 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 1111 | return 0; |
afd1a321 | 1112 | } |
afd1a321 RK |
1113 | |
1114 | /** | |
2a550e73 | 1115 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
1116 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1117 | * @sg: list of buffers | |
0adfca6f | 1118 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
1119 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
1120 | * | |
1121 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1122 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1123 | */ | |
2dc6a016 | 1124 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
00085f1e | 1125 | enum dma_data_direction dir, unsigned long attrs) |
afd1a321 | 1126 | { |
5299709d | 1127 | const struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 1128 | struct scatterlist *s; |
01135d92 | 1129 | |
01135d92 | 1130 | int i; |
24056f52 | 1131 | |
01135d92 | 1132 | for_each_sg(sg, s, nents, i) |
2a550e73 | 1133 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 1134 | } |
afd1a321 RK |
1135 | |
1136 | /** | |
2a550e73 | 1137 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
1138 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1139 | * @sg: list of buffers | |
1140 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1141 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1142 | */ | |
2dc6a016 | 1143 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1144 | int nents, enum dma_data_direction dir) |
1145 | { | |
5299709d | 1146 | const struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1147 | struct scatterlist *s; |
1148 | int i; | |
1149 | ||
2a550e73 MS |
1150 | for_each_sg(sg, s, nents, i) |
1151 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
1152 | dir); | |
afd1a321 | 1153 | } |
afd1a321 RK |
1154 | |
1155 | /** | |
2a550e73 | 1156 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
1157 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1158 | * @sg: list of buffers | |
1159 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1160 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1161 | */ | |
2dc6a016 | 1162 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1163 | int nents, enum dma_data_direction dir) |
1164 | { | |
5299709d | 1165 | const struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1166 | struct scatterlist *s; |
1167 | int i; | |
1168 | ||
2a550e73 MS |
1169 | for_each_sg(sg, s, nents, i) |
1170 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
1171 | dir); | |
afd1a321 | 1172 | } |
24056f52 | 1173 | |
022ae537 RK |
1174 | /* |
1175 | * Return whether the given device DMA address mask can be supported | |
1176 | * properly. For example, if your device can only drive the low 24-bits | |
1177 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
1178 | * to this function. | |
1179 | */ | |
1180 | int dma_supported(struct device *dev, u64 mask) | |
1181 | { | |
9f28cde0 | 1182 | return __dma_supported(dev, mask, false); |
022ae537 RK |
1183 | } |
1184 | EXPORT_SYMBOL(dma_supported); | |
1185 | ||
24056f52 RK |
1186 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
1187 | ||
1188 | static int __init dma_debug_do_init(void) | |
1189 | { | |
1190 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
1191 | return 0; | |
1192 | } | |
256ff1cf | 1193 | core_initcall(dma_debug_do_init); |
4ce63fcd MS |
1194 | |
1195 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
1196 | ||
7d2822df S |
1197 | static int __dma_info_to_prot(enum dma_data_direction dir, unsigned long attrs) |
1198 | { | |
1199 | int prot = 0; | |
1200 | ||
1201 | if (attrs & DMA_ATTR_PRIVILEGED) | |
1202 | prot |= IOMMU_PRIV; | |
1203 | ||
1204 | switch (dir) { | |
1205 | case DMA_BIDIRECTIONAL: | |
1206 | return prot | IOMMU_READ | IOMMU_WRITE; | |
1207 | case DMA_TO_DEVICE: | |
1208 | return prot | IOMMU_READ; | |
1209 | case DMA_FROM_DEVICE: | |
1210 | return prot | IOMMU_WRITE; | |
1211 | default: | |
1212 | return prot; | |
1213 | } | |
1214 | } | |
1215 | ||
4ce63fcd MS |
1216 | /* IOMMU */ |
1217 | ||
4d852ef8 AH |
1218 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping); |
1219 | ||
4ce63fcd MS |
1220 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, |
1221 | size_t size) | |
1222 | { | |
1223 | unsigned int order = get_order(size); | |
1224 | unsigned int align = 0; | |
1225 | unsigned int count, start; | |
006f841d | 1226 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1227 | unsigned long flags; |
4d852ef8 AH |
1228 | dma_addr_t iova; |
1229 | int i; | |
4ce63fcd | 1230 | |
60460abf SWK |
1231 | if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT) |
1232 | order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT; | |
1233 | ||
68efd7d2 MS |
1234 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1235 | align = (1 << order) - 1; | |
4ce63fcd MS |
1236 | |
1237 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 AH |
1238 | for (i = 0; i < mapping->nr_bitmaps; i++) { |
1239 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1240 | mapping->bits, 0, count, align); | |
1241 | ||
1242 | if (start > mapping->bits) | |
1243 | continue; | |
1244 | ||
1245 | bitmap_set(mapping->bitmaps[i], start, count); | |
1246 | break; | |
4ce63fcd MS |
1247 | } |
1248 | ||
4d852ef8 AH |
1249 | /* |
1250 | * No unused range found. Try to extend the existing mapping | |
1251 | * and perform a second attempt to reserve an IO virtual | |
1252 | * address range of size bytes. | |
1253 | */ | |
1254 | if (i == mapping->nr_bitmaps) { | |
1255 | if (extend_iommu_mapping(mapping)) { | |
1256 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1257 | return DMA_ERROR_CODE; | |
1258 | } | |
1259 | ||
1260 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1261 | mapping->bits, 0, count, align); | |
1262 | ||
1263 | if (start > mapping->bits) { | |
1264 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1265 | return DMA_ERROR_CODE; | |
1266 | } | |
1267 | ||
1268 | bitmap_set(mapping->bitmaps[i], start, count); | |
1269 | } | |
4ce63fcd MS |
1270 | spin_unlock_irqrestore(&mapping->lock, flags); |
1271 | ||
006f841d | 1272 | iova = mapping->base + (mapping_size * i); |
68efd7d2 | 1273 | iova += start << PAGE_SHIFT; |
4d852ef8 AH |
1274 | |
1275 | return iova; | |
4ce63fcd MS |
1276 | } |
1277 | ||
1278 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
1279 | dma_addr_t addr, size_t size) | |
1280 | { | |
4d852ef8 | 1281 | unsigned int start, count; |
006f841d | 1282 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1283 | unsigned long flags; |
4d852ef8 AH |
1284 | dma_addr_t bitmap_base; |
1285 | u32 bitmap_index; | |
1286 | ||
1287 | if (!size) | |
1288 | return; | |
1289 | ||
006f841d | 1290 | bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size; |
4d852ef8 AH |
1291 | BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions); |
1292 | ||
006f841d | 1293 | bitmap_base = mapping->base + mapping_size * bitmap_index; |
4d852ef8 | 1294 | |
68efd7d2 | 1295 | start = (addr - bitmap_base) >> PAGE_SHIFT; |
4d852ef8 | 1296 | |
006f841d | 1297 | if (addr + size > bitmap_base + mapping_size) { |
4d852ef8 AH |
1298 | /* |
1299 | * The address range to be freed reaches into the iova | |
1300 | * range of the next bitmap. This should not happen as | |
1301 | * we don't allow this in __alloc_iova (at the | |
1302 | * moment). | |
1303 | */ | |
1304 | BUG(); | |
1305 | } else | |
68efd7d2 | 1306 | count = size >> PAGE_SHIFT; |
4ce63fcd MS |
1307 | |
1308 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 | 1309 | bitmap_clear(mapping->bitmaps[bitmap_index], start, count); |
4ce63fcd MS |
1310 | spin_unlock_irqrestore(&mapping->lock, flags); |
1311 | } | |
1312 | ||
33298ef6 DA |
1313 | /* We'll try 2M, 1M, 64K, and finally 4K; array must end with 0! */ |
1314 | static const int iommu_order_array[] = { 9, 8, 4, 0 }; | |
1315 | ||
549a17e4 | 1316 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, |
00085f1e | 1317 | gfp_t gfp, unsigned long attrs, |
f1270896 | 1318 | int coherent_flag) |
4ce63fcd MS |
1319 | { |
1320 | struct page **pages; | |
1321 | int count = size >> PAGE_SHIFT; | |
1322 | int array_size = count * sizeof(struct page *); | |
1323 | int i = 0; | |
33298ef6 | 1324 | int order_idx = 0; |
4ce63fcd MS |
1325 | |
1326 | if (array_size <= PAGE_SIZE) | |
23be7fda | 1327 | pages = kzalloc(array_size, GFP_KERNEL); |
4ce63fcd MS |
1328 | else |
1329 | pages = vzalloc(array_size); | |
1330 | if (!pages) | |
1331 | return NULL; | |
1332 | ||
00085f1e | 1333 | if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) |
549a17e4 MS |
1334 | { |
1335 | unsigned long order = get_order(size); | |
1336 | struct page *page; | |
1337 | ||
712c604d | 1338 | page = dma_alloc_from_contiguous(dev, count, order, gfp); |
549a17e4 MS |
1339 | if (!page) |
1340 | goto error; | |
1341 | ||
f1270896 | 1342 | __dma_clear_buffer(page, size, coherent_flag); |
549a17e4 MS |
1343 | |
1344 | for (i = 0; i < count; i++) | |
1345 | pages[i] = page + i; | |
1346 | ||
1347 | return pages; | |
1348 | } | |
1349 | ||
14d3ae2e | 1350 | /* Go straight to 4K chunks if caller says it's OK. */ |
00085f1e | 1351 | if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES) |
14d3ae2e DA |
1352 | order_idx = ARRAY_SIZE(iommu_order_array) - 1; |
1353 | ||
f8669bef MS |
1354 | /* |
1355 | * IOMMU can map any pages, so himem can also be used here | |
1356 | */ | |
1357 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
1358 | ||
4ce63fcd | 1359 | while (count) { |
49f28aa6 TF |
1360 | int j, order; |
1361 | ||
33298ef6 DA |
1362 | order = iommu_order_array[order_idx]; |
1363 | ||
1364 | /* Drop down when we get small */ | |
1365 | if (__fls(count) < order) { | |
1366 | order_idx++; | |
1367 | continue; | |
49f28aa6 | 1368 | } |
4ce63fcd | 1369 | |
33298ef6 DA |
1370 | if (order) { |
1371 | /* See if it's easy to allocate a high-order chunk */ | |
1372 | pages[i] = alloc_pages(gfp | __GFP_NORETRY, order); | |
1373 | ||
1374 | /* Go down a notch at first sign of pressure */ | |
1375 | if (!pages[i]) { | |
1376 | order_idx++; | |
1377 | continue; | |
1378 | } | |
1379 | } else { | |
49f28aa6 TF |
1380 | pages[i] = alloc_pages(gfp, 0); |
1381 | if (!pages[i]) | |
1382 | goto error; | |
1383 | } | |
4ce63fcd | 1384 | |
5a796eeb | 1385 | if (order) { |
4ce63fcd | 1386 | split_page(pages[i], order); |
5a796eeb HD |
1387 | j = 1 << order; |
1388 | while (--j) | |
1389 | pages[i + j] = pages[i] + j; | |
1390 | } | |
4ce63fcd | 1391 | |
f1270896 | 1392 | __dma_clear_buffer(pages[i], PAGE_SIZE << order, coherent_flag); |
4ce63fcd MS |
1393 | i += 1 << order; |
1394 | count -= 1 << order; | |
1395 | } | |
1396 | ||
1397 | return pages; | |
1398 | error: | |
9fa8af91 | 1399 | while (i--) |
4ce63fcd MS |
1400 | if (pages[i]) |
1401 | __free_pages(pages[i], 0); | |
1d5cfdb0 | 1402 | kvfree(pages); |
4ce63fcd MS |
1403 | return NULL; |
1404 | } | |
1405 | ||
549a17e4 | 1406 | static int __iommu_free_buffer(struct device *dev, struct page **pages, |
00085f1e | 1407 | size_t size, unsigned long attrs) |
4ce63fcd MS |
1408 | { |
1409 | int count = size >> PAGE_SHIFT; | |
4ce63fcd | 1410 | int i; |
549a17e4 | 1411 | |
00085f1e | 1412 | if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) { |
549a17e4 MS |
1413 | dma_release_from_contiguous(dev, pages[0], count); |
1414 | } else { | |
1415 | for (i = 0; i < count; i++) | |
1416 | if (pages[i]) | |
1417 | __free_pages(pages[i], 0); | |
1418 | } | |
1419 | ||
1d5cfdb0 | 1420 | kvfree(pages); |
4ce63fcd MS |
1421 | return 0; |
1422 | } | |
1423 | ||
1424 | /* | |
1425 | * Create a CPU mapping for a specified pages | |
1426 | */ | |
1427 | static void * | |
e9da6e99 MS |
1428 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1429 | const void *caller) | |
4ce63fcd | 1430 | { |
513510dd LA |
1431 | return dma_common_pages_remap(pages, size, |
1432 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller); | |
4ce63fcd MS |
1433 | } |
1434 | ||
1435 | /* | |
1436 | * Create a mapping in device IO address space for specified pages | |
1437 | */ | |
1438 | static dma_addr_t | |
7d2822df S |
1439 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size, |
1440 | unsigned long attrs) | |
4ce63fcd | 1441 | { |
89cfdb19 | 1442 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1443 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1444 | dma_addr_t dma_addr, iova; | |
90cde558 | 1445 | int i; |
4ce63fcd MS |
1446 | |
1447 | dma_addr = __alloc_iova(mapping, size); | |
1448 | if (dma_addr == DMA_ERROR_CODE) | |
1449 | return dma_addr; | |
1450 | ||
1451 | iova = dma_addr; | |
1452 | for (i = 0; i < count; ) { | |
90cde558 AP |
1453 | int ret; |
1454 | ||
4ce63fcd MS |
1455 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; |
1456 | phys_addr_t phys = page_to_phys(pages[i]); | |
1457 | unsigned int len, j; | |
1458 | ||
1459 | for (j = i + 1; j < count; j++, next_pfn++) | |
1460 | if (page_to_pfn(pages[j]) != next_pfn) | |
1461 | break; | |
1462 | ||
1463 | len = (j - i) << PAGE_SHIFT; | |
c9b24996 | 1464 | ret = iommu_map(mapping->domain, iova, phys, len, |
7d2822df | 1465 | __dma_info_to_prot(DMA_BIDIRECTIONAL, attrs)); |
4ce63fcd MS |
1466 | if (ret < 0) |
1467 | goto fail; | |
1468 | iova += len; | |
1469 | i = j; | |
1470 | } | |
1471 | return dma_addr; | |
1472 | fail: | |
1473 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1474 | __free_iova(mapping, dma_addr, size); | |
1475 | return DMA_ERROR_CODE; | |
1476 | } | |
1477 | ||
1478 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1479 | { | |
89cfdb19 | 1480 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1481 | |
1482 | /* | |
1483 | * add optional in-page offset from iova to size and align | |
1484 | * result to page size | |
1485 | */ | |
1486 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1487 | iova &= PAGE_MASK; | |
1488 | ||
1489 | iommu_unmap(mapping->domain, iova, size); | |
1490 | __free_iova(mapping, iova, size); | |
1491 | return 0; | |
1492 | } | |
1493 | ||
665bad7b HD |
1494 | static struct page **__atomic_get_pages(void *addr) |
1495 | { | |
36d0fd21 LA |
1496 | struct page *page; |
1497 | phys_addr_t phys; | |
1498 | ||
1499 | phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr); | |
1500 | page = phys_to_page(phys); | |
665bad7b | 1501 | |
36d0fd21 | 1502 | return (struct page **)page; |
665bad7b HD |
1503 | } |
1504 | ||
00085f1e | 1505 | static struct page **__iommu_get_pages(void *cpu_addr, unsigned long attrs) |
e9da6e99 MS |
1506 | { |
1507 | struct vm_struct *area; | |
1508 | ||
665bad7b HD |
1509 | if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) |
1510 | return __atomic_get_pages(cpu_addr); | |
1511 | ||
00085f1e | 1512 | if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) |
955c757e MS |
1513 | return cpu_addr; |
1514 | ||
e9da6e99 MS |
1515 | area = find_vm_area(cpu_addr); |
1516 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1517 | return area->pages; | |
1518 | return NULL; | |
1519 | } | |
1520 | ||
56506822 | 1521 | static void *__iommu_alloc_simple(struct device *dev, size_t size, gfp_t gfp, |
7d2822df S |
1522 | dma_addr_t *handle, int coherent_flag, |
1523 | unsigned long attrs) | |
479ed93a HD |
1524 | { |
1525 | struct page *page; | |
1526 | void *addr; | |
1527 | ||
56506822 GC |
1528 | if (coherent_flag == COHERENT) |
1529 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
1530 | else | |
1531 | addr = __alloc_from_pool(size, &page); | |
479ed93a HD |
1532 | if (!addr) |
1533 | return NULL; | |
1534 | ||
7d2822df | 1535 | *handle = __iommu_create_mapping(dev, &page, size, attrs); |
479ed93a HD |
1536 | if (*handle == DMA_ERROR_CODE) |
1537 | goto err_mapping; | |
1538 | ||
1539 | return addr; | |
1540 | ||
1541 | err_mapping: | |
1542 | __free_from_pool(addr, size); | |
1543 | return NULL; | |
1544 | } | |
1545 | ||
d5898291 | 1546 | static void __iommu_free_atomic(struct device *dev, void *cpu_addr, |
56506822 | 1547 | dma_addr_t handle, size_t size, int coherent_flag) |
479ed93a HD |
1548 | { |
1549 | __iommu_remove_mapping(dev, handle, size); | |
56506822 GC |
1550 | if (coherent_flag == COHERENT) |
1551 | __dma_free_buffer(virt_to_page(cpu_addr), size); | |
1552 | else | |
1553 | __free_from_pool(cpu_addr, size); | |
479ed93a HD |
1554 | } |
1555 | ||
56506822 | 1556 | static void *__arm_iommu_alloc_attrs(struct device *dev, size_t size, |
00085f1e | 1557 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs, |
56506822 | 1558 | int coherent_flag) |
4ce63fcd | 1559 | { |
71b55663 | 1560 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
4ce63fcd MS |
1561 | struct page **pages; |
1562 | void *addr = NULL; | |
1563 | ||
1564 | *handle = DMA_ERROR_CODE; | |
1565 | size = PAGE_ALIGN(size); | |
1566 | ||
56506822 GC |
1567 | if (coherent_flag == COHERENT || !gfpflags_allow_blocking(gfp)) |
1568 | return __iommu_alloc_simple(dev, size, gfp, handle, | |
7d2822df | 1569 | coherent_flag, attrs); |
479ed93a | 1570 | |
5b91a98c RZ |
1571 | /* |
1572 | * Following is a work-around (a.k.a. hack) to prevent pages | |
1573 | * with __GFP_COMP being passed to split_page() which cannot | |
1574 | * handle them. The real problem is that this flag probably | |
1575 | * should be 0 on ARM as it is not supported on this | |
1576 | * platform; see CONFIG_HUGETLBFS. | |
1577 | */ | |
1578 | gfp &= ~(__GFP_COMP); | |
1579 | ||
56506822 | 1580 | pages = __iommu_alloc_buffer(dev, size, gfp, attrs, coherent_flag); |
4ce63fcd MS |
1581 | if (!pages) |
1582 | return NULL; | |
1583 | ||
7d2822df | 1584 | *handle = __iommu_create_mapping(dev, pages, size, attrs); |
4ce63fcd MS |
1585 | if (*handle == DMA_ERROR_CODE) |
1586 | goto err_buffer; | |
1587 | ||
00085f1e | 1588 | if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) |
955c757e MS |
1589 | return pages; |
1590 | ||
e9da6e99 MS |
1591 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1592 | __builtin_return_address(0)); | |
4ce63fcd MS |
1593 | if (!addr) |
1594 | goto err_mapping; | |
1595 | ||
1596 | return addr; | |
1597 | ||
1598 | err_mapping: | |
1599 | __iommu_remove_mapping(dev, *handle, size); | |
1600 | err_buffer: | |
549a17e4 | 1601 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1602 | return NULL; |
1603 | } | |
1604 | ||
56506822 | 1605 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
00085f1e | 1606 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs) |
56506822 GC |
1607 | { |
1608 | return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, NORMAL); | |
1609 | } | |
1610 | ||
1611 | static void *arm_coherent_iommu_alloc_attrs(struct device *dev, size_t size, | |
00085f1e | 1612 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs) |
56506822 GC |
1613 | { |
1614 | return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, COHERENT); | |
1615 | } | |
1616 | ||
1617 | static int __arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
4ce63fcd | 1618 | void *cpu_addr, dma_addr_t dma_addr, size_t size, |
00085f1e | 1619 | unsigned long attrs) |
4ce63fcd | 1620 | { |
e9da6e99 MS |
1621 | unsigned long uaddr = vma->vm_start; |
1622 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1623 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
371f0f08 MS |
1624 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1625 | unsigned long off = vma->vm_pgoff; | |
4ce63fcd | 1626 | |
e9da6e99 MS |
1627 | if (!pages) |
1628 | return -ENXIO; | |
4ce63fcd | 1629 | |
371f0f08 MS |
1630 | if (off >= nr_pages || (usize >> PAGE_SHIFT) > nr_pages - off) |
1631 | return -ENXIO; | |
1632 | ||
7e312103 MS |
1633 | pages += off; |
1634 | ||
e9da6e99 MS |
1635 | do { |
1636 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1637 | if (ret) { | |
1638 | pr_err("Remapping memory failed: %d\n", ret); | |
1639 | return ret; | |
1640 | } | |
1641 | uaddr += PAGE_SIZE; | |
1642 | usize -= PAGE_SIZE; | |
1643 | } while (usize > 0); | |
4ce63fcd | 1644 | |
4ce63fcd MS |
1645 | return 0; |
1646 | } | |
56506822 GC |
1647 | static int arm_iommu_mmap_attrs(struct device *dev, |
1648 | struct vm_area_struct *vma, void *cpu_addr, | |
00085f1e | 1649 | dma_addr_t dma_addr, size_t size, unsigned long attrs) |
56506822 GC |
1650 | { |
1651 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
1652 | ||
1653 | return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs); | |
1654 | } | |
1655 | ||
1656 | static int arm_coherent_iommu_mmap_attrs(struct device *dev, | |
1657 | struct vm_area_struct *vma, void *cpu_addr, | |
00085f1e | 1658 | dma_addr_t dma_addr, size_t size, unsigned long attrs) |
56506822 GC |
1659 | { |
1660 | return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs); | |
1661 | } | |
4ce63fcd MS |
1662 | |
1663 | /* | |
1664 | * free a page as defined by the above mapping. | |
1665 | * Must not be called with IRQs disabled. | |
1666 | */ | |
56506822 | 1667 | void __arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 1668 | dma_addr_t handle, unsigned long attrs, int coherent_flag) |
4ce63fcd | 1669 | { |
836bfa0d | 1670 | struct page **pages; |
4ce63fcd MS |
1671 | size = PAGE_ALIGN(size); |
1672 | ||
56506822 GC |
1673 | if (coherent_flag == COHERENT || __in_atomic_pool(cpu_addr, size)) { |
1674 | __iommu_free_atomic(dev, cpu_addr, handle, size, coherent_flag); | |
e9da6e99 | 1675 | return; |
4ce63fcd | 1676 | } |
e9da6e99 | 1677 | |
836bfa0d YC |
1678 | pages = __iommu_get_pages(cpu_addr, attrs); |
1679 | if (!pages) { | |
1680 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
479ed93a HD |
1681 | return; |
1682 | } | |
1683 | ||
00085f1e | 1684 | if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0) { |
513510dd LA |
1685 | dma_common_free_remap(cpu_addr, size, |
1686 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
955c757e | 1687 | } |
e9da6e99 MS |
1688 | |
1689 | __iommu_remove_mapping(dev, handle, size); | |
549a17e4 | 1690 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1691 | } |
1692 | ||
56506822 | 1693 | void arm_iommu_free_attrs(struct device *dev, size_t size, |
00085f1e | 1694 | void *cpu_addr, dma_addr_t handle, unsigned long attrs) |
56506822 GC |
1695 | { |
1696 | __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, NORMAL); | |
1697 | } | |
1698 | ||
1699 | void arm_coherent_iommu_free_attrs(struct device *dev, size_t size, | |
00085f1e | 1700 | void *cpu_addr, dma_addr_t handle, unsigned long attrs) |
56506822 GC |
1701 | { |
1702 | __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, COHERENT); | |
1703 | } | |
1704 | ||
dc2832e1 MS |
1705 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1706 | void *cpu_addr, dma_addr_t dma_addr, | |
00085f1e | 1707 | size_t size, unsigned long attrs) |
dc2832e1 MS |
1708 | { |
1709 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1710 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1711 | ||
1712 | if (!pages) | |
1713 | return -ENXIO; | |
1714 | ||
1715 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1716 | GFP_KERNEL); | |
4ce63fcd MS |
1717 | } |
1718 | ||
1719 | /* | |
1720 | * Map a part of the scatter-gather list into contiguous io address space | |
1721 | */ | |
1722 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1723 | size_t size, dma_addr_t *handle, | |
00085f1e | 1724 | enum dma_data_direction dir, unsigned long attrs, |
0fa478df | 1725 | bool is_coherent) |
4ce63fcd | 1726 | { |
89cfdb19 | 1727 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1728 | dma_addr_t iova, iova_base; |
1729 | int ret = 0; | |
1730 | unsigned int count; | |
1731 | struct scatterlist *s; | |
c9b24996 | 1732 | int prot; |
4ce63fcd MS |
1733 | |
1734 | size = PAGE_ALIGN(size); | |
1735 | *handle = DMA_ERROR_CODE; | |
1736 | ||
1737 | iova_base = iova = __alloc_iova(mapping, size); | |
1738 | if (iova == DMA_ERROR_CODE) | |
1739 | return -ENOMEM; | |
1740 | ||
1741 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
3e6110fd | 1742 | phys_addr_t phys = page_to_phys(sg_page(s)); |
4ce63fcd MS |
1743 | unsigned int len = PAGE_ALIGN(s->offset + s->length); |
1744 | ||
00085f1e | 1745 | if (!is_coherent && (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
4ce63fcd MS |
1746 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1747 | ||
7d2822df | 1748 | prot = __dma_info_to_prot(dir, attrs); |
c9b24996 AH |
1749 | |
1750 | ret = iommu_map(mapping->domain, iova, phys, len, prot); | |
4ce63fcd MS |
1751 | if (ret < 0) |
1752 | goto fail; | |
1753 | count += len >> PAGE_SHIFT; | |
1754 | iova += len; | |
1755 | } | |
1756 | *handle = iova_base; | |
1757 | ||
1758 | return 0; | |
1759 | fail: | |
1760 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1761 | __free_iova(mapping, iova_base, size); | |
1762 | return ret; | |
1763 | } | |
1764 | ||
0fa478df | 1765 | static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
00085f1e | 1766 | enum dma_data_direction dir, unsigned long attrs, |
0fa478df | 1767 | bool is_coherent) |
4ce63fcd MS |
1768 | { |
1769 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1770 | int i, count = 0; | |
1771 | unsigned int offset = s->offset; | |
1772 | unsigned int size = s->offset + s->length; | |
1773 | unsigned int max = dma_get_max_seg_size(dev); | |
1774 | ||
1775 | for (i = 1; i < nents; i++) { | |
1776 | s = sg_next(s); | |
1777 | ||
1778 | s->dma_address = DMA_ERROR_CODE; | |
1779 | s->dma_length = 0; | |
1780 | ||
1781 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1782 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
0fa478df | 1783 | dir, attrs, is_coherent) < 0) |
4ce63fcd MS |
1784 | goto bad_mapping; |
1785 | ||
1786 | dma->dma_address += offset; | |
1787 | dma->dma_length = size - offset; | |
1788 | ||
1789 | size = offset = s->offset; | |
1790 | start = s; | |
1791 | dma = sg_next(dma); | |
1792 | count += 1; | |
1793 | } | |
1794 | size += s->length; | |
1795 | } | |
0fa478df RH |
1796 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs, |
1797 | is_coherent) < 0) | |
4ce63fcd MS |
1798 | goto bad_mapping; |
1799 | ||
1800 | dma->dma_address += offset; | |
1801 | dma->dma_length = size - offset; | |
1802 | ||
1803 | return count+1; | |
1804 | ||
1805 | bad_mapping: | |
1806 | for_each_sg(sg, s, count, i) | |
1807 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1808 | return 0; | |
1809 | } | |
1810 | ||
1811 | /** | |
0fa478df | 1812 | * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA |
4ce63fcd MS |
1813 | * @dev: valid struct device pointer |
1814 | * @sg: list of buffers | |
0fa478df RH |
1815 | * @nents: number of buffers to map |
1816 | * @dir: DMA transfer direction | |
4ce63fcd | 1817 | * |
0fa478df RH |
1818 | * Map a set of i/o coherent buffers described by scatterlist in streaming |
1819 | * mode for DMA. The scatter gather list elements are merged together (if | |
1820 | * possible) and tagged with the appropriate dma address and length. They are | |
1821 | * obtained via sg_dma_{address,length}. | |
4ce63fcd | 1822 | */ |
0fa478df | 1823 | int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg, |
00085f1e | 1824 | int nents, enum dma_data_direction dir, unsigned long attrs) |
0fa478df RH |
1825 | { |
1826 | return __iommu_map_sg(dev, sg, nents, dir, attrs, true); | |
1827 | } | |
1828 | ||
1829 | /** | |
1830 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1831 | * @dev: valid struct device pointer | |
1832 | * @sg: list of buffers | |
1833 | * @nents: number of buffers to map | |
1834 | * @dir: DMA transfer direction | |
1835 | * | |
1836 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1837 | * The scatter gather list elements are merged together (if possible) and | |
1838 | * tagged with the appropriate dma address and length. They are obtained via | |
1839 | * sg_dma_{address,length}. | |
1840 | */ | |
1841 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, | |
00085f1e | 1842 | int nents, enum dma_data_direction dir, unsigned long attrs) |
0fa478df RH |
1843 | { |
1844 | return __iommu_map_sg(dev, sg, nents, dir, attrs, false); | |
1845 | } | |
1846 | ||
1847 | static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
00085f1e KK |
1848 | int nents, enum dma_data_direction dir, |
1849 | unsigned long attrs, bool is_coherent) | |
4ce63fcd MS |
1850 | { |
1851 | struct scatterlist *s; | |
1852 | int i; | |
1853 | ||
1854 | for_each_sg(sg, s, nents, i) { | |
1855 | if (sg_dma_len(s)) | |
1856 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1857 | sg_dma_len(s)); | |
00085f1e | 1858 | if (!is_coherent && (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
4ce63fcd MS |
1859 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1860 | s->length, dir); | |
1861 | } | |
1862 | } | |
1863 | ||
0fa478df RH |
1864 | /** |
1865 | * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1866 | * @dev: valid struct device pointer | |
1867 | * @sg: list of buffers | |
1868 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1869 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1870 | * | |
1871 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1872 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1873 | */ | |
1874 | void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
00085f1e KK |
1875 | int nents, enum dma_data_direction dir, |
1876 | unsigned long attrs) | |
0fa478df RH |
1877 | { |
1878 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, true); | |
1879 | } | |
1880 | ||
1881 | /** | |
1882 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1883 | * @dev: valid struct device pointer | |
1884 | * @sg: list of buffers | |
1885 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1886 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1887 | * | |
1888 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1889 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1890 | */ | |
1891 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
00085f1e KK |
1892 | enum dma_data_direction dir, |
1893 | unsigned long attrs) | |
0fa478df RH |
1894 | { |
1895 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, false); | |
1896 | } | |
1897 | ||
4ce63fcd MS |
1898 | /** |
1899 | * arm_iommu_sync_sg_for_cpu | |
1900 | * @dev: valid struct device pointer | |
1901 | * @sg: list of buffers | |
1902 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1903 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1904 | */ | |
1905 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1906 | int nents, enum dma_data_direction dir) | |
1907 | { | |
1908 | struct scatterlist *s; | |
1909 | int i; | |
1910 | ||
1911 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1912 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1913 | |
1914 | } | |
1915 | ||
1916 | /** | |
1917 | * arm_iommu_sync_sg_for_device | |
1918 | * @dev: valid struct device pointer | |
1919 | * @sg: list of buffers | |
1920 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1921 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1922 | */ | |
1923 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1924 | int nents, enum dma_data_direction dir) | |
1925 | { | |
1926 | struct scatterlist *s; | |
1927 | int i; | |
1928 | ||
1929 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1930 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1931 | } |
1932 | ||
1933 | ||
1934 | /** | |
0fa478df | 1935 | * arm_coherent_iommu_map_page |
4ce63fcd MS |
1936 | * @dev: valid struct device pointer |
1937 | * @page: page that buffer resides in | |
1938 | * @offset: offset into page for start of buffer | |
1939 | * @size: size of buffer to map | |
1940 | * @dir: DMA transfer direction | |
1941 | * | |
0fa478df | 1942 | * Coherent IOMMU aware version of arm_dma_map_page() |
4ce63fcd | 1943 | */ |
0fa478df | 1944 | static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page, |
4ce63fcd | 1945 | unsigned long offset, size_t size, enum dma_data_direction dir, |
00085f1e | 1946 | unsigned long attrs) |
4ce63fcd | 1947 | { |
89cfdb19 | 1948 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd | 1949 | dma_addr_t dma_addr; |
13987d68 | 1950 | int ret, prot, len = PAGE_ALIGN(size + offset); |
4ce63fcd | 1951 | |
4ce63fcd MS |
1952 | dma_addr = __alloc_iova(mapping, len); |
1953 | if (dma_addr == DMA_ERROR_CODE) | |
1954 | return dma_addr; | |
1955 | ||
7d2822df | 1956 | prot = __dma_info_to_prot(dir, attrs); |
13987d68 WD |
1957 | |
1958 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot); | |
4ce63fcd MS |
1959 | if (ret < 0) |
1960 | goto fail; | |
1961 | ||
1962 | return dma_addr + offset; | |
1963 | fail: | |
1964 | __free_iova(mapping, dma_addr, len); | |
1965 | return DMA_ERROR_CODE; | |
1966 | } | |
1967 | ||
0fa478df RH |
1968 | /** |
1969 | * arm_iommu_map_page | |
1970 | * @dev: valid struct device pointer | |
1971 | * @page: page that buffer resides in | |
1972 | * @offset: offset into page for start of buffer | |
1973 | * @size: size of buffer to map | |
1974 | * @dir: DMA transfer direction | |
1975 | * | |
1976 | * IOMMU aware version of arm_dma_map_page() | |
1977 | */ | |
1978 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1979 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
00085f1e | 1980 | unsigned long attrs) |
0fa478df | 1981 | { |
00085f1e | 1982 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
0fa478df RH |
1983 | __dma_page_cpu_to_dev(page, offset, size, dir); |
1984 | ||
1985 | return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs); | |
1986 | } | |
1987 | ||
1988 | /** | |
1989 | * arm_coherent_iommu_unmap_page | |
1990 | * @dev: valid struct device pointer | |
1991 | * @handle: DMA address of buffer | |
1992 | * @size: size of buffer (same as passed to dma_map_page) | |
1993 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1994 | * | |
1995 | * Coherent IOMMU aware version of arm_dma_unmap_page() | |
1996 | */ | |
1997 | static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
00085f1e | 1998 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
0fa478df | 1999 | { |
89cfdb19 | 2000 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
0fa478df | 2001 | dma_addr_t iova = handle & PAGE_MASK; |
0fa478df RH |
2002 | int offset = handle & ~PAGE_MASK; |
2003 | int len = PAGE_ALIGN(size + offset); | |
2004 | ||
2005 | if (!iova) | |
2006 | return; | |
2007 | ||
2008 | iommu_unmap(mapping->domain, iova, len); | |
2009 | __free_iova(mapping, iova, len); | |
2010 | } | |
2011 | ||
4ce63fcd MS |
2012 | /** |
2013 | * arm_iommu_unmap_page | |
2014 | * @dev: valid struct device pointer | |
2015 | * @handle: DMA address of buffer | |
2016 | * @size: size of buffer (same as passed to dma_map_page) | |
2017 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
2018 | * | |
2019 | * IOMMU aware version of arm_dma_unmap_page() | |
2020 | */ | |
2021 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
00085f1e | 2022 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
4ce63fcd | 2023 | { |
89cfdb19 | 2024 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
2025 | dma_addr_t iova = handle & PAGE_MASK; |
2026 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
2027 | int offset = handle & ~PAGE_MASK; | |
2028 | int len = PAGE_ALIGN(size + offset); | |
2029 | ||
2030 | if (!iova) | |
2031 | return; | |
2032 | ||
00085f1e | 2033 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
4ce63fcd MS |
2034 | __dma_page_dev_to_cpu(page, offset, size, dir); |
2035 | ||
2036 | iommu_unmap(mapping->domain, iova, len); | |
2037 | __free_iova(mapping, iova, len); | |
2038 | } | |
2039 | ||
24ed5d2c NS |
2040 | /** |
2041 | * arm_iommu_map_resource - map a device resource for DMA | |
2042 | * @dev: valid struct device pointer | |
2043 | * @phys_addr: physical address of resource | |
2044 | * @size: size of resource to map | |
2045 | * @dir: DMA transfer direction | |
2046 | */ | |
2047 | static dma_addr_t arm_iommu_map_resource(struct device *dev, | |
2048 | phys_addr_t phys_addr, size_t size, | |
2049 | enum dma_data_direction dir, unsigned long attrs) | |
2050 | { | |
2051 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
2052 | dma_addr_t dma_addr; | |
2053 | int ret, prot; | |
2054 | phys_addr_t addr = phys_addr & PAGE_MASK; | |
2055 | unsigned int offset = phys_addr & ~PAGE_MASK; | |
2056 | size_t len = PAGE_ALIGN(size + offset); | |
2057 | ||
2058 | dma_addr = __alloc_iova(mapping, len); | |
2059 | if (dma_addr == DMA_ERROR_CODE) | |
2060 | return dma_addr; | |
2061 | ||
7d2822df | 2062 | prot = __dma_info_to_prot(dir, attrs) | IOMMU_MMIO; |
24ed5d2c NS |
2063 | |
2064 | ret = iommu_map(mapping->domain, dma_addr, addr, len, prot); | |
2065 | if (ret < 0) | |
2066 | goto fail; | |
2067 | ||
2068 | return dma_addr + offset; | |
2069 | fail: | |
2070 | __free_iova(mapping, dma_addr, len); | |
2071 | return DMA_ERROR_CODE; | |
2072 | } | |
2073 | ||
2074 | /** | |
2075 | * arm_iommu_unmap_resource - unmap a device DMA resource | |
2076 | * @dev: valid struct device pointer | |
2077 | * @dma_handle: DMA address to resource | |
2078 | * @size: size of resource to map | |
2079 | * @dir: DMA transfer direction | |
2080 | */ | |
2081 | static void arm_iommu_unmap_resource(struct device *dev, dma_addr_t dma_handle, | |
2082 | size_t size, enum dma_data_direction dir, | |
2083 | unsigned long attrs) | |
2084 | { | |
2085 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
2086 | dma_addr_t iova = dma_handle & PAGE_MASK; | |
2087 | unsigned int offset = dma_handle & ~PAGE_MASK; | |
2088 | size_t len = PAGE_ALIGN(size + offset); | |
2089 | ||
2090 | if (!iova) | |
2091 | return; | |
2092 | ||
2093 | iommu_unmap(mapping->domain, iova, len); | |
2094 | __free_iova(mapping, iova, len); | |
2095 | } | |
2096 | ||
4ce63fcd MS |
2097 | static void arm_iommu_sync_single_for_cpu(struct device *dev, |
2098 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
2099 | { | |
89cfdb19 | 2100 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
2101 | dma_addr_t iova = handle & PAGE_MASK; |
2102 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
2103 | unsigned int offset = handle & ~PAGE_MASK; | |
2104 | ||
2105 | if (!iova) | |
2106 | return; | |
2107 | ||
0fa478df | 2108 | __dma_page_dev_to_cpu(page, offset, size, dir); |
4ce63fcd MS |
2109 | } |
2110 | ||
2111 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
2112 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
2113 | { | |
89cfdb19 | 2114 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
2115 | dma_addr_t iova = handle & PAGE_MASK; |
2116 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
2117 | unsigned int offset = handle & ~PAGE_MASK; | |
2118 | ||
2119 | if (!iova) | |
2120 | return; | |
2121 | ||
2122 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
2123 | } | |
2124 | ||
5299709d | 2125 | const struct dma_map_ops iommu_ops = { |
4ce63fcd MS |
2126 | .alloc = arm_iommu_alloc_attrs, |
2127 | .free = arm_iommu_free_attrs, | |
2128 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 2129 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
2130 | |
2131 | .map_page = arm_iommu_map_page, | |
2132 | .unmap_page = arm_iommu_unmap_page, | |
2133 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
2134 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
2135 | ||
2136 | .map_sg = arm_iommu_map_sg, | |
2137 | .unmap_sg = arm_iommu_unmap_sg, | |
2138 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
2139 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
24ed5d2c NS |
2140 | |
2141 | .map_resource = arm_iommu_map_resource, | |
2142 | .unmap_resource = arm_iommu_unmap_resource, | |
4ce63fcd MS |
2143 | }; |
2144 | ||
5299709d | 2145 | const struct dma_map_ops iommu_coherent_ops = { |
56506822 GC |
2146 | .alloc = arm_coherent_iommu_alloc_attrs, |
2147 | .free = arm_coherent_iommu_free_attrs, | |
2148 | .mmap = arm_coherent_iommu_mmap_attrs, | |
0fa478df RH |
2149 | .get_sgtable = arm_iommu_get_sgtable, |
2150 | ||
2151 | .map_page = arm_coherent_iommu_map_page, | |
2152 | .unmap_page = arm_coherent_iommu_unmap_page, | |
2153 | ||
2154 | .map_sg = arm_coherent_iommu_map_sg, | |
2155 | .unmap_sg = arm_coherent_iommu_unmap_sg, | |
24ed5d2c NS |
2156 | |
2157 | .map_resource = arm_iommu_map_resource, | |
2158 | .unmap_resource = arm_iommu_unmap_resource, | |
0fa478df RH |
2159 | }; |
2160 | ||
4ce63fcd MS |
2161 | /** |
2162 | * arm_iommu_create_mapping | |
2163 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
2164 | * @base: start address of the valid IO address space | |
68efd7d2 | 2165 | * @size: maximum size of the valid IO address space |
4ce63fcd MS |
2166 | * |
2167 | * Creates a mapping structure which holds information about used/unused | |
2168 | * IO address ranges, which is required to perform memory allocation and | |
2169 | * mapping with IOMMU aware functions. | |
2170 | * | |
2171 | * The client device need to be attached to the mapping with | |
2172 | * arm_iommu_attach_device function. | |
2173 | */ | |
2174 | struct dma_iommu_mapping * | |
1424532b | 2175 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size) |
4ce63fcd | 2176 | { |
68efd7d2 MS |
2177 | unsigned int bits = size >> PAGE_SHIFT; |
2178 | unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); | |
4ce63fcd | 2179 | struct dma_iommu_mapping *mapping; |
68efd7d2 | 2180 | int extensions = 1; |
4ce63fcd MS |
2181 | int err = -ENOMEM; |
2182 | ||
1424532b MS |
2183 | /* currently only 32-bit DMA address space is supported */ |
2184 | if (size > DMA_BIT_MASK(32) + 1) | |
2185 | return ERR_PTR(-ERANGE); | |
2186 | ||
68efd7d2 | 2187 | if (!bitmap_size) |
4ce63fcd MS |
2188 | return ERR_PTR(-EINVAL); |
2189 | ||
68efd7d2 MS |
2190 | if (bitmap_size > PAGE_SIZE) { |
2191 | extensions = bitmap_size / PAGE_SIZE; | |
2192 | bitmap_size = PAGE_SIZE; | |
2193 | } | |
2194 | ||
4ce63fcd MS |
2195 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); |
2196 | if (!mapping) | |
2197 | goto err; | |
2198 | ||
68efd7d2 MS |
2199 | mapping->bitmap_size = bitmap_size; |
2200 | mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *), | |
4d852ef8 AH |
2201 | GFP_KERNEL); |
2202 | if (!mapping->bitmaps) | |
4ce63fcd MS |
2203 | goto err2; |
2204 | ||
68efd7d2 | 2205 | mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL); |
4d852ef8 AH |
2206 | if (!mapping->bitmaps[0]) |
2207 | goto err3; | |
2208 | ||
2209 | mapping->nr_bitmaps = 1; | |
2210 | mapping->extensions = extensions; | |
4ce63fcd | 2211 | mapping->base = base; |
68efd7d2 | 2212 | mapping->bits = BITS_PER_BYTE * bitmap_size; |
4d852ef8 | 2213 | |
4ce63fcd MS |
2214 | spin_lock_init(&mapping->lock); |
2215 | ||
2216 | mapping->domain = iommu_domain_alloc(bus); | |
2217 | if (!mapping->domain) | |
4d852ef8 | 2218 | goto err4; |
4ce63fcd MS |
2219 | |
2220 | kref_init(&mapping->kref); | |
2221 | return mapping; | |
4d852ef8 AH |
2222 | err4: |
2223 | kfree(mapping->bitmaps[0]); | |
4ce63fcd | 2224 | err3: |
4d852ef8 | 2225 | kfree(mapping->bitmaps); |
4ce63fcd MS |
2226 | err2: |
2227 | kfree(mapping); | |
2228 | err: | |
2229 | return ERR_PTR(err); | |
2230 | } | |
18177d12 | 2231 | EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); |
4ce63fcd MS |
2232 | |
2233 | static void release_iommu_mapping(struct kref *kref) | |
2234 | { | |
4d852ef8 | 2235 | int i; |
4ce63fcd MS |
2236 | struct dma_iommu_mapping *mapping = |
2237 | container_of(kref, struct dma_iommu_mapping, kref); | |
2238 | ||
2239 | iommu_domain_free(mapping->domain); | |
4d852ef8 AH |
2240 | for (i = 0; i < mapping->nr_bitmaps; i++) |
2241 | kfree(mapping->bitmaps[i]); | |
2242 | kfree(mapping->bitmaps); | |
4ce63fcd MS |
2243 | kfree(mapping); |
2244 | } | |
2245 | ||
4d852ef8 AH |
2246 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) |
2247 | { | |
2248 | int next_bitmap; | |
2249 | ||
462859aa | 2250 | if (mapping->nr_bitmaps >= mapping->extensions) |
4d852ef8 AH |
2251 | return -EINVAL; |
2252 | ||
2253 | next_bitmap = mapping->nr_bitmaps; | |
2254 | mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size, | |
2255 | GFP_ATOMIC); | |
2256 | if (!mapping->bitmaps[next_bitmap]) | |
2257 | return -ENOMEM; | |
2258 | ||
2259 | mapping->nr_bitmaps++; | |
2260 | ||
2261 | return 0; | |
2262 | } | |
2263 | ||
4ce63fcd MS |
2264 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) |
2265 | { | |
2266 | if (mapping) | |
2267 | kref_put(&mapping->kref, release_iommu_mapping); | |
2268 | } | |
18177d12 | 2269 | EXPORT_SYMBOL_GPL(arm_iommu_release_mapping); |
4ce63fcd | 2270 | |
eab8d653 LP |
2271 | static int __arm_iommu_attach_device(struct device *dev, |
2272 | struct dma_iommu_mapping *mapping) | |
2273 | { | |
2274 | int err; | |
2275 | ||
2276 | err = iommu_attach_device(mapping->domain, dev); | |
2277 | if (err) | |
2278 | return err; | |
2279 | ||
2280 | kref_get(&mapping->kref); | |
89cfdb19 | 2281 | to_dma_iommu_mapping(dev) = mapping; |
eab8d653 LP |
2282 | |
2283 | pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
2284 | return 0; | |
2285 | } | |
2286 | ||
4ce63fcd MS |
2287 | /** |
2288 | * arm_iommu_attach_device | |
2289 | * @dev: valid struct device pointer | |
2290 | * @mapping: io address space mapping structure (returned from | |
2291 | * arm_iommu_create_mapping) | |
2292 | * | |
eab8d653 LP |
2293 | * Attaches specified io address space mapping to the provided device. |
2294 | * This replaces the dma operations (dma_map_ops pointer) with the | |
2295 | * IOMMU aware version. | |
2296 | * | |
4bb25789 WD |
2297 | * More than one client might be attached to the same io address space |
2298 | * mapping. | |
4ce63fcd MS |
2299 | */ |
2300 | int arm_iommu_attach_device(struct device *dev, | |
2301 | struct dma_iommu_mapping *mapping) | |
2302 | { | |
2303 | int err; | |
2304 | ||
eab8d653 | 2305 | err = __arm_iommu_attach_device(dev, mapping); |
4ce63fcd MS |
2306 | if (err) |
2307 | return err; | |
2308 | ||
eab8d653 | 2309 | set_dma_ops(dev, &iommu_ops); |
4ce63fcd MS |
2310 | return 0; |
2311 | } | |
18177d12 | 2312 | EXPORT_SYMBOL_GPL(arm_iommu_attach_device); |
4ce63fcd | 2313 | |
eab8d653 | 2314 | static void __arm_iommu_detach_device(struct device *dev) |
6fe36758 HD |
2315 | { |
2316 | struct dma_iommu_mapping *mapping; | |
2317 | ||
2318 | mapping = to_dma_iommu_mapping(dev); | |
2319 | if (!mapping) { | |
2320 | dev_warn(dev, "Not attached\n"); | |
2321 | return; | |
2322 | } | |
2323 | ||
2324 | iommu_detach_device(mapping->domain, dev); | |
2325 | kref_put(&mapping->kref, release_iommu_mapping); | |
89cfdb19 | 2326 | to_dma_iommu_mapping(dev) = NULL; |
6fe36758 HD |
2327 | |
2328 | pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev)); | |
2329 | } | |
eab8d653 LP |
2330 | |
2331 | /** | |
2332 | * arm_iommu_detach_device | |
2333 | * @dev: valid struct device pointer | |
2334 | * | |
2335 | * Detaches the provided device from a previously attached map. | |
2336 | * This voids the dma operations (dma_map_ops pointer) | |
2337 | */ | |
2338 | void arm_iommu_detach_device(struct device *dev) | |
2339 | { | |
2340 | __arm_iommu_detach_device(dev); | |
2341 | set_dma_ops(dev, NULL); | |
2342 | } | |
18177d12 | 2343 | EXPORT_SYMBOL_GPL(arm_iommu_detach_device); |
6fe36758 | 2344 | |
5299709d | 2345 | static const struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent) |
4bb25789 WD |
2346 | { |
2347 | return coherent ? &iommu_coherent_ops : &iommu_ops; | |
2348 | } | |
2349 | ||
2350 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
53c92d79 | 2351 | const struct iommu_ops *iommu) |
4bb25789 WD |
2352 | { |
2353 | struct dma_iommu_mapping *mapping; | |
2354 | ||
2355 | if (!iommu) | |
2356 | return false; | |
2357 | ||
2358 | mapping = arm_iommu_create_mapping(dev->bus, dma_base, size); | |
2359 | if (IS_ERR(mapping)) { | |
2360 | pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n", | |
2361 | size, dev_name(dev)); | |
2362 | return false; | |
2363 | } | |
2364 | ||
eab8d653 | 2365 | if (__arm_iommu_attach_device(dev, mapping)) { |
4bb25789 WD |
2366 | pr_warn("Failed to attached device %s to IOMMU_mapping\n", |
2367 | dev_name(dev)); | |
2368 | arm_iommu_release_mapping(mapping); | |
2369 | return false; | |
2370 | } | |
2371 | ||
2372 | return true; | |
2373 | } | |
2374 | ||
2375 | static void arm_teardown_iommu_dma_ops(struct device *dev) | |
2376 | { | |
89cfdb19 | 2377 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4bb25789 | 2378 | |
c2273a18 WD |
2379 | if (!mapping) |
2380 | return; | |
2381 | ||
eab8d653 | 2382 | __arm_iommu_detach_device(dev); |
4bb25789 WD |
2383 | arm_iommu_release_mapping(mapping); |
2384 | } | |
2385 | ||
2386 | #else | |
2387 | ||
2388 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
53c92d79 | 2389 | const struct iommu_ops *iommu) |
4bb25789 WD |
2390 | { |
2391 | return false; | |
2392 | } | |
2393 | ||
2394 | static void arm_teardown_iommu_dma_ops(struct device *dev) { } | |
2395 | ||
2396 | #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops | |
2397 | ||
2398 | #endif /* CONFIG_ARM_DMA_USE_IOMMU */ | |
2399 | ||
5299709d | 2400 | static const struct dma_map_ops *arm_get_dma_map_ops(bool coherent) |
4bb25789 WD |
2401 | { |
2402 | return coherent ? &arm_coherent_dma_ops : &arm_dma_ops; | |
2403 | } | |
2404 | ||
2405 | void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
53c92d79 | 2406 | const struct iommu_ops *iommu, bool coherent) |
4bb25789 | 2407 | { |
5299709d | 2408 | const struct dma_map_ops *dma_ops; |
4bb25789 | 2409 | |
6f51ee70 | 2410 | dev->archdata.dma_coherent = coherent; |
4bb25789 WD |
2411 | if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) |
2412 | dma_ops = arm_get_iommu_dma_map_ops(coherent); | |
2413 | else | |
2414 | dma_ops = arm_get_dma_map_ops(coherent); | |
2415 | ||
2416 | set_dma_ops(dev, dma_ops); | |
2417 | } | |
2418 | ||
2419 | void arch_teardown_dma_ops(struct device *dev) | |
2420 | { | |
2421 | arm_teardown_iommu_dma_ops(dev); | |
2422 | } |