]>
Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
11a5aa32 | 12 | #include <linux/bootmem.h> |
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/mm.h> | |
36d0fd21 | 15 | #include <linux/genalloc.h> |
5a0e3ad6 | 16 | #include <linux/gfp.h> |
1da177e4 LT |
17 | #include <linux/errno.h> |
18 | #include <linux/list.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/dma-mapping.h> | |
c7909509 | 22 | #include <linux/dma-contiguous.h> |
39af22a7 | 23 | #include <linux/highmem.h> |
c7909509 | 24 | #include <linux/memblock.h> |
99d1717d | 25 | #include <linux/slab.h> |
4ce63fcd | 26 | #include <linux/iommu.h> |
e9da6e99 | 27 | #include <linux/io.h> |
4ce63fcd | 28 | #include <linux/vmalloc.h> |
158e8bfe | 29 | #include <linux/sizes.h> |
a254129e | 30 | #include <linux/cma.h> |
1da177e4 | 31 | |
23759dc6 | 32 | #include <asm/memory.h> |
43377453 | 33 | #include <asm/highmem.h> |
1da177e4 | 34 | #include <asm/cacheflush.h> |
1da177e4 | 35 | #include <asm/tlbflush.h> |
99d1717d | 36 | #include <asm/mach/arch.h> |
4ce63fcd | 37 | #include <asm/dma-iommu.h> |
c7909509 MS |
38 | #include <asm/mach/map.h> |
39 | #include <asm/system_info.h> | |
40 | #include <asm/dma-contiguous.h> | |
37134cd5 | 41 | |
1234e3fd | 42 | #include "dma.h" |
022ae537 RK |
43 | #include "mm.h" |
44 | ||
b4268676 RV |
45 | struct arm_dma_alloc_args { |
46 | struct device *dev; | |
47 | size_t size; | |
48 | gfp_t gfp; | |
49 | pgprot_t prot; | |
50 | const void *caller; | |
51 | bool want_vaddr; | |
52 | }; | |
53 | ||
54 | struct arm_dma_free_args { | |
55 | struct device *dev; | |
56 | size_t size; | |
57 | void *cpu_addr; | |
58 | struct page *page; | |
59 | bool want_vaddr; | |
60 | }; | |
61 | ||
62 | struct arm_dma_allocator { | |
63 | void *(*alloc)(struct arm_dma_alloc_args *args, | |
64 | struct page **ret_page); | |
65 | void (*free)(struct arm_dma_free_args *args); | |
66 | }; | |
67 | ||
19e6e5e5 RV |
68 | struct arm_dma_buffer { |
69 | struct list_head list; | |
70 | void *virt; | |
b4268676 | 71 | struct arm_dma_allocator *allocator; |
19e6e5e5 RV |
72 | }; |
73 | ||
74 | static LIST_HEAD(arm_dma_bufs); | |
75 | static DEFINE_SPINLOCK(arm_dma_bufs_lock); | |
76 | ||
77 | static struct arm_dma_buffer *arm_dma_buffer_find(void *virt) | |
78 | { | |
79 | struct arm_dma_buffer *buf, *found = NULL; | |
80 | unsigned long flags; | |
81 | ||
82 | spin_lock_irqsave(&arm_dma_bufs_lock, flags); | |
83 | list_for_each_entry(buf, &arm_dma_bufs, list) { | |
84 | if (buf->virt == virt) { | |
85 | list_del(&buf->list); | |
86 | found = buf; | |
87 | break; | |
88 | } | |
89 | } | |
90 | spin_unlock_irqrestore(&arm_dma_bufs_lock, flags); | |
91 | return found; | |
92 | } | |
93 | ||
15237e1f MS |
94 | /* |
95 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
96 | * is either exclusively owned by the CPU (and therefore may be accessed | |
97 | * by it) or exclusively owned by the DMA device. These helper functions | |
98 | * represent the transitions between these two ownership states. | |
99 | * | |
100 | * Note, however, that on later ARMs, this notion does not work due to | |
101 | * speculative prefetches. We model our approach on the assumption that | |
102 | * the CPU does do speculative prefetches, which means we clean caches | |
103 | * before transfers and delay cache invalidation until transfer completion. | |
104 | * | |
15237e1f | 105 | */ |
51fde349 | 106 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 107 | size_t, enum dma_data_direction); |
51fde349 | 108 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
109 | size_t, enum dma_data_direction); |
110 | ||
2dc6a016 MS |
111 | /** |
112 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
113 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
114 | * @page: page that buffer resides in | |
115 | * @offset: offset into page for start of buffer | |
116 | * @size: size of buffer to map | |
117 | * @dir: DMA transfer direction | |
118 | * | |
119 | * Ensure that any data held in the cache is appropriately discarded | |
120 | * or written back. | |
121 | * | |
122 | * The device owns this memory once this call has completed. The CPU | |
123 | * can regain ownership by calling dma_unmap_page(). | |
124 | */ | |
51fde349 | 125 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
126 | unsigned long offset, size_t size, enum dma_data_direction dir, |
127 | struct dma_attrs *attrs) | |
128 | { | |
dd37e940 | 129 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
130 | __dma_page_cpu_to_dev(page, offset, size, dir); |
131 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
132 | } |
133 | ||
dd37e940 RH |
134 | static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page, |
135 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
136 | struct dma_attrs *attrs) | |
137 | { | |
138 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
139 | } | |
140 | ||
2dc6a016 MS |
141 | /** |
142 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
143 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
144 | * @handle: DMA address of buffer | |
145 | * @size: size of buffer (same as passed to dma_map_page) | |
146 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
147 | * | |
148 | * Unmap a page streaming mode DMA translation. The handle and size | |
149 | * must match what was provided in the previous dma_map_page() call. | |
150 | * All other usages are undefined. | |
151 | * | |
152 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
153 | * whatever the device wrote there. | |
154 | */ | |
51fde349 | 155 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
156 | size_t size, enum dma_data_direction dir, |
157 | struct dma_attrs *attrs) | |
158 | { | |
dd37e940 | 159 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
160 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
161 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
162 | } |
163 | ||
51fde349 | 164 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
165 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
166 | { | |
167 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
168 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 169 | __dma_page_dev_to_cpu(page, offset, size, dir); |
2dc6a016 MS |
170 | } |
171 | ||
51fde349 | 172 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
173 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
174 | { | |
175 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
176 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 177 | __dma_page_cpu_to_dev(page, offset, size, dir); |
2dc6a016 MS |
178 | } |
179 | ||
2dc6a016 | 180 | struct dma_map_ops arm_dma_ops = { |
f99d6034 MS |
181 | .alloc = arm_dma_alloc, |
182 | .free = arm_dma_free, | |
183 | .mmap = arm_dma_mmap, | |
dc2832e1 | 184 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
185 | .map_page = arm_dma_map_page, |
186 | .unmap_page = arm_dma_unmap_page, | |
187 | .map_sg = arm_dma_map_sg, | |
188 | .unmap_sg = arm_dma_unmap_sg, | |
189 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
190 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
191 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
192 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
2dc6a016 MS |
193 | }; |
194 | EXPORT_SYMBOL(arm_dma_ops); | |
195 | ||
dd37e940 RH |
196 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, |
197 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs); | |
198 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
199 | dma_addr_t handle, struct dma_attrs *attrs); | |
55af8a91 ML |
200 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
201 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
202 | struct dma_attrs *attrs); | |
dd37e940 RH |
203 | |
204 | struct dma_map_ops arm_coherent_dma_ops = { | |
205 | .alloc = arm_coherent_dma_alloc, | |
206 | .free = arm_coherent_dma_free, | |
55af8a91 | 207 | .mmap = arm_coherent_dma_mmap, |
dd37e940 RH |
208 | .get_sgtable = arm_dma_get_sgtable, |
209 | .map_page = arm_coherent_dma_map_page, | |
210 | .map_sg = arm_dma_map_sg, | |
dd37e940 RH |
211 | }; |
212 | EXPORT_SYMBOL(arm_coherent_dma_ops); | |
213 | ||
9f28cde0 RK |
214 | static int __dma_supported(struct device *dev, u64 mask, bool warn) |
215 | { | |
216 | unsigned long max_dma_pfn; | |
217 | ||
218 | /* | |
219 | * If the mask allows for more memory than we can address, | |
220 | * and we actually have that much memory, then we must | |
221 | * indicate that DMA to this device is not supported. | |
222 | */ | |
223 | if (sizeof(mask) != sizeof(dma_addr_t) && | |
224 | mask > (dma_addr_t)~0 && | |
8bf1268f | 225 | dma_to_pfn(dev, ~0) < max_pfn - 1) { |
9f28cde0 RK |
226 | if (warn) { |
227 | dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", | |
228 | mask); | |
229 | dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n"); | |
230 | } | |
231 | return 0; | |
232 | } | |
233 | ||
234 | max_dma_pfn = min(max_pfn, arm_dma_pfn_limit); | |
235 | ||
236 | /* | |
237 | * Translate the device's DMA mask to a PFN limit. This | |
238 | * PFN number includes the page which we can DMA to. | |
239 | */ | |
240 | if (dma_to_pfn(dev, mask) < max_dma_pfn) { | |
241 | if (warn) | |
242 | dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", | |
243 | mask, | |
244 | dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, | |
245 | max_dma_pfn + 1); | |
246 | return 0; | |
247 | } | |
248 | ||
249 | return 1; | |
250 | } | |
251 | ||
ab6494f0 CM |
252 | static u64 get_coherent_dma_mask(struct device *dev) |
253 | { | |
4dcfa600 | 254 | u64 mask = (u64)DMA_BIT_MASK(32); |
ab6494f0 CM |
255 | |
256 | if (dev) { | |
257 | mask = dev->coherent_dma_mask; | |
258 | ||
259 | /* | |
260 | * Sanity check the DMA mask - it must be non-zero, and | |
261 | * must be able to be satisfied by a DMA allocation. | |
262 | */ | |
263 | if (mask == 0) { | |
264 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
265 | return 0; | |
266 | } | |
267 | ||
9f28cde0 | 268 | if (!__dma_supported(dev, mask, true)) |
ab6494f0 | 269 | return 0; |
ab6494f0 | 270 | } |
1da177e4 | 271 | |
ab6494f0 CM |
272 | return mask; |
273 | } | |
274 | ||
c7909509 MS |
275 | static void __dma_clear_buffer(struct page *page, size_t size) |
276 | { | |
c7909509 MS |
277 | /* |
278 | * Ensure that the allocated pages are zeroed, and that any data | |
279 | * lurking in the kernel direct-mapped region is invalidated. | |
280 | */ | |
9848e48f MS |
281 | if (PageHighMem(page)) { |
282 | phys_addr_t base = __pfn_to_phys(page_to_pfn(page)); | |
283 | phys_addr_t end = base + size; | |
284 | while (size > 0) { | |
285 | void *ptr = kmap_atomic(page); | |
286 | memset(ptr, 0, PAGE_SIZE); | |
287 | dmac_flush_range(ptr, ptr + PAGE_SIZE); | |
288 | kunmap_atomic(ptr); | |
289 | page++; | |
290 | size -= PAGE_SIZE; | |
291 | } | |
292 | outer_flush_range(base, end); | |
293 | } else { | |
294 | void *ptr = page_address(page); | |
4ce63fcd MS |
295 | memset(ptr, 0, size); |
296 | dmac_flush_range(ptr, ptr + size); | |
297 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
298 | } | |
c7909509 MS |
299 | } |
300 | ||
7a9a32a9 RK |
301 | /* |
302 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
303 | * specified gfp mask. Note that 'size' must be page aligned. | |
304 | */ | |
305 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
306 | { | |
307 | unsigned long order = get_order(size); | |
308 | struct page *page, *p, *e; | |
7a9a32a9 RK |
309 | |
310 | page = alloc_pages(gfp, order); | |
311 | if (!page) | |
312 | return NULL; | |
313 | ||
314 | /* | |
315 | * Now split the huge page and free the excess pages | |
316 | */ | |
317 | split_page(page, order); | |
318 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
319 | __free_page(p); | |
320 | ||
c7909509 | 321 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
322 | |
323 | return page; | |
324 | } | |
325 | ||
326 | /* | |
327 | * Free a DMA buffer. 'size' must be page aligned. | |
328 | */ | |
329 | static void __dma_free_buffer(struct page *page, size_t size) | |
330 | { | |
331 | struct page *e = page + (size >> PAGE_SHIFT); | |
332 | ||
333 | while (page < e) { | |
334 | __free_page(page); | |
335 | page++; | |
336 | } | |
337 | } | |
338 | ||
ab6494f0 | 339 | #ifdef CONFIG_MMU |
a5e9d38b | 340 | |
e9da6e99 | 341 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
9848e48f | 342 | pgprot_t prot, struct page **ret_page, |
6e8266e3 | 343 | const void *caller, bool want_vaddr); |
99d1717d | 344 | |
e9da6e99 MS |
345 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
346 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 347 | const void *caller, bool want_vaddr); |
99d1717d | 348 | |
e9da6e99 MS |
349 | static void * |
350 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
351 | const void *caller) | |
99d1717d | 352 | { |
e9da6e99 MS |
353 | /* |
354 | * DMA allocation can be mapped to user space, so lets | |
355 | * set VM_USERMAP flags too. | |
356 | */ | |
513510dd LA |
357 | return dma_common_contiguous_remap(page, size, |
358 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
359 | prot, caller); | |
99d1717d | 360 | } |
1da177e4 | 361 | |
e9da6e99 | 362 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 363 | { |
513510dd LA |
364 | dma_common_free_remap(cpu_addr, size, |
365 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
88c58f3b | 366 | } |
88c58f3b | 367 | |
6e5267aa | 368 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
36d0fd21 | 369 | static struct gen_pool *atomic_pool; |
6e5267aa | 370 | |
36d0fd21 | 371 | static size_t atomic_pool_size = DEFAULT_DMA_COHERENT_POOL_SIZE; |
c7909509 MS |
372 | |
373 | static int __init early_coherent_pool(char *p) | |
374 | { | |
36d0fd21 | 375 | atomic_pool_size = memparse(p, &p); |
c7909509 MS |
376 | return 0; |
377 | } | |
378 | early_param("coherent_pool", early_coherent_pool); | |
379 | ||
6e5267aa MS |
380 | void __init init_dma_coherent_pool_size(unsigned long size) |
381 | { | |
382 | /* | |
383 | * Catch any attempt to set the pool size too late. | |
384 | */ | |
36d0fd21 | 385 | BUG_ON(atomic_pool); |
6e5267aa MS |
386 | |
387 | /* | |
388 | * Set architecture specific coherent pool size only if | |
389 | * it has not been changed by kernel command line parameter. | |
390 | */ | |
36d0fd21 LA |
391 | if (atomic_pool_size == DEFAULT_DMA_COHERENT_POOL_SIZE) |
392 | atomic_pool_size = size; | |
6e5267aa MS |
393 | } |
394 | ||
c7909509 MS |
395 | /* |
396 | * Initialise the coherent pool for atomic allocations. | |
397 | */ | |
e9da6e99 | 398 | static int __init atomic_pool_init(void) |
c7909509 | 399 | { |
71b55663 | 400 | pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); |
9d1400cf | 401 | gfp_t gfp = GFP_KERNEL | GFP_DMA; |
c7909509 MS |
402 | struct page *page; |
403 | void *ptr; | |
c7909509 | 404 | |
36d0fd21 LA |
405 | atomic_pool = gen_pool_create(PAGE_SHIFT, -1); |
406 | if (!atomic_pool) | |
407 | goto out; | |
6b3fe472 | 408 | |
e464ef16 | 409 | if (dev_get_cma_area(NULL)) |
36d0fd21 | 410 | ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot, |
6e8266e3 | 411 | &page, atomic_pool_init, true); |
e9da6e99 | 412 | else |
36d0fd21 | 413 | ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot, |
6e8266e3 | 414 | &page, atomic_pool_init, true); |
c7909509 | 415 | if (ptr) { |
36d0fd21 LA |
416 | int ret; |
417 | ||
418 | ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr, | |
419 | page_to_phys(page), | |
420 | atomic_pool_size, -1); | |
421 | if (ret) | |
422 | goto destroy_genpool; | |
423 | ||
424 | gen_pool_set_algo(atomic_pool, | |
425 | gen_pool_first_fit_order_align, | |
426 | (void *)PAGE_SHIFT); | |
427 | pr_info("DMA: preallocated %zd KiB pool for atomic coherent allocations\n", | |
428 | atomic_pool_size / 1024); | |
c7909509 MS |
429 | return 0; |
430 | } | |
ec10665c | 431 | |
36d0fd21 LA |
432 | destroy_genpool: |
433 | gen_pool_destroy(atomic_pool); | |
434 | atomic_pool = NULL; | |
435 | out: | |
436 | pr_err("DMA: failed to allocate %zx KiB pool for atomic coherent allocation\n", | |
437 | atomic_pool_size / 1024); | |
c7909509 MS |
438 | return -ENOMEM; |
439 | } | |
440 | /* | |
441 | * CMA is activated by core_initcall, so we must be called after it. | |
442 | */ | |
e9da6e99 | 443 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
444 | |
445 | struct dma_contig_early_reserve { | |
446 | phys_addr_t base; | |
447 | unsigned long size; | |
448 | }; | |
449 | ||
450 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
451 | ||
452 | static int dma_mmu_remap_num __initdata; | |
453 | ||
454 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
455 | { | |
456 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
457 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
458 | dma_mmu_remap_num++; | |
459 | } | |
460 | ||
461 | void __init dma_contiguous_remap(void) | |
462 | { | |
463 | int i; | |
464 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
465 | phys_addr_t start = dma_mmu_remap[i].base; | |
466 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
467 | struct map_desc map; | |
468 | unsigned long addr; | |
469 | ||
470 | if (end > arm_lowmem_limit) | |
471 | end = arm_lowmem_limit; | |
472 | if (start >= end) | |
39f78e70 | 473 | continue; |
c7909509 MS |
474 | |
475 | map.pfn = __phys_to_pfn(start); | |
476 | map.virtual = __phys_to_virt(start); | |
477 | map.length = end - start; | |
478 | map.type = MT_MEMORY_DMA_READY; | |
479 | ||
480 | /* | |
6b076991 RK |
481 | * Clear previous low-memory mapping to ensure that the |
482 | * TLB does not see any conflicting entries, then flush | |
483 | * the TLB of the old entries before creating new mappings. | |
484 | * | |
485 | * This ensures that any speculatively loaded TLB entries | |
486 | * (even though they may be rare) can not cause any problems, | |
487 | * and ensures that this code is architecturally compliant. | |
c7909509 MS |
488 | */ |
489 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 490 | addr += PMD_SIZE) |
c7909509 MS |
491 | pmd_clear(pmd_off_k(addr)); |
492 | ||
6b076991 RK |
493 | flush_tlb_kernel_range(__phys_to_virt(start), |
494 | __phys_to_virt(end)); | |
495 | ||
c7909509 MS |
496 | iotable_init(&map, 1); |
497 | } | |
498 | } | |
499 | ||
c7909509 MS |
500 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
501 | void *data) | |
502 | { | |
503 | struct page *page = virt_to_page(addr); | |
504 | pgprot_t prot = *(pgprot_t *)data; | |
505 | ||
506 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
507 | return 0; | |
508 | } | |
509 | ||
510 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
511 | { | |
512 | unsigned long start = (unsigned long) page_address(page); | |
513 | unsigned end = start + size; | |
514 | ||
515 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
c7909509 MS |
516 | flush_tlb_kernel_range(start, end); |
517 | } | |
518 | ||
519 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
520 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 521 | const void *caller, bool want_vaddr) |
c7909509 MS |
522 | { |
523 | struct page *page; | |
6e8266e3 | 524 | void *ptr = NULL; |
c7909509 MS |
525 | page = __dma_alloc_buffer(dev, size, gfp); |
526 | if (!page) | |
527 | return NULL; | |
6e8266e3 CC |
528 | if (!want_vaddr) |
529 | goto out; | |
c7909509 MS |
530 | |
531 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
532 | if (!ptr) { | |
533 | __dma_free_buffer(page, size); | |
534 | return NULL; | |
535 | } | |
536 | ||
6e8266e3 | 537 | out: |
c7909509 MS |
538 | *ret_page = page; |
539 | return ptr; | |
540 | } | |
541 | ||
e9da6e99 | 542 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 543 | { |
36d0fd21 | 544 | unsigned long val; |
e9da6e99 | 545 | void *ptr = NULL; |
c7909509 | 546 | |
36d0fd21 | 547 | if (!atomic_pool) { |
e9da6e99 | 548 | WARN(1, "coherent pool not initialised!\n"); |
c7909509 MS |
549 | return NULL; |
550 | } | |
551 | ||
36d0fd21 LA |
552 | val = gen_pool_alloc(atomic_pool, size); |
553 | if (val) { | |
554 | phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val); | |
555 | ||
556 | *ret_page = phys_to_page(phys); | |
557 | ptr = (void *)val; | |
c7909509 | 558 | } |
e9da6e99 MS |
559 | |
560 | return ptr; | |
c7909509 MS |
561 | } |
562 | ||
21d0a759 HD |
563 | static bool __in_atomic_pool(void *start, size_t size) |
564 | { | |
36d0fd21 | 565 | return addr_in_gen_pool(atomic_pool, (unsigned long)start, size); |
21d0a759 HD |
566 | } |
567 | ||
e9da6e99 | 568 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 569 | { |
21d0a759 | 570 | if (!__in_atomic_pool(start, size)) |
c7909509 MS |
571 | return 0; |
572 | ||
36d0fd21 | 573 | gen_pool_free(atomic_pool, (unsigned long)start, size); |
e9da6e99 | 574 | |
c7909509 MS |
575 | return 1; |
576 | } | |
577 | ||
578 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
9848e48f | 579 | pgprot_t prot, struct page **ret_page, |
6e8266e3 | 580 | const void *caller, bool want_vaddr) |
c7909509 MS |
581 | { |
582 | unsigned long order = get_order(size); | |
583 | size_t count = size >> PAGE_SHIFT; | |
584 | struct page *page; | |
6e8266e3 | 585 | void *ptr = NULL; |
c7909509 MS |
586 | |
587 | page = dma_alloc_from_contiguous(dev, count, order); | |
588 | if (!page) | |
589 | return NULL; | |
590 | ||
591 | __dma_clear_buffer(page, size); | |
c7909509 | 592 | |
6e8266e3 CC |
593 | if (!want_vaddr) |
594 | goto out; | |
595 | ||
9848e48f MS |
596 | if (PageHighMem(page)) { |
597 | ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller); | |
598 | if (!ptr) { | |
599 | dma_release_from_contiguous(dev, page, count); | |
600 | return NULL; | |
601 | } | |
602 | } else { | |
603 | __dma_remap(page, size, prot); | |
604 | ptr = page_address(page); | |
605 | } | |
6e8266e3 CC |
606 | |
607 | out: | |
c7909509 | 608 | *ret_page = page; |
9848e48f | 609 | return ptr; |
c7909509 MS |
610 | } |
611 | ||
612 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
6e8266e3 | 613 | void *cpu_addr, size_t size, bool want_vaddr) |
c7909509 | 614 | { |
6e8266e3 CC |
615 | if (want_vaddr) { |
616 | if (PageHighMem(page)) | |
617 | __dma_free_remap(cpu_addr, size); | |
618 | else | |
619 | __dma_remap(page, size, PAGE_KERNEL); | |
620 | } | |
c7909509 MS |
621 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); |
622 | } | |
623 | ||
f99d6034 MS |
624 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
625 | { | |
626 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
627 | pgprot_writecombine(prot) : | |
628 | pgprot_dmacoherent(prot); | |
629 | return prot; | |
630 | } | |
631 | ||
c7909509 MS |
632 | #define nommu() 0 |
633 | ||
ab6494f0 | 634 | #else /* !CONFIG_MMU */ |
695ae0af | 635 | |
c7909509 MS |
636 | #define nommu() 1 |
637 | ||
6e8266e3 CC |
638 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
639 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c, wv) NULL | |
e9da6e99 | 640 | #define __alloc_from_pool(size, ret_page) NULL |
6e8266e3 | 641 | #define __alloc_from_contiguous(dev, size, prot, ret, c, wv) NULL |
b4268676 | 642 | #define __free_from_pool(cpu_addr, size) do { } while (0) |
6e8266e3 | 643 | #define __free_from_contiguous(dev, page, cpu_addr, size, wv) do { } while (0) |
c7909509 | 644 | #define __dma_free_remap(cpu_addr, size) do { } while (0) |
31ebf944 RK |
645 | |
646 | #endif /* CONFIG_MMU */ | |
647 | ||
c7909509 MS |
648 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
649 | struct page **ret_page) | |
ab6494f0 | 650 | { |
c7909509 MS |
651 | struct page *page; |
652 | page = __dma_alloc_buffer(dev, size, gfp); | |
653 | if (!page) | |
654 | return NULL; | |
655 | ||
656 | *ret_page = page; | |
657 | return page_address(page); | |
658 | } | |
659 | ||
b4268676 RV |
660 | static void *simple_allocator_alloc(struct arm_dma_alloc_args *args, |
661 | struct page **ret_page) | |
662 | { | |
663 | return __alloc_simple_buffer(args->dev, args->size, args->gfp, | |
664 | ret_page); | |
665 | } | |
c7909509 | 666 | |
b4268676 RV |
667 | static void simple_allocator_free(struct arm_dma_free_args *args) |
668 | { | |
669 | __dma_free_buffer(args->page, args->size); | |
670 | } | |
671 | ||
672 | static struct arm_dma_allocator simple_allocator = { | |
673 | .alloc = simple_allocator_alloc, | |
674 | .free = simple_allocator_free, | |
675 | }; | |
676 | ||
677 | static void *cma_allocator_alloc(struct arm_dma_alloc_args *args, | |
678 | struct page **ret_page) | |
679 | { | |
680 | return __alloc_from_contiguous(args->dev, args->size, args->prot, | |
681 | ret_page, args->caller, | |
682 | args->want_vaddr); | |
683 | } | |
684 | ||
685 | static void cma_allocator_free(struct arm_dma_free_args *args) | |
686 | { | |
687 | __free_from_contiguous(args->dev, args->page, args->cpu_addr, | |
688 | args->size, args->want_vaddr); | |
689 | } | |
690 | ||
691 | static struct arm_dma_allocator cma_allocator = { | |
692 | .alloc = cma_allocator_alloc, | |
693 | .free = cma_allocator_free, | |
694 | }; | |
695 | ||
696 | static void *pool_allocator_alloc(struct arm_dma_alloc_args *args, | |
697 | struct page **ret_page) | |
698 | { | |
699 | return __alloc_from_pool(args->size, ret_page); | |
700 | } | |
701 | ||
702 | static void pool_allocator_free(struct arm_dma_free_args *args) | |
703 | { | |
704 | __free_from_pool(args->cpu_addr, args->size); | |
705 | } | |
706 | ||
707 | static struct arm_dma_allocator pool_allocator = { | |
708 | .alloc = pool_allocator_alloc, | |
709 | .free = pool_allocator_free, | |
710 | }; | |
711 | ||
712 | static void *remap_allocator_alloc(struct arm_dma_alloc_args *args, | |
713 | struct page **ret_page) | |
714 | { | |
715 | return __alloc_remap_buffer(args->dev, args->size, args->gfp, | |
716 | args->prot, ret_page, args->caller, | |
717 | args->want_vaddr); | |
718 | } | |
719 | ||
720 | static void remap_allocator_free(struct arm_dma_free_args *args) | |
721 | { | |
722 | if (args->want_vaddr) | |
723 | __dma_free_remap(args->cpu_addr, args->size); | |
724 | ||
725 | __dma_free_buffer(args->page, args->size); | |
726 | } | |
727 | ||
728 | static struct arm_dma_allocator remap_allocator = { | |
729 | .alloc = remap_allocator_alloc, | |
730 | .free = remap_allocator_free, | |
731 | }; | |
c7909509 MS |
732 | |
733 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
6e8266e3 CC |
734 | gfp_t gfp, pgprot_t prot, bool is_coherent, |
735 | struct dma_attrs *attrs, const void *caller) | |
c7909509 MS |
736 | { |
737 | u64 mask = get_coherent_dma_mask(dev); | |
3dd7ea92 | 738 | struct page *page = NULL; |
31ebf944 | 739 | void *addr; |
b4268676 | 740 | bool allowblock, cma; |
19e6e5e5 | 741 | struct arm_dma_buffer *buf; |
b4268676 RV |
742 | struct arm_dma_alloc_args args = { |
743 | .dev = dev, | |
744 | .size = PAGE_ALIGN(size), | |
745 | .gfp = gfp, | |
746 | .prot = prot, | |
747 | .caller = caller, | |
748 | .want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs), | |
749 | }; | |
ab6494f0 | 750 | |
c7909509 MS |
751 | #ifdef CONFIG_DMA_API_DEBUG |
752 | u64 limit = (mask + 1) & ~mask; | |
753 | if (limit && size >= limit) { | |
754 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
755 | size, mask); | |
756 | return NULL; | |
757 | } | |
758 | #endif | |
759 | ||
760 | if (!mask) | |
761 | return NULL; | |
762 | ||
9c18fcf7 AC |
763 | buf = kzalloc(sizeof(*buf), |
764 | gfp & ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM)); | |
19e6e5e5 RV |
765 | if (!buf) |
766 | return NULL; | |
767 | ||
c7909509 MS |
768 | if (mask < 0xffffffffULL) |
769 | gfp |= GFP_DMA; | |
770 | ||
ea2e7057 SB |
771 | /* |
772 | * Following is a work-around (a.k.a. hack) to prevent pages | |
773 | * with __GFP_COMP being passed to split_page() which cannot | |
774 | * handle them. The real problem is that this flag probably | |
775 | * should be 0 on ARM as it is not supported on this | |
776 | * platform; see CONFIG_HUGETLBFS. | |
777 | */ | |
778 | gfp &= ~(__GFP_COMP); | |
b4268676 | 779 | args.gfp = gfp; |
ea2e7057 | 780 | |
553ac788 | 781 | *handle = DMA_ERROR_CODE; |
b4268676 RV |
782 | allowblock = gfpflags_allow_blocking(gfp); |
783 | cma = allowblock ? dev_get_cma_area(dev) : false; | |
784 | ||
785 | if (cma) | |
786 | buf->allocator = &cma_allocator; | |
787 | else if (nommu() || is_coherent) | |
788 | buf->allocator = &simple_allocator; | |
789 | else if (allowblock) | |
790 | buf->allocator = &remap_allocator; | |
31ebf944 | 791 | else |
b4268676 RV |
792 | buf->allocator = &pool_allocator; |
793 | ||
794 | addr = buf->allocator->alloc(&args, &page); | |
695ae0af | 795 | |
19e6e5e5 RV |
796 | if (page) { |
797 | unsigned long flags; | |
798 | ||
9eedd963 | 799 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
b4268676 | 800 | buf->virt = args.want_vaddr ? addr : page; |
19e6e5e5 RV |
801 | |
802 | spin_lock_irqsave(&arm_dma_bufs_lock, flags); | |
803 | list_add(&buf->list, &arm_dma_bufs); | |
804 | spin_unlock_irqrestore(&arm_dma_bufs_lock, flags); | |
805 | } else { | |
806 | kfree(buf); | |
807 | } | |
695ae0af | 808 | |
b4268676 | 809 | return args.want_vaddr ? addr : page; |
31ebf944 | 810 | } |
1da177e4 LT |
811 | |
812 | /* | |
813 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
814 | * virtual and bus address for that space. | |
815 | */ | |
f99d6034 MS |
816 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
817 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 818 | { |
0ea1ec71 | 819 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
1fe53268 | 820 | |
dd37e940 | 821 | return __dma_alloc(dev, size, handle, gfp, prot, false, |
6e8266e3 | 822 | attrs, __builtin_return_address(0)); |
dd37e940 RH |
823 | } |
824 | ||
825 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, | |
826 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
827 | { | |
21caf3a7 | 828 | return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true, |
6e8266e3 | 829 | attrs, __builtin_return_address(0)); |
1da177e4 | 830 | } |
1da177e4 | 831 | |
55af8a91 | 832 | static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
f99d6034 MS |
833 | void *cpu_addr, dma_addr_t dma_addr, size_t size, |
834 | struct dma_attrs *attrs) | |
1da177e4 | 835 | { |
ab6494f0 CM |
836 | int ret = -ENXIO; |
837 | #ifdef CONFIG_MMU | |
50262a4b MS |
838 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
839 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 840 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
841 | unsigned long off = vma->vm_pgoff; |
842 | ||
47142f07 MS |
843 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
844 | return ret; | |
845 | ||
50262a4b MS |
846 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
847 | ret = remap_pfn_range(vma, vma->vm_start, | |
848 | pfn + off, | |
849 | vma->vm_end - vma->vm_start, | |
850 | vma->vm_page_prot); | |
851 | } | |
ab6494f0 | 852 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
853 | |
854 | return ret; | |
855 | } | |
856 | ||
55af8a91 ML |
857 | /* |
858 | * Create userspace mapping for the DMA-coherent memory. | |
859 | */ | |
860 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
861 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
862 | struct dma_attrs *attrs) | |
863 | { | |
864 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
865 | } | |
866 | ||
867 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
868 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
869 | struct dma_attrs *attrs) | |
870 | { | |
871 | #ifdef CONFIG_MMU | |
872 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
873 | #endif /* CONFIG_MMU */ | |
874 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
875 | } | |
876 | ||
1da177e4 | 877 | /* |
c7909509 | 878 | * Free a buffer as defined by the above mapping. |
1da177e4 | 879 | */ |
dd37e940 RH |
880 | static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
881 | dma_addr_t handle, struct dma_attrs *attrs, | |
882 | bool is_coherent) | |
1da177e4 | 883 | { |
c7909509 | 884 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
19e6e5e5 | 885 | struct arm_dma_buffer *buf; |
b4268676 RV |
886 | struct arm_dma_free_args args = { |
887 | .dev = dev, | |
888 | .size = PAGE_ALIGN(size), | |
889 | .cpu_addr = cpu_addr, | |
890 | .page = page, | |
891 | .want_vaddr = !dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs), | |
892 | }; | |
19e6e5e5 RV |
893 | |
894 | buf = arm_dma_buffer_find(cpu_addr); | |
895 | if (WARN(!buf, "Freeing invalid buffer %p\n", cpu_addr)) | |
896 | return; | |
5edf71ae | 897 | |
b4268676 | 898 | buf->allocator->free(&args); |
19e6e5e5 | 899 | kfree(buf); |
1da177e4 | 900 | } |
afd1a321 | 901 | |
dd37e940 RH |
902 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
903 | dma_addr_t handle, struct dma_attrs *attrs) | |
904 | { | |
905 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, false); | |
906 | } | |
907 | ||
908 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
909 | dma_addr_t handle, struct dma_attrs *attrs) | |
910 | { | |
911 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, true); | |
912 | } | |
913 | ||
dc2832e1 MS |
914 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
915 | void *cpu_addr, dma_addr_t handle, size_t size, | |
916 | struct dma_attrs *attrs) | |
917 | { | |
918 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
919 | int ret; | |
920 | ||
921 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
922 | if (unlikely(ret)) | |
923 | return ret; | |
924 | ||
925 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
926 | return 0; | |
927 | } | |
928 | ||
4ea0d737 | 929 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
930 | size_t size, enum dma_data_direction dir, |
931 | void (*op)(const void *, size_t, int)) | |
43377453 | 932 | { |
15653371 RK |
933 | unsigned long pfn; |
934 | size_t left = size; | |
935 | ||
936 | pfn = page_to_pfn(page) + offset / PAGE_SIZE; | |
937 | offset %= PAGE_SIZE; | |
938 | ||
43377453 NP |
939 | /* |
940 | * A single sg entry may refer to multiple physically contiguous | |
941 | * pages. But we still need to process highmem pages individually. | |
942 | * If highmem is not configured then the bulk of this loop gets | |
943 | * optimized out. | |
944 | */ | |
43377453 NP |
945 | do { |
946 | size_t len = left; | |
93f1d629 RK |
947 | void *vaddr; |
948 | ||
15653371 RK |
949 | page = pfn_to_page(pfn); |
950 | ||
93f1d629 | 951 | if (PageHighMem(page)) { |
15653371 | 952 | if (len + offset > PAGE_SIZE) |
93f1d629 | 953 | len = PAGE_SIZE - offset; |
dd0f67f4 JK |
954 | |
955 | if (cache_is_vipt_nonaliasing()) { | |
39af22a7 | 956 | vaddr = kmap_atomic(page); |
7e5a69e8 | 957 | op(vaddr + offset, len, dir); |
39af22a7 | 958 | kunmap_atomic(vaddr); |
dd0f67f4 JK |
959 | } else { |
960 | vaddr = kmap_high_get(page); | |
961 | if (vaddr) { | |
962 | op(vaddr + offset, len, dir); | |
963 | kunmap_high(page); | |
964 | } | |
43377453 | 965 | } |
93f1d629 RK |
966 | } else { |
967 | vaddr = page_address(page) + offset; | |
a9c9147e | 968 | op(vaddr, len, dir); |
43377453 | 969 | } |
43377453 | 970 | offset = 0; |
15653371 | 971 | pfn++; |
43377453 NP |
972 | left -= len; |
973 | } while (left); | |
974 | } | |
4ea0d737 | 975 | |
51fde349 MS |
976 | /* |
977 | * Make an area consistent for devices. | |
978 | * Note: Drivers should NOT use this function directly, as it will break | |
979 | * platforms with CONFIG_DMABOUNCE. | |
980 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
981 | */ | |
982 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
983 | size_t size, enum dma_data_direction dir) |
984 | { | |
2161c248 | 985 | phys_addr_t paddr; |
65af191a | 986 | |
a9c9147e | 987 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
988 | |
989 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
990 | if (dir == DMA_FROM_DEVICE) { |
991 | outer_inv_range(paddr, paddr + size); | |
992 | } else { | |
993 | outer_clean_range(paddr, paddr + size); | |
994 | } | |
995 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 996 | } |
4ea0d737 | 997 | |
51fde349 | 998 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
999 | size_t size, enum dma_data_direction dir) |
1000 | { | |
2161c248 | 1001 | phys_addr_t paddr = page_to_phys(page) + off; |
2ffe2da3 RK |
1002 | |
1003 | /* FIXME: non-speculating: not required */ | |
deace4a6 RK |
1004 | /* in any case, don't bother invalidating if DMA to device */ |
1005 | if (dir != DMA_TO_DEVICE) { | |
2ffe2da3 RK |
1006 | outer_inv_range(paddr, paddr + size); |
1007 | ||
deace4a6 RK |
1008 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
1009 | } | |
c0177800 CM |
1010 | |
1011 | /* | |
b2a234ed | 1012 | * Mark the D-cache clean for these pages to avoid extra flushing. |
c0177800 | 1013 | */ |
b2a234ed ML |
1014 | if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) { |
1015 | unsigned long pfn; | |
1016 | size_t left = size; | |
1017 | ||
1018 | pfn = page_to_pfn(page) + off / PAGE_SIZE; | |
1019 | off %= PAGE_SIZE; | |
1020 | if (off) { | |
1021 | pfn++; | |
1022 | left -= PAGE_SIZE - off; | |
1023 | } | |
1024 | while (left >= PAGE_SIZE) { | |
1025 | page = pfn_to_page(pfn++); | |
1026 | set_bit(PG_dcache_clean, &page->flags); | |
1027 | left -= PAGE_SIZE; | |
1028 | } | |
1029 | } | |
4ea0d737 | 1030 | } |
43377453 | 1031 | |
afd1a321 | 1032 | /** |
2a550e73 | 1033 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
1034 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1035 | * @sg: list of buffers | |
1036 | * @nents: number of buffers to map | |
1037 | * @dir: DMA transfer direction | |
1038 | * | |
1039 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1040 | * This is the scatter-gather version of the dma_map_single interface. | |
1041 | * Here the scatter gather list elements are each tagged with the | |
1042 | * appropriate dma address and length. They are obtained via | |
1043 | * sg_dma_{address,length}. | |
1044 | * | |
1045 | * Device ownership issues as mentioned for dma_map_single are the same | |
1046 | * here. | |
1047 | */ | |
2dc6a016 MS |
1048 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
1049 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 1050 | { |
2a550e73 | 1051 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 1052 | struct scatterlist *s; |
01135d92 | 1053 | int i, j; |
afd1a321 RK |
1054 | |
1055 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
1056 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
1057 | s->dma_length = s->length; | |
1058 | #endif | |
2a550e73 MS |
1059 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
1060 | s->length, dir, attrs); | |
01135d92 RK |
1061 | if (dma_mapping_error(dev, s->dma_address)) |
1062 | goto bad_mapping; | |
afd1a321 | 1063 | } |
afd1a321 | 1064 | return nents; |
01135d92 RK |
1065 | |
1066 | bad_mapping: | |
1067 | for_each_sg(sg, s, i, j) | |
2a550e73 | 1068 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 1069 | return 0; |
afd1a321 | 1070 | } |
afd1a321 RK |
1071 | |
1072 | /** | |
2a550e73 | 1073 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
1074 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1075 | * @sg: list of buffers | |
0adfca6f | 1076 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
1077 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
1078 | * | |
1079 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1080 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1081 | */ | |
2dc6a016 MS |
1082 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
1083 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 1084 | { |
2a550e73 | 1085 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 1086 | struct scatterlist *s; |
01135d92 | 1087 | |
01135d92 | 1088 | int i; |
24056f52 | 1089 | |
01135d92 | 1090 | for_each_sg(sg, s, nents, i) |
2a550e73 | 1091 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 1092 | } |
afd1a321 RK |
1093 | |
1094 | /** | |
2a550e73 | 1095 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
1096 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1097 | * @sg: list of buffers | |
1098 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1099 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1100 | */ | |
2dc6a016 | 1101 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1102 | int nents, enum dma_data_direction dir) |
1103 | { | |
2a550e73 | 1104 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1105 | struct scatterlist *s; |
1106 | int i; | |
1107 | ||
2a550e73 MS |
1108 | for_each_sg(sg, s, nents, i) |
1109 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
1110 | dir); | |
afd1a321 | 1111 | } |
afd1a321 RK |
1112 | |
1113 | /** | |
2a550e73 | 1114 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
1115 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1116 | * @sg: list of buffers | |
1117 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1118 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1119 | */ | |
2dc6a016 | 1120 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1121 | int nents, enum dma_data_direction dir) |
1122 | { | |
2a550e73 | 1123 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1124 | struct scatterlist *s; |
1125 | int i; | |
1126 | ||
2a550e73 MS |
1127 | for_each_sg(sg, s, nents, i) |
1128 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
1129 | dir); | |
afd1a321 | 1130 | } |
24056f52 | 1131 | |
022ae537 RK |
1132 | /* |
1133 | * Return whether the given device DMA address mask can be supported | |
1134 | * properly. For example, if your device can only drive the low 24-bits | |
1135 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
1136 | * to this function. | |
1137 | */ | |
1138 | int dma_supported(struct device *dev, u64 mask) | |
1139 | { | |
9f28cde0 | 1140 | return __dma_supported(dev, mask, false); |
022ae537 RK |
1141 | } |
1142 | EXPORT_SYMBOL(dma_supported); | |
1143 | ||
24056f52 RK |
1144 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
1145 | ||
1146 | static int __init dma_debug_do_init(void) | |
1147 | { | |
1148 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
1149 | return 0; | |
1150 | } | |
1151 | fs_initcall(dma_debug_do_init); | |
4ce63fcd MS |
1152 | |
1153 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
1154 | ||
1155 | /* IOMMU */ | |
1156 | ||
4d852ef8 AH |
1157 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping); |
1158 | ||
4ce63fcd MS |
1159 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, |
1160 | size_t size) | |
1161 | { | |
1162 | unsigned int order = get_order(size); | |
1163 | unsigned int align = 0; | |
1164 | unsigned int count, start; | |
006f841d | 1165 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1166 | unsigned long flags; |
4d852ef8 AH |
1167 | dma_addr_t iova; |
1168 | int i; | |
4ce63fcd | 1169 | |
60460abf SWK |
1170 | if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT) |
1171 | order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT; | |
1172 | ||
68efd7d2 MS |
1173 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1174 | align = (1 << order) - 1; | |
4ce63fcd MS |
1175 | |
1176 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 AH |
1177 | for (i = 0; i < mapping->nr_bitmaps; i++) { |
1178 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1179 | mapping->bits, 0, count, align); | |
1180 | ||
1181 | if (start > mapping->bits) | |
1182 | continue; | |
1183 | ||
1184 | bitmap_set(mapping->bitmaps[i], start, count); | |
1185 | break; | |
4ce63fcd MS |
1186 | } |
1187 | ||
4d852ef8 AH |
1188 | /* |
1189 | * No unused range found. Try to extend the existing mapping | |
1190 | * and perform a second attempt to reserve an IO virtual | |
1191 | * address range of size bytes. | |
1192 | */ | |
1193 | if (i == mapping->nr_bitmaps) { | |
1194 | if (extend_iommu_mapping(mapping)) { | |
1195 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1196 | return DMA_ERROR_CODE; | |
1197 | } | |
1198 | ||
1199 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1200 | mapping->bits, 0, count, align); | |
1201 | ||
1202 | if (start > mapping->bits) { | |
1203 | spin_unlock_irqrestore(&mapping->lock, flags); | |
1204 | return DMA_ERROR_CODE; | |
1205 | } | |
1206 | ||
1207 | bitmap_set(mapping->bitmaps[i], start, count); | |
1208 | } | |
4ce63fcd MS |
1209 | spin_unlock_irqrestore(&mapping->lock, flags); |
1210 | ||
006f841d | 1211 | iova = mapping->base + (mapping_size * i); |
68efd7d2 | 1212 | iova += start << PAGE_SHIFT; |
4d852ef8 AH |
1213 | |
1214 | return iova; | |
4ce63fcd MS |
1215 | } |
1216 | ||
1217 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
1218 | dma_addr_t addr, size_t size) | |
1219 | { | |
4d852ef8 | 1220 | unsigned int start, count; |
006f841d | 1221 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1222 | unsigned long flags; |
4d852ef8 AH |
1223 | dma_addr_t bitmap_base; |
1224 | u32 bitmap_index; | |
1225 | ||
1226 | if (!size) | |
1227 | return; | |
1228 | ||
006f841d | 1229 | bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size; |
4d852ef8 AH |
1230 | BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions); |
1231 | ||
006f841d | 1232 | bitmap_base = mapping->base + mapping_size * bitmap_index; |
4d852ef8 | 1233 | |
68efd7d2 | 1234 | start = (addr - bitmap_base) >> PAGE_SHIFT; |
4d852ef8 | 1235 | |
006f841d | 1236 | if (addr + size > bitmap_base + mapping_size) { |
4d852ef8 AH |
1237 | /* |
1238 | * The address range to be freed reaches into the iova | |
1239 | * range of the next bitmap. This should not happen as | |
1240 | * we don't allow this in __alloc_iova (at the | |
1241 | * moment). | |
1242 | */ | |
1243 | BUG(); | |
1244 | } else | |
68efd7d2 | 1245 | count = size >> PAGE_SHIFT; |
4ce63fcd MS |
1246 | |
1247 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 | 1248 | bitmap_clear(mapping->bitmaps[bitmap_index], start, count); |
4ce63fcd MS |
1249 | spin_unlock_irqrestore(&mapping->lock, flags); |
1250 | } | |
1251 | ||
33298ef6 DA |
1252 | /* We'll try 2M, 1M, 64K, and finally 4K; array must end with 0! */ |
1253 | static const int iommu_order_array[] = { 9, 8, 4, 0 }; | |
1254 | ||
549a17e4 MS |
1255 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, |
1256 | gfp_t gfp, struct dma_attrs *attrs) | |
4ce63fcd MS |
1257 | { |
1258 | struct page **pages; | |
1259 | int count = size >> PAGE_SHIFT; | |
1260 | int array_size = count * sizeof(struct page *); | |
1261 | int i = 0; | |
33298ef6 | 1262 | int order_idx = 0; |
4ce63fcd MS |
1263 | |
1264 | if (array_size <= PAGE_SIZE) | |
23be7fda | 1265 | pages = kzalloc(array_size, GFP_KERNEL); |
4ce63fcd MS |
1266 | else |
1267 | pages = vzalloc(array_size); | |
1268 | if (!pages) | |
1269 | return NULL; | |
1270 | ||
549a17e4 MS |
1271 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) |
1272 | { | |
1273 | unsigned long order = get_order(size); | |
1274 | struct page *page; | |
1275 | ||
1276 | page = dma_alloc_from_contiguous(dev, count, order); | |
1277 | if (!page) | |
1278 | goto error; | |
1279 | ||
1280 | __dma_clear_buffer(page, size); | |
1281 | ||
1282 | for (i = 0; i < count; i++) | |
1283 | pages[i] = page + i; | |
1284 | ||
1285 | return pages; | |
1286 | } | |
1287 | ||
14d3ae2e DA |
1288 | /* Go straight to 4K chunks if caller says it's OK. */ |
1289 | if (dma_get_attr(DMA_ATTR_ALLOC_SINGLE_PAGES, attrs)) | |
1290 | order_idx = ARRAY_SIZE(iommu_order_array) - 1; | |
1291 | ||
f8669bef MS |
1292 | /* |
1293 | * IOMMU can map any pages, so himem can also be used here | |
1294 | */ | |
1295 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
1296 | ||
4ce63fcd | 1297 | while (count) { |
49f28aa6 TF |
1298 | int j, order; |
1299 | ||
33298ef6 DA |
1300 | order = iommu_order_array[order_idx]; |
1301 | ||
1302 | /* Drop down when we get small */ | |
1303 | if (__fls(count) < order) { | |
1304 | order_idx++; | |
1305 | continue; | |
49f28aa6 | 1306 | } |
4ce63fcd | 1307 | |
33298ef6 DA |
1308 | if (order) { |
1309 | /* See if it's easy to allocate a high-order chunk */ | |
1310 | pages[i] = alloc_pages(gfp | __GFP_NORETRY, order); | |
1311 | ||
1312 | /* Go down a notch at first sign of pressure */ | |
1313 | if (!pages[i]) { | |
1314 | order_idx++; | |
1315 | continue; | |
1316 | } | |
1317 | } else { | |
49f28aa6 TF |
1318 | pages[i] = alloc_pages(gfp, 0); |
1319 | if (!pages[i]) | |
1320 | goto error; | |
1321 | } | |
4ce63fcd | 1322 | |
5a796eeb | 1323 | if (order) { |
4ce63fcd | 1324 | split_page(pages[i], order); |
5a796eeb HD |
1325 | j = 1 << order; |
1326 | while (--j) | |
1327 | pages[i + j] = pages[i] + j; | |
1328 | } | |
4ce63fcd MS |
1329 | |
1330 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
1331 | i += 1 << order; | |
1332 | count -= 1 << order; | |
1333 | } | |
1334 | ||
1335 | return pages; | |
1336 | error: | |
9fa8af91 | 1337 | while (i--) |
4ce63fcd MS |
1338 | if (pages[i]) |
1339 | __free_pages(pages[i], 0); | |
1d5cfdb0 | 1340 | kvfree(pages); |
4ce63fcd MS |
1341 | return NULL; |
1342 | } | |
1343 | ||
549a17e4 MS |
1344 | static int __iommu_free_buffer(struct device *dev, struct page **pages, |
1345 | size_t size, struct dma_attrs *attrs) | |
4ce63fcd MS |
1346 | { |
1347 | int count = size >> PAGE_SHIFT; | |
4ce63fcd | 1348 | int i; |
549a17e4 MS |
1349 | |
1350 | if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) { | |
1351 | dma_release_from_contiguous(dev, pages[0], count); | |
1352 | } else { | |
1353 | for (i = 0; i < count; i++) | |
1354 | if (pages[i]) | |
1355 | __free_pages(pages[i], 0); | |
1356 | } | |
1357 | ||
1d5cfdb0 | 1358 | kvfree(pages); |
4ce63fcd MS |
1359 | return 0; |
1360 | } | |
1361 | ||
1362 | /* | |
1363 | * Create a CPU mapping for a specified pages | |
1364 | */ | |
1365 | static void * | |
e9da6e99 MS |
1366 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1367 | const void *caller) | |
4ce63fcd | 1368 | { |
513510dd LA |
1369 | return dma_common_pages_remap(pages, size, |
1370 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller); | |
4ce63fcd MS |
1371 | } |
1372 | ||
1373 | /* | |
1374 | * Create a mapping in device IO address space for specified pages | |
1375 | */ | |
1376 | static dma_addr_t | |
1377 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1378 | { | |
89cfdb19 | 1379 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1380 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1381 | dma_addr_t dma_addr, iova; | |
90cde558 | 1382 | int i; |
4ce63fcd MS |
1383 | |
1384 | dma_addr = __alloc_iova(mapping, size); | |
1385 | if (dma_addr == DMA_ERROR_CODE) | |
1386 | return dma_addr; | |
1387 | ||
1388 | iova = dma_addr; | |
1389 | for (i = 0; i < count; ) { | |
90cde558 AP |
1390 | int ret; |
1391 | ||
4ce63fcd MS |
1392 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; |
1393 | phys_addr_t phys = page_to_phys(pages[i]); | |
1394 | unsigned int len, j; | |
1395 | ||
1396 | for (j = i + 1; j < count; j++, next_pfn++) | |
1397 | if (page_to_pfn(pages[j]) != next_pfn) | |
1398 | break; | |
1399 | ||
1400 | len = (j - i) << PAGE_SHIFT; | |
c9b24996 AH |
1401 | ret = iommu_map(mapping->domain, iova, phys, len, |
1402 | IOMMU_READ|IOMMU_WRITE); | |
4ce63fcd MS |
1403 | if (ret < 0) |
1404 | goto fail; | |
1405 | iova += len; | |
1406 | i = j; | |
1407 | } | |
1408 | return dma_addr; | |
1409 | fail: | |
1410 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1411 | __free_iova(mapping, dma_addr, size); | |
1412 | return DMA_ERROR_CODE; | |
1413 | } | |
1414 | ||
1415 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1416 | { | |
89cfdb19 | 1417 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1418 | |
1419 | /* | |
1420 | * add optional in-page offset from iova to size and align | |
1421 | * result to page size | |
1422 | */ | |
1423 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1424 | iova &= PAGE_MASK; | |
1425 | ||
1426 | iommu_unmap(mapping->domain, iova, size); | |
1427 | __free_iova(mapping, iova, size); | |
1428 | return 0; | |
1429 | } | |
1430 | ||
665bad7b HD |
1431 | static struct page **__atomic_get_pages(void *addr) |
1432 | { | |
36d0fd21 LA |
1433 | struct page *page; |
1434 | phys_addr_t phys; | |
1435 | ||
1436 | phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr); | |
1437 | page = phys_to_page(phys); | |
665bad7b | 1438 | |
36d0fd21 | 1439 | return (struct page **)page; |
665bad7b HD |
1440 | } |
1441 | ||
955c757e | 1442 | static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) |
e9da6e99 MS |
1443 | { |
1444 | struct vm_struct *area; | |
1445 | ||
665bad7b HD |
1446 | if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) |
1447 | return __atomic_get_pages(cpu_addr); | |
1448 | ||
955c757e MS |
1449 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1450 | return cpu_addr; | |
1451 | ||
e9da6e99 MS |
1452 | area = find_vm_area(cpu_addr); |
1453 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1454 | return area->pages; | |
1455 | return NULL; | |
1456 | } | |
1457 | ||
479ed93a HD |
1458 | static void *__iommu_alloc_atomic(struct device *dev, size_t size, |
1459 | dma_addr_t *handle) | |
1460 | { | |
1461 | struct page *page; | |
1462 | void *addr; | |
1463 | ||
1464 | addr = __alloc_from_pool(size, &page); | |
1465 | if (!addr) | |
1466 | return NULL; | |
1467 | ||
1468 | *handle = __iommu_create_mapping(dev, &page, size); | |
1469 | if (*handle == DMA_ERROR_CODE) | |
1470 | goto err_mapping; | |
1471 | ||
1472 | return addr; | |
1473 | ||
1474 | err_mapping: | |
1475 | __free_from_pool(addr, size); | |
1476 | return NULL; | |
1477 | } | |
1478 | ||
d5898291 | 1479 | static void __iommu_free_atomic(struct device *dev, void *cpu_addr, |
479ed93a HD |
1480 | dma_addr_t handle, size_t size) |
1481 | { | |
1482 | __iommu_remove_mapping(dev, handle, size); | |
d5898291 | 1483 | __free_from_pool(cpu_addr, size); |
479ed93a HD |
1484 | } |
1485 | ||
4ce63fcd MS |
1486 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
1487 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1488 | { | |
71b55663 | 1489 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
4ce63fcd MS |
1490 | struct page **pages; |
1491 | void *addr = NULL; | |
1492 | ||
1493 | *handle = DMA_ERROR_CODE; | |
1494 | size = PAGE_ALIGN(size); | |
1495 | ||
d0164adc | 1496 | if (!gfpflags_allow_blocking(gfp)) |
479ed93a HD |
1497 | return __iommu_alloc_atomic(dev, size, handle); |
1498 | ||
5b91a98c RZ |
1499 | /* |
1500 | * Following is a work-around (a.k.a. hack) to prevent pages | |
1501 | * with __GFP_COMP being passed to split_page() which cannot | |
1502 | * handle them. The real problem is that this flag probably | |
1503 | * should be 0 on ARM as it is not supported on this | |
1504 | * platform; see CONFIG_HUGETLBFS. | |
1505 | */ | |
1506 | gfp &= ~(__GFP_COMP); | |
1507 | ||
549a17e4 | 1508 | pages = __iommu_alloc_buffer(dev, size, gfp, attrs); |
4ce63fcd MS |
1509 | if (!pages) |
1510 | return NULL; | |
1511 | ||
1512 | *handle = __iommu_create_mapping(dev, pages, size); | |
1513 | if (*handle == DMA_ERROR_CODE) | |
1514 | goto err_buffer; | |
1515 | ||
955c757e MS |
1516 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1517 | return pages; | |
1518 | ||
e9da6e99 MS |
1519 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1520 | __builtin_return_address(0)); | |
4ce63fcd MS |
1521 | if (!addr) |
1522 | goto err_mapping; | |
1523 | ||
1524 | return addr; | |
1525 | ||
1526 | err_mapping: | |
1527 | __iommu_remove_mapping(dev, *handle, size); | |
1528 | err_buffer: | |
549a17e4 | 1529 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1530 | return NULL; |
1531 | } | |
1532 | ||
1533 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1534 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1535 | struct dma_attrs *attrs) | |
1536 | { | |
e9da6e99 MS |
1537 | unsigned long uaddr = vma->vm_start; |
1538 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1539 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
371f0f08 MS |
1540 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1541 | unsigned long off = vma->vm_pgoff; | |
4ce63fcd MS |
1542 | |
1543 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
4ce63fcd | 1544 | |
e9da6e99 MS |
1545 | if (!pages) |
1546 | return -ENXIO; | |
4ce63fcd | 1547 | |
371f0f08 MS |
1548 | if (off >= nr_pages || (usize >> PAGE_SHIFT) > nr_pages - off) |
1549 | return -ENXIO; | |
1550 | ||
7e312103 MS |
1551 | pages += off; |
1552 | ||
e9da6e99 MS |
1553 | do { |
1554 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1555 | if (ret) { | |
1556 | pr_err("Remapping memory failed: %d\n", ret); | |
1557 | return ret; | |
1558 | } | |
1559 | uaddr += PAGE_SIZE; | |
1560 | usize -= PAGE_SIZE; | |
1561 | } while (usize > 0); | |
4ce63fcd | 1562 | |
4ce63fcd MS |
1563 | return 0; |
1564 | } | |
1565 | ||
1566 | /* | |
1567 | * free a page as defined by the above mapping. | |
1568 | * Must not be called with IRQs disabled. | |
1569 | */ | |
1570 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1571 | dma_addr_t handle, struct dma_attrs *attrs) | |
1572 | { | |
836bfa0d | 1573 | struct page **pages; |
4ce63fcd MS |
1574 | size = PAGE_ALIGN(size); |
1575 | ||
836bfa0d YC |
1576 | if (__in_atomic_pool(cpu_addr, size)) { |
1577 | __iommu_free_atomic(dev, cpu_addr, handle, size); | |
e9da6e99 | 1578 | return; |
4ce63fcd | 1579 | } |
e9da6e99 | 1580 | |
836bfa0d YC |
1581 | pages = __iommu_get_pages(cpu_addr, attrs); |
1582 | if (!pages) { | |
1583 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
479ed93a HD |
1584 | return; |
1585 | } | |
1586 | ||
955c757e | 1587 | if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { |
513510dd LA |
1588 | dma_common_free_remap(cpu_addr, size, |
1589 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
955c757e | 1590 | } |
e9da6e99 MS |
1591 | |
1592 | __iommu_remove_mapping(dev, handle, size); | |
549a17e4 | 1593 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1594 | } |
1595 | ||
dc2832e1 MS |
1596 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1597 | void *cpu_addr, dma_addr_t dma_addr, | |
1598 | size_t size, struct dma_attrs *attrs) | |
1599 | { | |
1600 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1601 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1602 | ||
1603 | if (!pages) | |
1604 | return -ENXIO; | |
1605 | ||
1606 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1607 | GFP_KERNEL); | |
4ce63fcd MS |
1608 | } |
1609 | ||
c9b24996 AH |
1610 | static int __dma_direction_to_prot(enum dma_data_direction dir) |
1611 | { | |
1612 | int prot; | |
1613 | ||
1614 | switch (dir) { | |
1615 | case DMA_BIDIRECTIONAL: | |
1616 | prot = IOMMU_READ | IOMMU_WRITE; | |
1617 | break; | |
1618 | case DMA_TO_DEVICE: | |
1619 | prot = IOMMU_READ; | |
1620 | break; | |
1621 | case DMA_FROM_DEVICE: | |
1622 | prot = IOMMU_WRITE; | |
1623 | break; | |
1624 | default: | |
1625 | prot = 0; | |
1626 | } | |
1627 | ||
1628 | return prot; | |
1629 | } | |
1630 | ||
4ce63fcd MS |
1631 | /* |
1632 | * Map a part of the scatter-gather list into contiguous io address space | |
1633 | */ | |
1634 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1635 | size_t size, dma_addr_t *handle, | |
0fa478df RH |
1636 | enum dma_data_direction dir, struct dma_attrs *attrs, |
1637 | bool is_coherent) | |
4ce63fcd | 1638 | { |
89cfdb19 | 1639 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1640 | dma_addr_t iova, iova_base; |
1641 | int ret = 0; | |
1642 | unsigned int count; | |
1643 | struct scatterlist *s; | |
c9b24996 | 1644 | int prot; |
4ce63fcd MS |
1645 | |
1646 | size = PAGE_ALIGN(size); | |
1647 | *handle = DMA_ERROR_CODE; | |
1648 | ||
1649 | iova_base = iova = __alloc_iova(mapping, size); | |
1650 | if (iova == DMA_ERROR_CODE) | |
1651 | return -ENOMEM; | |
1652 | ||
1653 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
3e6110fd | 1654 | phys_addr_t phys = page_to_phys(sg_page(s)); |
4ce63fcd MS |
1655 | unsigned int len = PAGE_ALIGN(s->offset + s->length); |
1656 | ||
0fa478df RH |
1657 | if (!is_coherent && |
1658 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1659 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1660 | ||
c9b24996 AH |
1661 | prot = __dma_direction_to_prot(dir); |
1662 | ||
1663 | ret = iommu_map(mapping->domain, iova, phys, len, prot); | |
4ce63fcd MS |
1664 | if (ret < 0) |
1665 | goto fail; | |
1666 | count += len >> PAGE_SHIFT; | |
1667 | iova += len; | |
1668 | } | |
1669 | *handle = iova_base; | |
1670 | ||
1671 | return 0; | |
1672 | fail: | |
1673 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1674 | __free_iova(mapping, iova_base, size); | |
1675 | return ret; | |
1676 | } | |
1677 | ||
0fa478df RH |
1678 | static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
1679 | enum dma_data_direction dir, struct dma_attrs *attrs, | |
1680 | bool is_coherent) | |
4ce63fcd MS |
1681 | { |
1682 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1683 | int i, count = 0; | |
1684 | unsigned int offset = s->offset; | |
1685 | unsigned int size = s->offset + s->length; | |
1686 | unsigned int max = dma_get_max_seg_size(dev); | |
1687 | ||
1688 | for (i = 1; i < nents; i++) { | |
1689 | s = sg_next(s); | |
1690 | ||
1691 | s->dma_address = DMA_ERROR_CODE; | |
1692 | s->dma_length = 0; | |
1693 | ||
1694 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1695 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
0fa478df | 1696 | dir, attrs, is_coherent) < 0) |
4ce63fcd MS |
1697 | goto bad_mapping; |
1698 | ||
1699 | dma->dma_address += offset; | |
1700 | dma->dma_length = size - offset; | |
1701 | ||
1702 | size = offset = s->offset; | |
1703 | start = s; | |
1704 | dma = sg_next(dma); | |
1705 | count += 1; | |
1706 | } | |
1707 | size += s->length; | |
1708 | } | |
0fa478df RH |
1709 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs, |
1710 | is_coherent) < 0) | |
4ce63fcd MS |
1711 | goto bad_mapping; |
1712 | ||
1713 | dma->dma_address += offset; | |
1714 | dma->dma_length = size - offset; | |
1715 | ||
1716 | return count+1; | |
1717 | ||
1718 | bad_mapping: | |
1719 | for_each_sg(sg, s, count, i) | |
1720 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1721 | return 0; | |
1722 | } | |
1723 | ||
1724 | /** | |
0fa478df | 1725 | * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA |
4ce63fcd MS |
1726 | * @dev: valid struct device pointer |
1727 | * @sg: list of buffers | |
0fa478df RH |
1728 | * @nents: number of buffers to map |
1729 | * @dir: DMA transfer direction | |
4ce63fcd | 1730 | * |
0fa478df RH |
1731 | * Map a set of i/o coherent buffers described by scatterlist in streaming |
1732 | * mode for DMA. The scatter gather list elements are merged together (if | |
1733 | * possible) and tagged with the appropriate dma address and length. They are | |
1734 | * obtained via sg_dma_{address,length}. | |
4ce63fcd | 1735 | */ |
0fa478df RH |
1736 | int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg, |
1737 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1738 | { | |
1739 | return __iommu_map_sg(dev, sg, nents, dir, attrs, true); | |
1740 | } | |
1741 | ||
1742 | /** | |
1743 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1744 | * @dev: valid struct device pointer | |
1745 | * @sg: list of buffers | |
1746 | * @nents: number of buffers to map | |
1747 | * @dir: DMA transfer direction | |
1748 | * | |
1749 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1750 | * The scatter gather list elements are merged together (if possible) and | |
1751 | * tagged with the appropriate dma address and length. They are obtained via | |
1752 | * sg_dma_{address,length}. | |
1753 | */ | |
1754 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, | |
1755 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1756 | { | |
1757 | return __iommu_map_sg(dev, sg, nents, dir, attrs, false); | |
1758 | } | |
1759 | ||
1760 | static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1761 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs, | |
1762 | bool is_coherent) | |
4ce63fcd MS |
1763 | { |
1764 | struct scatterlist *s; | |
1765 | int i; | |
1766 | ||
1767 | for_each_sg(sg, s, nents, i) { | |
1768 | if (sg_dma_len(s)) | |
1769 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1770 | sg_dma_len(s)); | |
0fa478df | 1771 | if (!is_coherent && |
97ef952a | 1772 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1773 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1774 | s->length, dir); | |
1775 | } | |
1776 | } | |
1777 | ||
0fa478df RH |
1778 | /** |
1779 | * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1780 | * @dev: valid struct device pointer | |
1781 | * @sg: list of buffers | |
1782 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1783 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1784 | * | |
1785 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1786 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1787 | */ | |
1788 | void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
1789 | int nents, enum dma_data_direction dir, struct dma_attrs *attrs) | |
1790 | { | |
1791 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, true); | |
1792 | } | |
1793 | ||
1794 | /** | |
1795 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1796 | * @dev: valid struct device pointer | |
1797 | * @sg: list of buffers | |
1798 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1799 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1800 | * | |
1801 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1802 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1803 | */ | |
1804 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1805 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1806 | { | |
1807 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, false); | |
1808 | } | |
1809 | ||
4ce63fcd MS |
1810 | /** |
1811 | * arm_iommu_sync_sg_for_cpu | |
1812 | * @dev: valid struct device pointer | |
1813 | * @sg: list of buffers | |
1814 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1815 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1816 | */ | |
1817 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1818 | int nents, enum dma_data_direction dir) | |
1819 | { | |
1820 | struct scatterlist *s; | |
1821 | int i; | |
1822 | ||
1823 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1824 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1825 | |
1826 | } | |
1827 | ||
1828 | /** | |
1829 | * arm_iommu_sync_sg_for_device | |
1830 | * @dev: valid struct device pointer | |
1831 | * @sg: list of buffers | |
1832 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1833 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1834 | */ | |
1835 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1836 | int nents, enum dma_data_direction dir) | |
1837 | { | |
1838 | struct scatterlist *s; | |
1839 | int i; | |
1840 | ||
1841 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1842 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1843 | } |
1844 | ||
1845 | ||
1846 | /** | |
0fa478df | 1847 | * arm_coherent_iommu_map_page |
4ce63fcd MS |
1848 | * @dev: valid struct device pointer |
1849 | * @page: page that buffer resides in | |
1850 | * @offset: offset into page for start of buffer | |
1851 | * @size: size of buffer to map | |
1852 | * @dir: DMA transfer direction | |
1853 | * | |
0fa478df | 1854 | * Coherent IOMMU aware version of arm_dma_map_page() |
4ce63fcd | 1855 | */ |
0fa478df | 1856 | static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page, |
4ce63fcd MS |
1857 | unsigned long offset, size_t size, enum dma_data_direction dir, |
1858 | struct dma_attrs *attrs) | |
1859 | { | |
89cfdb19 | 1860 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd | 1861 | dma_addr_t dma_addr; |
13987d68 | 1862 | int ret, prot, len = PAGE_ALIGN(size + offset); |
4ce63fcd | 1863 | |
4ce63fcd MS |
1864 | dma_addr = __alloc_iova(mapping, len); |
1865 | if (dma_addr == DMA_ERROR_CODE) | |
1866 | return dma_addr; | |
1867 | ||
c9b24996 | 1868 | prot = __dma_direction_to_prot(dir); |
13987d68 WD |
1869 | |
1870 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot); | |
4ce63fcd MS |
1871 | if (ret < 0) |
1872 | goto fail; | |
1873 | ||
1874 | return dma_addr + offset; | |
1875 | fail: | |
1876 | __free_iova(mapping, dma_addr, len); | |
1877 | return DMA_ERROR_CODE; | |
1878 | } | |
1879 | ||
0fa478df RH |
1880 | /** |
1881 | * arm_iommu_map_page | |
1882 | * @dev: valid struct device pointer | |
1883 | * @page: page that buffer resides in | |
1884 | * @offset: offset into page for start of buffer | |
1885 | * @size: size of buffer to map | |
1886 | * @dir: DMA transfer direction | |
1887 | * | |
1888 | * IOMMU aware version of arm_dma_map_page() | |
1889 | */ | |
1890 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1891 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1892 | struct dma_attrs *attrs) | |
1893 | { | |
1894 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
1895 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1896 | ||
1897 | return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs); | |
1898 | } | |
1899 | ||
1900 | /** | |
1901 | * arm_coherent_iommu_unmap_page | |
1902 | * @dev: valid struct device pointer | |
1903 | * @handle: DMA address of buffer | |
1904 | * @size: size of buffer (same as passed to dma_map_page) | |
1905 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1906 | * | |
1907 | * Coherent IOMMU aware version of arm_dma_unmap_page() | |
1908 | */ | |
1909 | static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1910 | size_t size, enum dma_data_direction dir, | |
1911 | struct dma_attrs *attrs) | |
1912 | { | |
89cfdb19 | 1913 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
0fa478df | 1914 | dma_addr_t iova = handle & PAGE_MASK; |
0fa478df RH |
1915 | int offset = handle & ~PAGE_MASK; |
1916 | int len = PAGE_ALIGN(size + offset); | |
1917 | ||
1918 | if (!iova) | |
1919 | return; | |
1920 | ||
1921 | iommu_unmap(mapping->domain, iova, len); | |
1922 | __free_iova(mapping, iova, len); | |
1923 | } | |
1924 | ||
4ce63fcd MS |
1925 | /** |
1926 | * arm_iommu_unmap_page | |
1927 | * @dev: valid struct device pointer | |
1928 | * @handle: DMA address of buffer | |
1929 | * @size: size of buffer (same as passed to dma_map_page) | |
1930 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1931 | * | |
1932 | * IOMMU aware version of arm_dma_unmap_page() | |
1933 | */ | |
1934 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1935 | size_t size, enum dma_data_direction dir, | |
1936 | struct dma_attrs *attrs) | |
1937 | { | |
89cfdb19 | 1938 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1939 | dma_addr_t iova = handle & PAGE_MASK; |
1940 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1941 | int offset = handle & ~PAGE_MASK; | |
1942 | int len = PAGE_ALIGN(size + offset); | |
1943 | ||
1944 | if (!iova) | |
1945 | return; | |
1946 | ||
0fa478df | 1947 | if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1948 | __dma_page_dev_to_cpu(page, offset, size, dir); |
1949 | ||
1950 | iommu_unmap(mapping->domain, iova, len); | |
1951 | __free_iova(mapping, iova, len); | |
1952 | } | |
1953 | ||
1954 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1955 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1956 | { | |
89cfdb19 | 1957 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1958 | dma_addr_t iova = handle & PAGE_MASK; |
1959 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1960 | unsigned int offset = handle & ~PAGE_MASK; | |
1961 | ||
1962 | if (!iova) | |
1963 | return; | |
1964 | ||
0fa478df | 1965 | __dma_page_dev_to_cpu(page, offset, size, dir); |
4ce63fcd MS |
1966 | } |
1967 | ||
1968 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1969 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1970 | { | |
89cfdb19 | 1971 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1972 | dma_addr_t iova = handle & PAGE_MASK; |
1973 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1974 | unsigned int offset = handle & ~PAGE_MASK; | |
1975 | ||
1976 | if (!iova) | |
1977 | return; | |
1978 | ||
1979 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1980 | } | |
1981 | ||
1982 | struct dma_map_ops iommu_ops = { | |
1983 | .alloc = arm_iommu_alloc_attrs, | |
1984 | .free = arm_iommu_free_attrs, | |
1985 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 1986 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
1987 | |
1988 | .map_page = arm_iommu_map_page, | |
1989 | .unmap_page = arm_iommu_unmap_page, | |
1990 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1991 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1992 | ||
1993 | .map_sg = arm_iommu_map_sg, | |
1994 | .unmap_sg = arm_iommu_unmap_sg, | |
1995 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1996 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
1997 | }; | |
1998 | ||
0fa478df RH |
1999 | struct dma_map_ops iommu_coherent_ops = { |
2000 | .alloc = arm_iommu_alloc_attrs, | |
2001 | .free = arm_iommu_free_attrs, | |
2002 | .mmap = arm_iommu_mmap_attrs, | |
2003 | .get_sgtable = arm_iommu_get_sgtable, | |
2004 | ||
2005 | .map_page = arm_coherent_iommu_map_page, | |
2006 | .unmap_page = arm_coherent_iommu_unmap_page, | |
2007 | ||
2008 | .map_sg = arm_coherent_iommu_map_sg, | |
2009 | .unmap_sg = arm_coherent_iommu_unmap_sg, | |
2010 | }; | |
2011 | ||
4ce63fcd MS |
2012 | /** |
2013 | * arm_iommu_create_mapping | |
2014 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
2015 | * @base: start address of the valid IO address space | |
68efd7d2 | 2016 | * @size: maximum size of the valid IO address space |
4ce63fcd MS |
2017 | * |
2018 | * Creates a mapping structure which holds information about used/unused | |
2019 | * IO address ranges, which is required to perform memory allocation and | |
2020 | * mapping with IOMMU aware functions. | |
2021 | * | |
2022 | * The client device need to be attached to the mapping with | |
2023 | * arm_iommu_attach_device function. | |
2024 | */ | |
2025 | struct dma_iommu_mapping * | |
1424532b | 2026 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size) |
4ce63fcd | 2027 | { |
68efd7d2 MS |
2028 | unsigned int bits = size >> PAGE_SHIFT; |
2029 | unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); | |
4ce63fcd | 2030 | struct dma_iommu_mapping *mapping; |
68efd7d2 | 2031 | int extensions = 1; |
4ce63fcd MS |
2032 | int err = -ENOMEM; |
2033 | ||
1424532b MS |
2034 | /* currently only 32-bit DMA address space is supported */ |
2035 | if (size > DMA_BIT_MASK(32) + 1) | |
2036 | return ERR_PTR(-ERANGE); | |
2037 | ||
68efd7d2 | 2038 | if (!bitmap_size) |
4ce63fcd MS |
2039 | return ERR_PTR(-EINVAL); |
2040 | ||
68efd7d2 MS |
2041 | if (bitmap_size > PAGE_SIZE) { |
2042 | extensions = bitmap_size / PAGE_SIZE; | |
2043 | bitmap_size = PAGE_SIZE; | |
2044 | } | |
2045 | ||
4ce63fcd MS |
2046 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); |
2047 | if (!mapping) | |
2048 | goto err; | |
2049 | ||
68efd7d2 MS |
2050 | mapping->bitmap_size = bitmap_size; |
2051 | mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *), | |
4d852ef8 AH |
2052 | GFP_KERNEL); |
2053 | if (!mapping->bitmaps) | |
4ce63fcd MS |
2054 | goto err2; |
2055 | ||
68efd7d2 | 2056 | mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL); |
4d852ef8 AH |
2057 | if (!mapping->bitmaps[0]) |
2058 | goto err3; | |
2059 | ||
2060 | mapping->nr_bitmaps = 1; | |
2061 | mapping->extensions = extensions; | |
4ce63fcd | 2062 | mapping->base = base; |
68efd7d2 | 2063 | mapping->bits = BITS_PER_BYTE * bitmap_size; |
4d852ef8 | 2064 | |
4ce63fcd MS |
2065 | spin_lock_init(&mapping->lock); |
2066 | ||
2067 | mapping->domain = iommu_domain_alloc(bus); | |
2068 | if (!mapping->domain) | |
4d852ef8 | 2069 | goto err4; |
4ce63fcd MS |
2070 | |
2071 | kref_init(&mapping->kref); | |
2072 | return mapping; | |
4d852ef8 AH |
2073 | err4: |
2074 | kfree(mapping->bitmaps[0]); | |
4ce63fcd | 2075 | err3: |
4d852ef8 | 2076 | kfree(mapping->bitmaps); |
4ce63fcd MS |
2077 | err2: |
2078 | kfree(mapping); | |
2079 | err: | |
2080 | return ERR_PTR(err); | |
2081 | } | |
18177d12 | 2082 | EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); |
4ce63fcd MS |
2083 | |
2084 | static void release_iommu_mapping(struct kref *kref) | |
2085 | { | |
4d852ef8 | 2086 | int i; |
4ce63fcd MS |
2087 | struct dma_iommu_mapping *mapping = |
2088 | container_of(kref, struct dma_iommu_mapping, kref); | |
2089 | ||
2090 | iommu_domain_free(mapping->domain); | |
4d852ef8 AH |
2091 | for (i = 0; i < mapping->nr_bitmaps; i++) |
2092 | kfree(mapping->bitmaps[i]); | |
2093 | kfree(mapping->bitmaps); | |
4ce63fcd MS |
2094 | kfree(mapping); |
2095 | } | |
2096 | ||
4d852ef8 AH |
2097 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) |
2098 | { | |
2099 | int next_bitmap; | |
2100 | ||
462859aa | 2101 | if (mapping->nr_bitmaps >= mapping->extensions) |
4d852ef8 AH |
2102 | return -EINVAL; |
2103 | ||
2104 | next_bitmap = mapping->nr_bitmaps; | |
2105 | mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size, | |
2106 | GFP_ATOMIC); | |
2107 | if (!mapping->bitmaps[next_bitmap]) | |
2108 | return -ENOMEM; | |
2109 | ||
2110 | mapping->nr_bitmaps++; | |
2111 | ||
2112 | return 0; | |
2113 | } | |
2114 | ||
4ce63fcd MS |
2115 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) |
2116 | { | |
2117 | if (mapping) | |
2118 | kref_put(&mapping->kref, release_iommu_mapping); | |
2119 | } | |
18177d12 | 2120 | EXPORT_SYMBOL_GPL(arm_iommu_release_mapping); |
4ce63fcd | 2121 | |
eab8d653 LP |
2122 | static int __arm_iommu_attach_device(struct device *dev, |
2123 | struct dma_iommu_mapping *mapping) | |
2124 | { | |
2125 | int err; | |
2126 | ||
2127 | err = iommu_attach_device(mapping->domain, dev); | |
2128 | if (err) | |
2129 | return err; | |
2130 | ||
2131 | kref_get(&mapping->kref); | |
89cfdb19 | 2132 | to_dma_iommu_mapping(dev) = mapping; |
eab8d653 LP |
2133 | |
2134 | pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
2135 | return 0; | |
2136 | } | |
2137 | ||
4ce63fcd MS |
2138 | /** |
2139 | * arm_iommu_attach_device | |
2140 | * @dev: valid struct device pointer | |
2141 | * @mapping: io address space mapping structure (returned from | |
2142 | * arm_iommu_create_mapping) | |
2143 | * | |
eab8d653 LP |
2144 | * Attaches specified io address space mapping to the provided device. |
2145 | * This replaces the dma operations (dma_map_ops pointer) with the | |
2146 | * IOMMU aware version. | |
2147 | * | |
4bb25789 WD |
2148 | * More than one client might be attached to the same io address space |
2149 | * mapping. | |
4ce63fcd MS |
2150 | */ |
2151 | int arm_iommu_attach_device(struct device *dev, | |
2152 | struct dma_iommu_mapping *mapping) | |
2153 | { | |
2154 | int err; | |
2155 | ||
eab8d653 | 2156 | err = __arm_iommu_attach_device(dev, mapping); |
4ce63fcd MS |
2157 | if (err) |
2158 | return err; | |
2159 | ||
eab8d653 | 2160 | set_dma_ops(dev, &iommu_ops); |
4ce63fcd MS |
2161 | return 0; |
2162 | } | |
18177d12 | 2163 | EXPORT_SYMBOL_GPL(arm_iommu_attach_device); |
4ce63fcd | 2164 | |
eab8d653 | 2165 | static void __arm_iommu_detach_device(struct device *dev) |
6fe36758 HD |
2166 | { |
2167 | struct dma_iommu_mapping *mapping; | |
2168 | ||
2169 | mapping = to_dma_iommu_mapping(dev); | |
2170 | if (!mapping) { | |
2171 | dev_warn(dev, "Not attached\n"); | |
2172 | return; | |
2173 | } | |
2174 | ||
2175 | iommu_detach_device(mapping->domain, dev); | |
2176 | kref_put(&mapping->kref, release_iommu_mapping); | |
89cfdb19 | 2177 | to_dma_iommu_mapping(dev) = NULL; |
6fe36758 HD |
2178 | |
2179 | pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev)); | |
2180 | } | |
eab8d653 LP |
2181 | |
2182 | /** | |
2183 | * arm_iommu_detach_device | |
2184 | * @dev: valid struct device pointer | |
2185 | * | |
2186 | * Detaches the provided device from a previously attached map. | |
2187 | * This voids the dma operations (dma_map_ops pointer) | |
2188 | */ | |
2189 | void arm_iommu_detach_device(struct device *dev) | |
2190 | { | |
2191 | __arm_iommu_detach_device(dev); | |
2192 | set_dma_ops(dev, NULL); | |
2193 | } | |
18177d12 | 2194 | EXPORT_SYMBOL_GPL(arm_iommu_detach_device); |
6fe36758 | 2195 | |
4bb25789 WD |
2196 | static struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent) |
2197 | { | |
2198 | return coherent ? &iommu_coherent_ops : &iommu_ops; | |
2199 | } | |
2200 | ||
2201 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
53c92d79 | 2202 | const struct iommu_ops *iommu) |
4bb25789 WD |
2203 | { |
2204 | struct dma_iommu_mapping *mapping; | |
2205 | ||
2206 | if (!iommu) | |
2207 | return false; | |
2208 | ||
2209 | mapping = arm_iommu_create_mapping(dev->bus, dma_base, size); | |
2210 | if (IS_ERR(mapping)) { | |
2211 | pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n", | |
2212 | size, dev_name(dev)); | |
2213 | return false; | |
2214 | } | |
2215 | ||
eab8d653 | 2216 | if (__arm_iommu_attach_device(dev, mapping)) { |
4bb25789 WD |
2217 | pr_warn("Failed to attached device %s to IOMMU_mapping\n", |
2218 | dev_name(dev)); | |
2219 | arm_iommu_release_mapping(mapping); | |
2220 | return false; | |
2221 | } | |
2222 | ||
2223 | return true; | |
2224 | } | |
2225 | ||
2226 | static void arm_teardown_iommu_dma_ops(struct device *dev) | |
2227 | { | |
89cfdb19 | 2228 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4bb25789 | 2229 | |
c2273a18 WD |
2230 | if (!mapping) |
2231 | return; | |
2232 | ||
eab8d653 | 2233 | __arm_iommu_detach_device(dev); |
4bb25789 WD |
2234 | arm_iommu_release_mapping(mapping); |
2235 | } | |
2236 | ||
2237 | #else | |
2238 | ||
2239 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
53c92d79 | 2240 | const struct iommu_ops *iommu) |
4bb25789 WD |
2241 | { |
2242 | return false; | |
2243 | } | |
2244 | ||
2245 | static void arm_teardown_iommu_dma_ops(struct device *dev) { } | |
2246 | ||
2247 | #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops | |
2248 | ||
2249 | #endif /* CONFIG_ARM_DMA_USE_IOMMU */ | |
2250 | ||
2251 | static struct dma_map_ops *arm_get_dma_map_ops(bool coherent) | |
2252 | { | |
2253 | return coherent ? &arm_coherent_dma_ops : &arm_dma_ops; | |
2254 | } | |
2255 | ||
2256 | void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
53c92d79 | 2257 | const struct iommu_ops *iommu, bool coherent) |
4bb25789 WD |
2258 | { |
2259 | struct dma_map_ops *dma_ops; | |
2260 | ||
6f51ee70 | 2261 | dev->archdata.dma_coherent = coherent; |
4bb25789 WD |
2262 | if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) |
2263 | dma_ops = arm_get_iommu_dma_map_ops(coherent); | |
2264 | else | |
2265 | dma_ops = arm_get_dma_map_ops(coherent); | |
2266 | ||
2267 | set_dma_ops(dev, dma_ops); | |
2268 | } | |
2269 | ||
2270 | void arch_teardown_dma_ops(struct device *dev) | |
2271 | { | |
2272 | arm_teardown_iommu_dma_ops(dev); | |
2273 | } |