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Commit | Line | Data |
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1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
1da177e4 LT |
15 | #include <linux/errno.h> |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
39af22a7 | 20 | #include <linux/highmem.h> |
99d1717d | 21 | #include <linux/slab.h> |
1da177e4 | 22 | |
23759dc6 | 23 | #include <asm/memory.h> |
43377453 | 24 | #include <asm/highmem.h> |
1da177e4 | 25 | #include <asm/cacheflush.h> |
1da177e4 | 26 | #include <asm/tlbflush.h> |
37134cd5 | 27 | #include <asm/sizes.h> |
99d1717d | 28 | #include <asm/mach/arch.h> |
37134cd5 | 29 | |
022ae537 RK |
30 | #include "mm.h" |
31 | ||
15237e1f MS |
32 | /* |
33 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
34 | * is either exclusively owned by the CPU (and therefore may be accessed | |
35 | * by it) or exclusively owned by the DMA device. These helper functions | |
36 | * represent the transitions between these two ownership states. | |
37 | * | |
38 | * Note, however, that on later ARMs, this notion does not work due to | |
39 | * speculative prefetches. We model our approach on the assumption that | |
40 | * the CPU does do speculative prefetches, which means we clean caches | |
41 | * before transfers and delay cache invalidation until transfer completion. | |
42 | * | |
15237e1f | 43 | */ |
51fde349 | 44 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 45 | size_t, enum dma_data_direction); |
51fde349 | 46 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
47 | size_t, enum dma_data_direction); |
48 | ||
2dc6a016 MS |
49 | /** |
50 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
51 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
52 | * @page: page that buffer resides in | |
53 | * @offset: offset into page for start of buffer | |
54 | * @size: size of buffer to map | |
55 | * @dir: DMA transfer direction | |
56 | * | |
57 | * Ensure that any data held in the cache is appropriately discarded | |
58 | * or written back. | |
59 | * | |
60 | * The device owns this memory once this call has completed. The CPU | |
61 | * can regain ownership by calling dma_unmap_page(). | |
62 | */ | |
51fde349 | 63 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
64 | unsigned long offset, size_t size, enum dma_data_direction dir, |
65 | struct dma_attrs *attrs) | |
66 | { | |
51fde349 MS |
67 | if (!arch_is_coherent()) |
68 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
69 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
70 | } |
71 | ||
72 | /** | |
73 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
74 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
75 | * @handle: DMA address of buffer | |
76 | * @size: size of buffer (same as passed to dma_map_page) | |
77 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
78 | * | |
79 | * Unmap a page streaming mode DMA translation. The handle and size | |
80 | * must match what was provided in the previous dma_map_page() call. | |
81 | * All other usages are undefined. | |
82 | * | |
83 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
84 | * whatever the device wrote there. | |
85 | */ | |
51fde349 | 86 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
87 | size_t size, enum dma_data_direction dir, |
88 | struct dma_attrs *attrs) | |
89 | { | |
51fde349 MS |
90 | if (!arch_is_coherent()) |
91 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), | |
92 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
93 | } |
94 | ||
51fde349 | 95 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
96 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
97 | { | |
98 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
99 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
100 | if (!arch_is_coherent()) |
101 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
2dc6a016 MS |
102 | } |
103 | ||
51fde349 | 104 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
105 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
106 | { | |
107 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
108 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
109 | if (!arch_is_coherent()) |
110 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
2dc6a016 MS |
111 | } |
112 | ||
113 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask); | |
114 | ||
115 | struct dma_map_ops arm_dma_ops = { | |
f99d6034 MS |
116 | .alloc = arm_dma_alloc, |
117 | .free = arm_dma_free, | |
118 | .mmap = arm_dma_mmap, | |
2dc6a016 MS |
119 | .map_page = arm_dma_map_page, |
120 | .unmap_page = arm_dma_unmap_page, | |
121 | .map_sg = arm_dma_map_sg, | |
122 | .unmap_sg = arm_dma_unmap_sg, | |
123 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
124 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
125 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
126 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
127 | .set_dma_mask = arm_dma_set_mask, | |
128 | }; | |
129 | EXPORT_SYMBOL(arm_dma_ops); | |
130 | ||
ab6494f0 CM |
131 | static u64 get_coherent_dma_mask(struct device *dev) |
132 | { | |
022ae537 | 133 | u64 mask = (u64)arm_dma_limit; |
ab6494f0 CM |
134 | |
135 | if (dev) { | |
136 | mask = dev->coherent_dma_mask; | |
137 | ||
138 | /* | |
139 | * Sanity check the DMA mask - it must be non-zero, and | |
140 | * must be able to be satisfied by a DMA allocation. | |
141 | */ | |
142 | if (mask == 0) { | |
143 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
144 | return 0; | |
145 | } | |
146 | ||
022ae537 | 147 | if ((~mask) & (u64)arm_dma_limit) { |
ab6494f0 CM |
148 | dev_warn(dev, "coherent DMA mask %#llx is smaller " |
149 | "than system GFP_DMA mask %#llx\n", | |
022ae537 | 150 | mask, (u64)arm_dma_limit); |
ab6494f0 CM |
151 | return 0; |
152 | } | |
153 | } | |
1da177e4 | 154 | |
ab6494f0 CM |
155 | return mask; |
156 | } | |
157 | ||
7a9a32a9 RK |
158 | /* |
159 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
160 | * specified gfp mask. Note that 'size' must be page aligned. | |
161 | */ | |
162 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
163 | { | |
164 | unsigned long order = get_order(size); | |
165 | struct page *page, *p, *e; | |
166 | void *ptr; | |
167 | u64 mask = get_coherent_dma_mask(dev); | |
168 | ||
169 | #ifdef CONFIG_DMA_API_DEBUG | |
170 | u64 limit = (mask + 1) & ~mask; | |
171 | if (limit && size >= limit) { | |
172 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
173 | size, mask); | |
174 | return NULL; | |
175 | } | |
176 | #endif | |
177 | ||
178 | if (!mask) | |
179 | return NULL; | |
180 | ||
181 | if (mask < 0xffffffffULL) | |
182 | gfp |= GFP_DMA; | |
183 | ||
184 | page = alloc_pages(gfp, order); | |
185 | if (!page) | |
186 | return NULL; | |
187 | ||
188 | /* | |
189 | * Now split the huge page and free the excess pages | |
190 | */ | |
191 | split_page(page, order); | |
192 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
193 | __free_page(p); | |
194 | ||
195 | /* | |
196 | * Ensure that the allocated pages are zeroed, and that any data | |
197 | * lurking in the kernel direct-mapped region is invalidated. | |
198 | */ | |
199 | ptr = page_address(page); | |
200 | memset(ptr, 0, size); | |
201 | dmac_flush_range(ptr, ptr + size); | |
202 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
203 | ||
204 | return page; | |
205 | } | |
206 | ||
207 | /* | |
208 | * Free a DMA buffer. 'size' must be page aligned. | |
209 | */ | |
210 | static void __dma_free_buffer(struct page *page, size_t size) | |
211 | { | |
212 | struct page *e = page + (size >> PAGE_SHIFT); | |
213 | ||
214 | while (page < e) { | |
215 | __free_page(page); | |
216 | page++; | |
217 | } | |
218 | } | |
219 | ||
ab6494f0 | 220 | #ifdef CONFIG_MMU |
a5e9d38b | 221 | |
99d1717d | 222 | #define CONSISTENT_OFFSET(x) (((unsigned long)(x) - consistent_base) >> PAGE_SHIFT) |
1fdb24e9 | 223 | #define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - consistent_base) >> PMD_SHIFT) |
a5e9d38b | 224 | |
1da177e4 | 225 | /* |
37134cd5 | 226 | * These are the page tables (2MB each) covering uncached, DMA consistent allocations |
1da177e4 | 227 | */ |
99d1717d JM |
228 | static pte_t **consistent_pte; |
229 | ||
99d1717d | 230 | #define DEFAULT_CONSISTENT_DMA_SIZE SZ_2M |
99d1717d JM |
231 | |
232 | unsigned long consistent_base = CONSISTENT_END - DEFAULT_CONSISTENT_DMA_SIZE; | |
233 | ||
234 | void __init init_consistent_dma_size(unsigned long size) | |
235 | { | |
236 | unsigned long base = CONSISTENT_END - ALIGN(size, SZ_2M); | |
237 | ||
238 | BUG_ON(consistent_pte); /* Check we're called before DMA region init */ | |
239 | BUG_ON(base < VMALLOC_END); | |
240 | ||
241 | /* Grow region to accommodate specified size */ | |
242 | if (base < consistent_base) | |
243 | consistent_base = base; | |
244 | } | |
1da177e4 | 245 | |
13ccf3ad | 246 | #include "vmregion.h" |
1da177e4 | 247 | |
13ccf3ad RK |
248 | static struct arm_vmregion_head consistent_head = { |
249 | .vm_lock = __SPIN_LOCK_UNLOCKED(&consistent_head.vm_lock), | |
1da177e4 | 250 | .vm_list = LIST_HEAD_INIT(consistent_head.vm_list), |
1da177e4 LT |
251 | .vm_end = CONSISTENT_END, |
252 | }; | |
253 | ||
1da177e4 LT |
254 | #ifdef CONFIG_HUGETLB_PAGE |
255 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
256 | #endif | |
257 | ||
88c58f3b RK |
258 | /* |
259 | * Initialise the consistent memory allocation. | |
260 | */ | |
261 | static int __init consistent_init(void) | |
262 | { | |
263 | int ret = 0; | |
264 | pgd_t *pgd; | |
516295e5 | 265 | pud_t *pud; |
88c58f3b RK |
266 | pmd_t *pmd; |
267 | pte_t *pte; | |
268 | int i = 0; | |
99d1717d | 269 | unsigned long base = consistent_base; |
53cbcbcf | 270 | unsigned long num_ptes = (CONSISTENT_END - base) >> PMD_SHIFT; |
99d1717d JM |
271 | |
272 | consistent_pte = kmalloc(num_ptes * sizeof(pte_t), GFP_KERNEL); | |
273 | if (!consistent_pte) { | |
274 | pr_err("%s: no memory\n", __func__); | |
275 | return -ENOMEM; | |
276 | } | |
277 | ||
278 | pr_debug("DMA memory: 0x%08lx - 0x%08lx:\n", base, CONSISTENT_END); | |
279 | consistent_head.vm_start = base; | |
88c58f3b RK |
280 | |
281 | do { | |
282 | pgd = pgd_offset(&init_mm, base); | |
516295e5 RK |
283 | |
284 | pud = pud_alloc(&init_mm, pgd, base); | |
285 | if (!pud) { | |
6b6f770b | 286 | pr_err("%s: no pud tables\n", __func__); |
516295e5 RK |
287 | ret = -ENOMEM; |
288 | break; | |
289 | } | |
290 | ||
291 | pmd = pmd_alloc(&init_mm, pud, base); | |
88c58f3b | 292 | if (!pmd) { |
6b6f770b | 293 | pr_err("%s: no pmd tables\n", __func__); |
88c58f3b RK |
294 | ret = -ENOMEM; |
295 | break; | |
296 | } | |
297 | WARN_ON(!pmd_none(*pmd)); | |
298 | ||
299 | pte = pte_alloc_kernel(pmd, base); | |
300 | if (!pte) { | |
6b6f770b | 301 | pr_err("%s: no pte tables\n", __func__); |
88c58f3b RK |
302 | ret = -ENOMEM; |
303 | break; | |
304 | } | |
305 | ||
306 | consistent_pte[i++] = pte; | |
e73fc88e | 307 | base += PMD_SIZE; |
88c58f3b RK |
308 | } while (base < CONSISTENT_END); |
309 | ||
310 | return ret; | |
311 | } | |
312 | ||
313 | core_initcall(consistent_init); | |
314 | ||
1da177e4 | 315 | static void * |
45cd5290 RK |
316 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, |
317 | const void *caller) | |
1da177e4 | 318 | { |
13ccf3ad | 319 | struct arm_vmregion *c; |
5bc23d32 RK |
320 | size_t align; |
321 | int bit; | |
1da177e4 | 322 | |
99d1717d | 323 | if (!consistent_pte) { |
6b6f770b | 324 | pr_err("%s: not initialised\n", __func__); |
ebd7a845 | 325 | dump_stack(); |
ebd7a845 RK |
326 | return NULL; |
327 | } | |
328 | ||
5bc23d32 RK |
329 | /* |
330 | * Align the virtual region allocation - maximum alignment is | |
331 | * a section size, minimum is a page size. This helps reduce | |
332 | * fragmentation of the DMA space, and also prevents allocations | |
333 | * smaller than a section from crossing a section boundary. | |
334 | */ | |
c947f69f | 335 | bit = fls(size - 1); |
5bc23d32 RK |
336 | if (bit > SECTION_SHIFT) |
337 | bit = SECTION_SHIFT; | |
338 | align = 1 << bit; | |
339 | ||
1da177e4 LT |
340 | /* |
341 | * Allocate a virtual address in the consistent mapping region. | |
342 | */ | |
5bc23d32 | 343 | c = arm_vmregion_alloc(&consistent_head, align, size, |
45cd5290 | 344 | gfp & ~(__GFP_DMA | __GFP_HIGHMEM), caller); |
1da177e4 | 345 | if (c) { |
37134cd5 | 346 | pte_t *pte; |
37134cd5 KH |
347 | int idx = CONSISTENT_PTE_INDEX(c->vm_start); |
348 | u32 off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
1da177e4 | 349 | |
37134cd5 | 350 | pte = consistent_pte[idx] + off; |
1da177e4 LT |
351 | c->vm_pages = page; |
352 | ||
1da177e4 LT |
353 | do { |
354 | BUG_ON(!pte_none(*pte)); | |
355 | ||
ad1ae2fe | 356 | set_pte_ext(pte, mk_pte(page, prot), 0); |
1da177e4 LT |
357 | page++; |
358 | pte++; | |
37134cd5 KH |
359 | off++; |
360 | if (off >= PTRS_PER_PTE) { | |
361 | off = 0; | |
362 | pte = consistent_pte[++idx]; | |
363 | } | |
1da177e4 LT |
364 | } while (size -= PAGE_SIZE); |
365 | ||
2be23c47 RK |
366 | dsb(); |
367 | ||
1da177e4 LT |
368 | return (void *)c->vm_start; |
369 | } | |
1da177e4 LT |
370 | return NULL; |
371 | } | |
695ae0af RK |
372 | |
373 | static void __dma_free_remap(void *cpu_addr, size_t size) | |
374 | { | |
375 | struct arm_vmregion *c; | |
376 | unsigned long addr; | |
377 | pte_t *ptep; | |
378 | int idx; | |
379 | u32 off; | |
380 | ||
381 | c = arm_vmregion_find_remove(&consistent_head, (unsigned long)cpu_addr); | |
382 | if (!c) { | |
6b6f770b | 383 | pr_err("%s: trying to free invalid coherent area: %p\n", |
695ae0af RK |
384 | __func__, cpu_addr); |
385 | dump_stack(); | |
386 | return; | |
387 | } | |
388 | ||
389 | if ((c->vm_end - c->vm_start) != size) { | |
6b6f770b | 390 | pr_err("%s: freeing wrong coherent size (%ld != %d)\n", |
695ae0af RK |
391 | __func__, c->vm_end - c->vm_start, size); |
392 | dump_stack(); | |
393 | size = c->vm_end - c->vm_start; | |
394 | } | |
395 | ||
396 | idx = CONSISTENT_PTE_INDEX(c->vm_start); | |
397 | off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1); | |
398 | ptep = consistent_pte[idx] + off; | |
399 | addr = c->vm_start; | |
400 | do { | |
401 | pte_t pte = ptep_get_and_clear(&init_mm, addr, ptep); | |
695ae0af RK |
402 | |
403 | ptep++; | |
404 | addr += PAGE_SIZE; | |
405 | off++; | |
406 | if (off >= PTRS_PER_PTE) { | |
407 | off = 0; | |
408 | ptep = consistent_pte[++idx]; | |
409 | } | |
410 | ||
acaac256 | 411 | if (pte_none(pte) || !pte_present(pte)) |
6b6f770b MS |
412 | pr_crit("%s: bad page in kernel page table\n", |
413 | __func__); | |
695ae0af RK |
414 | } while (size -= PAGE_SIZE); |
415 | ||
416 | flush_tlb_kernel_range(c->vm_start, c->vm_end); | |
417 | ||
418 | arm_vmregion_free(&consistent_head, c); | |
419 | } | |
420 | ||
f99d6034 MS |
421 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
422 | { | |
423 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
424 | pgprot_writecombine(prot) : | |
425 | pgprot_dmacoherent(prot); | |
426 | return prot; | |
427 | } | |
428 | ||
ab6494f0 | 429 | #else /* !CONFIG_MMU */ |
695ae0af | 430 | |
45cd5290 | 431 | #define __dma_alloc_remap(page, size, gfp, prot, c) page_address(page) |
31ebf944 | 432 | #define __dma_free_remap(addr, size) do { } while (0) |
f99d6034 | 433 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
31ebf944 RK |
434 | |
435 | #endif /* CONFIG_MMU */ | |
436 | ||
ab6494f0 CM |
437 | static void * |
438 | __dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, gfp_t gfp, | |
45cd5290 | 439 | pgprot_t prot, const void *caller) |
ab6494f0 | 440 | { |
04da5694 | 441 | struct page *page; |
31ebf944 | 442 | void *addr; |
ab6494f0 | 443 | |
ea2e7057 SB |
444 | /* |
445 | * Following is a work-around (a.k.a. hack) to prevent pages | |
446 | * with __GFP_COMP being passed to split_page() which cannot | |
447 | * handle them. The real problem is that this flag probably | |
448 | * should be 0 on ARM as it is not supported on this | |
449 | * platform; see CONFIG_HUGETLBFS. | |
450 | */ | |
451 | gfp &= ~(__GFP_COMP); | |
452 | ||
553ac788 | 453 | *handle = DMA_ERROR_CODE; |
04da5694 | 454 | size = PAGE_ALIGN(size); |
ab6494f0 | 455 | |
04da5694 RK |
456 | page = __dma_alloc_buffer(dev, size, gfp); |
457 | if (!page) | |
458 | return NULL; | |
ab6494f0 | 459 | |
31ebf944 | 460 | if (!arch_is_coherent()) |
45cd5290 | 461 | addr = __dma_alloc_remap(page, size, gfp, prot, caller); |
31ebf944 RK |
462 | else |
463 | addr = page_address(page); | |
695ae0af | 464 | |
31ebf944 | 465 | if (addr) |
9eedd963 | 466 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
d8e89b47 RK |
467 | else |
468 | __dma_free_buffer(page, size); | |
695ae0af | 469 | |
31ebf944 RK |
470 | return addr; |
471 | } | |
1da177e4 LT |
472 | |
473 | /* | |
474 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
475 | * virtual and bus address for that space. | |
476 | */ | |
f99d6034 MS |
477 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
478 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 479 | { |
f99d6034 | 480 | pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); |
1fe53268 DES |
481 | void *memory; |
482 | ||
483 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
484 | return memory; | |
485 | ||
f99d6034 | 486 | return __dma_alloc(dev, size, handle, gfp, prot, |
45cd5290 | 487 | __builtin_return_address(0)); |
1da177e4 | 488 | } |
1da177e4 LT |
489 | |
490 | /* | |
f99d6034 | 491 | * Create userspace mapping for the DMA-coherent memory. |
1da177e4 | 492 | */ |
f99d6034 MS |
493 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
494 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
495 | struct dma_attrs *attrs) | |
1da177e4 | 496 | { |
ab6494f0 CM |
497 | int ret = -ENXIO; |
498 | #ifdef CONFIG_MMU | |
13ccf3ad RK |
499 | unsigned long user_size, kern_size; |
500 | struct arm_vmregion *c; | |
1da177e4 | 501 | |
f99d6034 MS |
502 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
503 | ||
47142f07 MS |
504 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
505 | return ret; | |
506 | ||
1da177e4 LT |
507 | user_size = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
508 | ||
13ccf3ad | 509 | c = arm_vmregion_find(&consistent_head, (unsigned long)cpu_addr); |
1da177e4 LT |
510 | if (c) { |
511 | unsigned long off = vma->vm_pgoff; | |
512 | ||
513 | kern_size = (c->vm_end - c->vm_start) >> PAGE_SHIFT; | |
514 | ||
515 | if (off < kern_size && | |
516 | user_size <= (kern_size - off)) { | |
1da177e4 LT |
517 | ret = remap_pfn_range(vma, vma->vm_start, |
518 | page_to_pfn(c->vm_pages) + off, | |
519 | user_size << PAGE_SHIFT, | |
520 | vma->vm_page_prot); | |
521 | } | |
522 | } | |
ab6494f0 | 523 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
524 | |
525 | return ret; | |
526 | } | |
527 | ||
1da177e4 LT |
528 | /* |
529 | * free a page as defined by the above mapping. | |
5edf71ae | 530 | * Must not be called with IRQs disabled. |
1da177e4 | 531 | */ |
f99d6034 MS |
532 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
533 | dma_addr_t handle, struct dma_attrs *attrs) | |
1da177e4 | 534 | { |
5edf71ae RK |
535 | WARN_ON(irqs_disabled()); |
536 | ||
1fe53268 DES |
537 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
538 | return; | |
539 | ||
3e82d012 RK |
540 | size = PAGE_ALIGN(size); |
541 | ||
695ae0af RK |
542 | if (!arch_is_coherent()) |
543 | __dma_free_remap(cpu_addr, size); | |
7a9a32a9 | 544 | |
9eedd963 | 545 | __dma_free_buffer(pfn_to_page(dma_to_pfn(dev, handle)), size); |
1da177e4 | 546 | } |
1da177e4 | 547 | |
4ea0d737 | 548 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
549 | size_t size, enum dma_data_direction dir, |
550 | void (*op)(const void *, size_t, int)) | |
43377453 NP |
551 | { |
552 | /* | |
553 | * A single sg entry may refer to multiple physically contiguous | |
554 | * pages. But we still need to process highmem pages individually. | |
555 | * If highmem is not configured then the bulk of this loop gets | |
556 | * optimized out. | |
557 | */ | |
558 | size_t left = size; | |
559 | do { | |
560 | size_t len = left; | |
93f1d629 RK |
561 | void *vaddr; |
562 | ||
563 | if (PageHighMem(page)) { | |
564 | if (len + offset > PAGE_SIZE) { | |
565 | if (offset >= PAGE_SIZE) { | |
566 | page += offset / PAGE_SIZE; | |
567 | offset %= PAGE_SIZE; | |
568 | } | |
569 | len = PAGE_SIZE - offset; | |
570 | } | |
571 | vaddr = kmap_high_get(page); | |
572 | if (vaddr) { | |
573 | vaddr += offset; | |
a9c9147e | 574 | op(vaddr, len, dir); |
93f1d629 | 575 | kunmap_high(page); |
7e5a69e8 | 576 | } else if (cache_is_vipt()) { |
39af22a7 NP |
577 | /* unmapped pages might still be cached */ |
578 | vaddr = kmap_atomic(page); | |
7e5a69e8 | 579 | op(vaddr + offset, len, dir); |
39af22a7 | 580 | kunmap_atomic(vaddr); |
43377453 | 581 | } |
93f1d629 RK |
582 | } else { |
583 | vaddr = page_address(page) + offset; | |
a9c9147e | 584 | op(vaddr, len, dir); |
43377453 | 585 | } |
43377453 NP |
586 | offset = 0; |
587 | page++; | |
588 | left -= len; | |
589 | } while (left); | |
590 | } | |
4ea0d737 | 591 | |
51fde349 MS |
592 | /* |
593 | * Make an area consistent for devices. | |
594 | * Note: Drivers should NOT use this function directly, as it will break | |
595 | * platforms with CONFIG_DMABOUNCE. | |
596 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
597 | */ | |
598 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
599 | size_t size, enum dma_data_direction dir) |
600 | { | |
65af191a | 601 | unsigned long paddr; |
65af191a | 602 | |
a9c9147e | 603 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
604 | |
605 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
606 | if (dir == DMA_FROM_DEVICE) { |
607 | outer_inv_range(paddr, paddr + size); | |
608 | } else { | |
609 | outer_clean_range(paddr, paddr + size); | |
610 | } | |
611 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 612 | } |
4ea0d737 | 613 | |
51fde349 | 614 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
615 | size_t size, enum dma_data_direction dir) |
616 | { | |
2ffe2da3 RK |
617 | unsigned long paddr = page_to_phys(page) + off; |
618 | ||
619 | /* FIXME: non-speculating: not required */ | |
620 | /* don't bother invalidating if DMA to device */ | |
621 | if (dir != DMA_TO_DEVICE) | |
622 | outer_inv_range(paddr, paddr + size); | |
623 | ||
a9c9147e | 624 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
c0177800 CM |
625 | |
626 | /* | |
627 | * Mark the D-cache clean for this page to avoid extra flushing. | |
628 | */ | |
629 | if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE) | |
630 | set_bit(PG_dcache_clean, &page->flags); | |
4ea0d737 | 631 | } |
43377453 | 632 | |
afd1a321 | 633 | /** |
2a550e73 | 634 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
635 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
636 | * @sg: list of buffers | |
637 | * @nents: number of buffers to map | |
638 | * @dir: DMA transfer direction | |
639 | * | |
640 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
641 | * This is the scatter-gather version of the dma_map_single interface. | |
642 | * Here the scatter gather list elements are each tagged with the | |
643 | * appropriate dma address and length. They are obtained via | |
644 | * sg_dma_{address,length}. | |
645 | * | |
646 | * Device ownership issues as mentioned for dma_map_single are the same | |
647 | * here. | |
648 | */ | |
2dc6a016 MS |
649 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
650 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 651 | { |
2a550e73 | 652 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 653 | struct scatterlist *s; |
01135d92 | 654 | int i, j; |
afd1a321 RK |
655 | |
656 | for_each_sg(sg, s, nents, i) { | |
2a550e73 MS |
657 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
658 | s->length, dir, attrs); | |
01135d92 RK |
659 | if (dma_mapping_error(dev, s->dma_address)) |
660 | goto bad_mapping; | |
afd1a321 | 661 | } |
afd1a321 | 662 | return nents; |
01135d92 RK |
663 | |
664 | bad_mapping: | |
665 | for_each_sg(sg, s, i, j) | |
2a550e73 | 666 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 667 | return 0; |
afd1a321 | 668 | } |
afd1a321 RK |
669 | |
670 | /** | |
2a550e73 | 671 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
672 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
673 | * @sg: list of buffers | |
0adfca6f | 674 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
675 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
676 | * | |
677 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
678 | * rules concerning calls here are the same as for dma_unmap_single(). | |
679 | */ | |
2dc6a016 MS |
680 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
681 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 682 | { |
2a550e73 | 683 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 684 | struct scatterlist *s; |
2a550e73 | 685 | |
01135d92 RK |
686 | int i; |
687 | ||
688 | for_each_sg(sg, s, nents, i) | |
2a550e73 | 689 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 690 | } |
afd1a321 RK |
691 | |
692 | /** | |
2a550e73 | 693 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
694 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
695 | * @sg: list of buffers | |
696 | * @nents: number of buffers to map (returned from dma_map_sg) | |
697 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
698 | */ | |
2dc6a016 | 699 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
700 | int nents, enum dma_data_direction dir) |
701 | { | |
2a550e73 | 702 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
703 | struct scatterlist *s; |
704 | int i; | |
705 | ||
2a550e73 MS |
706 | for_each_sg(sg, s, nents, i) |
707 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
708 | dir); | |
afd1a321 | 709 | } |
afd1a321 RK |
710 | |
711 | /** | |
2a550e73 | 712 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
713 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
714 | * @sg: list of buffers | |
715 | * @nents: number of buffers to map (returned from dma_map_sg) | |
716 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
717 | */ | |
2dc6a016 | 718 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
719 | int nents, enum dma_data_direction dir) |
720 | { | |
2a550e73 | 721 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
722 | struct scatterlist *s; |
723 | int i; | |
724 | ||
2a550e73 MS |
725 | for_each_sg(sg, s, nents, i) |
726 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
727 | dir); | |
afd1a321 | 728 | } |
24056f52 | 729 | |
022ae537 RK |
730 | /* |
731 | * Return whether the given device DMA address mask can be supported | |
732 | * properly. For example, if your device can only drive the low 24-bits | |
733 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
734 | * to this function. | |
735 | */ | |
736 | int dma_supported(struct device *dev, u64 mask) | |
737 | { | |
738 | if (mask < (u64)arm_dma_limit) | |
739 | return 0; | |
740 | return 1; | |
741 | } | |
742 | EXPORT_SYMBOL(dma_supported); | |
743 | ||
2dc6a016 | 744 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
745 | { |
746 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
747 | return -EIO; | |
748 | ||
022ae537 | 749 | *dev->dma_mask = dma_mask; |
022ae537 RK |
750 | |
751 | return 0; | |
752 | } | |
022ae537 | 753 | |
24056f52 RK |
754 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
755 | ||
756 | static int __init dma_debug_do_init(void) | |
757 | { | |
45cd5290 RK |
758 | #ifdef CONFIG_MMU |
759 | arm_vmregion_create_proc("dma-mappings", &consistent_head); | |
760 | #endif | |
24056f52 RK |
761 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); |
762 | return 0; | |
763 | } | |
764 | fs_initcall(dma_debug_do_init); |