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Commit | Line | Data |
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1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
11a5aa32 | 12 | #include <linux/bootmem.h> |
1da177e4 LT |
13 | #include <linux/module.h> |
14 | #include <linux/mm.h> | |
36d0fd21 | 15 | #include <linux/genalloc.h> |
5a0e3ad6 | 16 | #include <linux/gfp.h> |
1da177e4 LT |
17 | #include <linux/errno.h> |
18 | #include <linux/list.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/device.h> | |
21 | #include <linux/dma-mapping.h> | |
c7909509 | 22 | #include <linux/dma-contiguous.h> |
39af22a7 | 23 | #include <linux/highmem.h> |
c7909509 | 24 | #include <linux/memblock.h> |
99d1717d | 25 | #include <linux/slab.h> |
4ce63fcd | 26 | #include <linux/iommu.h> |
e9da6e99 | 27 | #include <linux/io.h> |
4ce63fcd | 28 | #include <linux/vmalloc.h> |
158e8bfe | 29 | #include <linux/sizes.h> |
a254129e | 30 | #include <linux/cma.h> |
1da177e4 | 31 | |
23759dc6 | 32 | #include <asm/memory.h> |
43377453 | 33 | #include <asm/highmem.h> |
1da177e4 | 34 | #include <asm/cacheflush.h> |
1da177e4 | 35 | #include <asm/tlbflush.h> |
99d1717d | 36 | #include <asm/mach/arch.h> |
4ce63fcd | 37 | #include <asm/dma-iommu.h> |
c7909509 MS |
38 | #include <asm/mach/map.h> |
39 | #include <asm/system_info.h> | |
40 | #include <asm/dma-contiguous.h> | |
37134cd5 | 41 | |
1234e3fd | 42 | #include "dma.h" |
022ae537 RK |
43 | #include "mm.h" |
44 | ||
b4268676 RV |
45 | struct arm_dma_alloc_args { |
46 | struct device *dev; | |
47 | size_t size; | |
48 | gfp_t gfp; | |
49 | pgprot_t prot; | |
50 | const void *caller; | |
51 | bool want_vaddr; | |
f1270896 | 52 | int coherent_flag; |
b4268676 RV |
53 | }; |
54 | ||
55 | struct arm_dma_free_args { | |
56 | struct device *dev; | |
57 | size_t size; | |
58 | void *cpu_addr; | |
59 | struct page *page; | |
60 | bool want_vaddr; | |
61 | }; | |
62 | ||
f1270896 GC |
63 | #define NORMAL 0 |
64 | #define COHERENT 1 | |
65 | ||
b4268676 RV |
66 | struct arm_dma_allocator { |
67 | void *(*alloc)(struct arm_dma_alloc_args *args, | |
68 | struct page **ret_page); | |
69 | void (*free)(struct arm_dma_free_args *args); | |
70 | }; | |
71 | ||
19e6e5e5 RV |
72 | struct arm_dma_buffer { |
73 | struct list_head list; | |
74 | void *virt; | |
b4268676 | 75 | struct arm_dma_allocator *allocator; |
19e6e5e5 RV |
76 | }; |
77 | ||
78 | static LIST_HEAD(arm_dma_bufs); | |
79 | static DEFINE_SPINLOCK(arm_dma_bufs_lock); | |
80 | ||
81 | static struct arm_dma_buffer *arm_dma_buffer_find(void *virt) | |
82 | { | |
83 | struct arm_dma_buffer *buf, *found = NULL; | |
84 | unsigned long flags; | |
85 | ||
86 | spin_lock_irqsave(&arm_dma_bufs_lock, flags); | |
87 | list_for_each_entry(buf, &arm_dma_bufs, list) { | |
88 | if (buf->virt == virt) { | |
89 | list_del(&buf->list); | |
90 | found = buf; | |
91 | break; | |
92 | } | |
93 | } | |
94 | spin_unlock_irqrestore(&arm_dma_bufs_lock, flags); | |
95 | return found; | |
96 | } | |
97 | ||
15237e1f MS |
98 | /* |
99 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
100 | * is either exclusively owned by the CPU (and therefore may be accessed | |
101 | * by it) or exclusively owned by the DMA device. These helper functions | |
102 | * represent the transitions between these two ownership states. | |
103 | * | |
104 | * Note, however, that on later ARMs, this notion does not work due to | |
105 | * speculative prefetches. We model our approach on the assumption that | |
106 | * the CPU does do speculative prefetches, which means we clean caches | |
107 | * before transfers and delay cache invalidation until transfer completion. | |
108 | * | |
15237e1f | 109 | */ |
51fde349 | 110 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 111 | size_t, enum dma_data_direction); |
51fde349 | 112 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
113 | size_t, enum dma_data_direction); |
114 | ||
2dc6a016 MS |
115 | /** |
116 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
117 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
118 | * @page: page that buffer resides in | |
119 | * @offset: offset into page for start of buffer | |
120 | * @size: size of buffer to map | |
121 | * @dir: DMA transfer direction | |
122 | * | |
123 | * Ensure that any data held in the cache is appropriately discarded | |
124 | * or written back. | |
125 | * | |
126 | * The device owns this memory once this call has completed. The CPU | |
127 | * can regain ownership by calling dma_unmap_page(). | |
128 | */ | |
51fde349 | 129 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 | 130 | unsigned long offset, size_t size, enum dma_data_direction dir, |
00085f1e | 131 | unsigned long attrs) |
2dc6a016 | 132 | { |
00085f1e | 133 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
51fde349 MS |
134 | __dma_page_cpu_to_dev(page, offset, size, dir); |
135 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
136 | } |
137 | ||
dd37e940 RH |
138 | static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page, |
139 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
00085f1e | 140 | unsigned long attrs) |
dd37e940 RH |
141 | { |
142 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
143 | } | |
144 | ||
2dc6a016 MS |
145 | /** |
146 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
147 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
148 | * @handle: DMA address of buffer | |
149 | * @size: size of buffer (same as passed to dma_map_page) | |
150 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
151 | * | |
152 | * Unmap a page streaming mode DMA translation. The handle and size | |
153 | * must match what was provided in the previous dma_map_page() call. | |
154 | * All other usages are undefined. | |
155 | * | |
156 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
157 | * whatever the device wrote there. | |
158 | */ | |
51fde349 | 159 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
00085f1e | 160 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
2dc6a016 | 161 | { |
00085f1e | 162 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
51fde349 MS |
163 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
164 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
165 | } |
166 | ||
51fde349 | 167 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
168 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
169 | { | |
170 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
171 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 172 | __dma_page_dev_to_cpu(page, offset, size, dir); |
2dc6a016 MS |
173 | } |
174 | ||
51fde349 | 175 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
176 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
177 | { | |
178 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
179 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
dd37e940 | 180 | __dma_page_cpu_to_dev(page, offset, size, dir); |
2dc6a016 MS |
181 | } |
182 | ||
9eef8b8c CH |
183 | static int arm_dma_mapping_error(struct device *dev, dma_addr_t dma_addr) |
184 | { | |
185 | return dma_addr == ARM_MAPPING_ERROR; | |
186 | } | |
187 | ||
5299709d | 188 | const struct dma_map_ops arm_dma_ops = { |
f99d6034 MS |
189 | .alloc = arm_dma_alloc, |
190 | .free = arm_dma_free, | |
191 | .mmap = arm_dma_mmap, | |
dc2832e1 | 192 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
193 | .map_page = arm_dma_map_page, |
194 | .unmap_page = arm_dma_unmap_page, | |
195 | .map_sg = arm_dma_map_sg, | |
196 | .unmap_sg = arm_dma_unmap_sg, | |
197 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
198 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
199 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
200 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
9eef8b8c | 201 | .mapping_error = arm_dma_mapping_error, |
418a7a7e | 202 | .dma_supported = arm_dma_supported, |
2dc6a016 MS |
203 | }; |
204 | EXPORT_SYMBOL(arm_dma_ops); | |
205 | ||
dd37e940 | 206 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, |
00085f1e | 207 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs); |
dd37e940 | 208 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 209 | dma_addr_t handle, unsigned long attrs); |
55af8a91 ML |
210 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
211 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
00085f1e | 212 | unsigned long attrs); |
dd37e940 | 213 | |
5299709d | 214 | const struct dma_map_ops arm_coherent_dma_ops = { |
dd37e940 RH |
215 | .alloc = arm_coherent_dma_alloc, |
216 | .free = arm_coherent_dma_free, | |
55af8a91 | 217 | .mmap = arm_coherent_dma_mmap, |
dd37e940 RH |
218 | .get_sgtable = arm_dma_get_sgtable, |
219 | .map_page = arm_coherent_dma_map_page, | |
220 | .map_sg = arm_dma_map_sg, | |
9eef8b8c | 221 | .mapping_error = arm_dma_mapping_error, |
418a7a7e | 222 | .dma_supported = arm_dma_supported, |
dd37e940 RH |
223 | }; |
224 | EXPORT_SYMBOL(arm_coherent_dma_ops); | |
225 | ||
9f28cde0 RK |
226 | static int __dma_supported(struct device *dev, u64 mask, bool warn) |
227 | { | |
228 | unsigned long max_dma_pfn; | |
229 | ||
230 | /* | |
231 | * If the mask allows for more memory than we can address, | |
232 | * and we actually have that much memory, then we must | |
233 | * indicate that DMA to this device is not supported. | |
234 | */ | |
235 | if (sizeof(mask) != sizeof(dma_addr_t) && | |
236 | mask > (dma_addr_t)~0 && | |
8bf1268f | 237 | dma_to_pfn(dev, ~0) < max_pfn - 1) { |
9f28cde0 RK |
238 | if (warn) { |
239 | dev_warn(dev, "Coherent DMA mask %#llx is larger than dma_addr_t allows\n", | |
240 | mask); | |
241 | dev_warn(dev, "Driver did not use or check the return value from dma_set_coherent_mask()?\n"); | |
242 | } | |
243 | return 0; | |
244 | } | |
245 | ||
246 | max_dma_pfn = min(max_pfn, arm_dma_pfn_limit); | |
247 | ||
248 | /* | |
249 | * Translate the device's DMA mask to a PFN limit. This | |
250 | * PFN number includes the page which we can DMA to. | |
251 | */ | |
252 | if (dma_to_pfn(dev, mask) < max_dma_pfn) { | |
253 | if (warn) | |
254 | dev_warn(dev, "Coherent DMA mask %#llx (pfn %#lx-%#lx) covers a smaller range of system memory than the DMA zone pfn 0x0-%#lx\n", | |
255 | mask, | |
256 | dma_to_pfn(dev, 0), dma_to_pfn(dev, mask) + 1, | |
257 | max_dma_pfn + 1); | |
258 | return 0; | |
259 | } | |
260 | ||
261 | return 1; | |
262 | } | |
263 | ||
ab6494f0 CM |
264 | static u64 get_coherent_dma_mask(struct device *dev) |
265 | { | |
4dcfa600 | 266 | u64 mask = (u64)DMA_BIT_MASK(32); |
ab6494f0 CM |
267 | |
268 | if (dev) { | |
269 | mask = dev->coherent_dma_mask; | |
270 | ||
271 | /* | |
272 | * Sanity check the DMA mask - it must be non-zero, and | |
273 | * must be able to be satisfied by a DMA allocation. | |
274 | */ | |
275 | if (mask == 0) { | |
276 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
277 | return 0; | |
278 | } | |
279 | ||
9f28cde0 | 280 | if (!__dma_supported(dev, mask, true)) |
ab6494f0 | 281 | return 0; |
ab6494f0 | 282 | } |
1da177e4 | 283 | |
ab6494f0 CM |
284 | return mask; |
285 | } | |
286 | ||
f1270896 | 287 | static void __dma_clear_buffer(struct page *page, size_t size, int coherent_flag) |
c7909509 | 288 | { |
c7909509 MS |
289 | /* |
290 | * Ensure that the allocated pages are zeroed, and that any data | |
291 | * lurking in the kernel direct-mapped region is invalidated. | |
292 | */ | |
9848e48f MS |
293 | if (PageHighMem(page)) { |
294 | phys_addr_t base = __pfn_to_phys(page_to_pfn(page)); | |
295 | phys_addr_t end = base + size; | |
296 | while (size > 0) { | |
297 | void *ptr = kmap_atomic(page); | |
298 | memset(ptr, 0, PAGE_SIZE); | |
f1270896 GC |
299 | if (coherent_flag != COHERENT) |
300 | dmac_flush_range(ptr, ptr + PAGE_SIZE); | |
9848e48f MS |
301 | kunmap_atomic(ptr); |
302 | page++; | |
303 | size -= PAGE_SIZE; | |
304 | } | |
f1270896 GC |
305 | if (coherent_flag != COHERENT) |
306 | outer_flush_range(base, end); | |
9848e48f MS |
307 | } else { |
308 | void *ptr = page_address(page); | |
4ce63fcd | 309 | memset(ptr, 0, size); |
f1270896 GC |
310 | if (coherent_flag != COHERENT) { |
311 | dmac_flush_range(ptr, ptr + size); | |
312 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
313 | } | |
4ce63fcd | 314 | } |
c7909509 MS |
315 | } |
316 | ||
7a9a32a9 RK |
317 | /* |
318 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
319 | * specified gfp mask. Note that 'size' must be page aligned. | |
320 | */ | |
f1270896 GC |
321 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, |
322 | gfp_t gfp, int coherent_flag) | |
7a9a32a9 RK |
323 | { |
324 | unsigned long order = get_order(size); | |
325 | struct page *page, *p, *e; | |
7a9a32a9 RK |
326 | |
327 | page = alloc_pages(gfp, order); | |
328 | if (!page) | |
329 | return NULL; | |
330 | ||
331 | /* | |
332 | * Now split the huge page and free the excess pages | |
333 | */ | |
334 | split_page(page, order); | |
335 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
336 | __free_page(p); | |
337 | ||
f1270896 | 338 | __dma_clear_buffer(page, size, coherent_flag); |
7a9a32a9 RK |
339 | |
340 | return page; | |
341 | } | |
342 | ||
343 | /* | |
344 | * Free a DMA buffer. 'size' must be page aligned. | |
345 | */ | |
346 | static void __dma_free_buffer(struct page *page, size_t size) | |
347 | { | |
348 | struct page *e = page + (size >> PAGE_SHIFT); | |
349 | ||
350 | while (page < e) { | |
351 | __free_page(page); | |
352 | page++; | |
353 | } | |
354 | } | |
355 | ||
e9da6e99 | 356 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
9848e48f | 357 | pgprot_t prot, struct page **ret_page, |
f1270896 | 358 | const void *caller, bool want_vaddr, |
712c604d | 359 | int coherent_flag, gfp_t gfp); |
99d1717d | 360 | |
e9da6e99 MS |
361 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
362 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 363 | const void *caller, bool want_vaddr); |
99d1717d | 364 | |
e9da6e99 MS |
365 | static void * |
366 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
367 | const void *caller) | |
99d1717d | 368 | { |
e9da6e99 MS |
369 | /* |
370 | * DMA allocation can be mapped to user space, so lets | |
371 | * set VM_USERMAP flags too. | |
372 | */ | |
513510dd LA |
373 | return dma_common_contiguous_remap(page, size, |
374 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
375 | prot, caller); | |
99d1717d | 376 | } |
1da177e4 | 377 | |
e9da6e99 | 378 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 379 | { |
513510dd LA |
380 | dma_common_free_remap(cpu_addr, size, |
381 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
88c58f3b | 382 | } |
88c58f3b | 383 | |
6e5267aa | 384 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
b337e1c4 | 385 | static struct gen_pool *atomic_pool __ro_after_init; |
6e5267aa | 386 | |
b337e1c4 | 387 | static size_t atomic_pool_size __initdata = DEFAULT_DMA_COHERENT_POOL_SIZE; |
c7909509 MS |
388 | |
389 | static int __init early_coherent_pool(char *p) | |
390 | { | |
36d0fd21 | 391 | atomic_pool_size = memparse(p, &p); |
c7909509 MS |
392 | return 0; |
393 | } | |
394 | early_param("coherent_pool", early_coherent_pool); | |
395 | ||
396 | /* | |
397 | * Initialise the coherent pool for atomic allocations. | |
398 | */ | |
e9da6e99 | 399 | static int __init atomic_pool_init(void) |
c7909509 | 400 | { |
71b55663 | 401 | pgprot_t prot = pgprot_dmacoherent(PAGE_KERNEL); |
9d1400cf | 402 | gfp_t gfp = GFP_KERNEL | GFP_DMA; |
c7909509 MS |
403 | struct page *page; |
404 | void *ptr; | |
c7909509 | 405 | |
36d0fd21 LA |
406 | atomic_pool = gen_pool_create(PAGE_SHIFT, -1); |
407 | if (!atomic_pool) | |
408 | goto out; | |
f1270896 GC |
409 | /* |
410 | * The atomic pool is only used for non-coherent allocations | |
411 | * so we must pass NORMAL for coherent_flag. | |
412 | */ | |
e464ef16 | 413 | if (dev_get_cma_area(NULL)) |
36d0fd21 | 414 | ptr = __alloc_from_contiguous(NULL, atomic_pool_size, prot, |
712c604d LS |
415 | &page, atomic_pool_init, true, NORMAL, |
416 | GFP_KERNEL); | |
e9da6e99 | 417 | else |
36d0fd21 | 418 | ptr = __alloc_remap_buffer(NULL, atomic_pool_size, gfp, prot, |
6e8266e3 | 419 | &page, atomic_pool_init, true); |
c7909509 | 420 | if (ptr) { |
36d0fd21 LA |
421 | int ret; |
422 | ||
423 | ret = gen_pool_add_virt(atomic_pool, (unsigned long)ptr, | |
424 | page_to_phys(page), | |
425 | atomic_pool_size, -1); | |
426 | if (ret) | |
427 | goto destroy_genpool; | |
428 | ||
429 | gen_pool_set_algo(atomic_pool, | |
430 | gen_pool_first_fit_order_align, | |
acb62448 | 431 | NULL); |
bf31c5e0 | 432 | pr_info("DMA: preallocated %zu KiB pool for atomic coherent allocations\n", |
36d0fd21 | 433 | atomic_pool_size / 1024); |
c7909509 MS |
434 | return 0; |
435 | } | |
ec10665c | 436 | |
36d0fd21 LA |
437 | destroy_genpool: |
438 | gen_pool_destroy(atomic_pool); | |
439 | atomic_pool = NULL; | |
440 | out: | |
bf31c5e0 | 441 | pr_err("DMA: failed to allocate %zu KiB pool for atomic coherent allocation\n", |
36d0fd21 | 442 | atomic_pool_size / 1024); |
c7909509 MS |
443 | return -ENOMEM; |
444 | } | |
445 | /* | |
446 | * CMA is activated by core_initcall, so we must be called after it. | |
447 | */ | |
e9da6e99 | 448 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
449 | |
450 | struct dma_contig_early_reserve { | |
451 | phys_addr_t base; | |
452 | unsigned long size; | |
453 | }; | |
454 | ||
455 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
456 | ||
457 | static int dma_mmu_remap_num __initdata; | |
458 | ||
459 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
460 | { | |
461 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
462 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
463 | dma_mmu_remap_num++; | |
464 | } | |
465 | ||
466 | void __init dma_contiguous_remap(void) | |
467 | { | |
468 | int i; | |
469 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
470 | phys_addr_t start = dma_mmu_remap[i].base; | |
471 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
472 | struct map_desc map; | |
473 | unsigned long addr; | |
474 | ||
475 | if (end > arm_lowmem_limit) | |
476 | end = arm_lowmem_limit; | |
477 | if (start >= end) | |
39f78e70 | 478 | continue; |
c7909509 MS |
479 | |
480 | map.pfn = __phys_to_pfn(start); | |
481 | map.virtual = __phys_to_virt(start); | |
482 | map.length = end - start; | |
483 | map.type = MT_MEMORY_DMA_READY; | |
484 | ||
485 | /* | |
6b076991 RK |
486 | * Clear previous low-memory mapping to ensure that the |
487 | * TLB does not see any conflicting entries, then flush | |
488 | * the TLB of the old entries before creating new mappings. | |
489 | * | |
490 | * This ensures that any speculatively loaded TLB entries | |
491 | * (even though they may be rare) can not cause any problems, | |
492 | * and ensures that this code is architecturally compliant. | |
c7909509 MS |
493 | */ |
494 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 495 | addr += PMD_SIZE) |
c7909509 MS |
496 | pmd_clear(pmd_off_k(addr)); |
497 | ||
6b076991 RK |
498 | flush_tlb_kernel_range(__phys_to_virt(start), |
499 | __phys_to_virt(end)); | |
500 | ||
c7909509 MS |
501 | iotable_init(&map, 1); |
502 | } | |
503 | } | |
504 | ||
c7909509 MS |
505 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
506 | void *data) | |
507 | { | |
508 | struct page *page = virt_to_page(addr); | |
509 | pgprot_t prot = *(pgprot_t *)data; | |
510 | ||
511 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
512 | return 0; | |
513 | } | |
514 | ||
515 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
516 | { | |
517 | unsigned long start = (unsigned long) page_address(page); | |
518 | unsigned end = start + size; | |
519 | ||
520 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
c7909509 MS |
521 | flush_tlb_kernel_range(start, end); |
522 | } | |
523 | ||
524 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
525 | pgprot_t prot, struct page **ret_page, | |
6e8266e3 | 526 | const void *caller, bool want_vaddr) |
c7909509 MS |
527 | { |
528 | struct page *page; | |
6e8266e3 | 529 | void *ptr = NULL; |
f1270896 GC |
530 | /* |
531 | * __alloc_remap_buffer is only called when the device is | |
532 | * non-coherent | |
533 | */ | |
534 | page = __dma_alloc_buffer(dev, size, gfp, NORMAL); | |
c7909509 MS |
535 | if (!page) |
536 | return NULL; | |
6e8266e3 CC |
537 | if (!want_vaddr) |
538 | goto out; | |
c7909509 MS |
539 | |
540 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
541 | if (!ptr) { | |
542 | __dma_free_buffer(page, size); | |
543 | return NULL; | |
544 | } | |
545 | ||
6e8266e3 | 546 | out: |
c7909509 MS |
547 | *ret_page = page; |
548 | return ptr; | |
549 | } | |
550 | ||
e9da6e99 | 551 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 552 | { |
36d0fd21 | 553 | unsigned long val; |
e9da6e99 | 554 | void *ptr = NULL; |
c7909509 | 555 | |
36d0fd21 | 556 | if (!atomic_pool) { |
e9da6e99 | 557 | WARN(1, "coherent pool not initialised!\n"); |
c7909509 MS |
558 | return NULL; |
559 | } | |
560 | ||
36d0fd21 LA |
561 | val = gen_pool_alloc(atomic_pool, size); |
562 | if (val) { | |
563 | phys_addr_t phys = gen_pool_virt_to_phys(atomic_pool, val); | |
564 | ||
565 | *ret_page = phys_to_page(phys); | |
566 | ptr = (void *)val; | |
c7909509 | 567 | } |
e9da6e99 MS |
568 | |
569 | return ptr; | |
c7909509 MS |
570 | } |
571 | ||
21d0a759 HD |
572 | static bool __in_atomic_pool(void *start, size_t size) |
573 | { | |
36d0fd21 | 574 | return addr_in_gen_pool(atomic_pool, (unsigned long)start, size); |
21d0a759 HD |
575 | } |
576 | ||
e9da6e99 | 577 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 578 | { |
21d0a759 | 579 | if (!__in_atomic_pool(start, size)) |
c7909509 MS |
580 | return 0; |
581 | ||
36d0fd21 | 582 | gen_pool_free(atomic_pool, (unsigned long)start, size); |
e9da6e99 | 583 | |
c7909509 MS |
584 | return 1; |
585 | } | |
586 | ||
587 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
9848e48f | 588 | pgprot_t prot, struct page **ret_page, |
f1270896 | 589 | const void *caller, bool want_vaddr, |
712c604d | 590 | int coherent_flag, gfp_t gfp) |
c7909509 MS |
591 | { |
592 | unsigned long order = get_order(size); | |
593 | size_t count = size >> PAGE_SHIFT; | |
594 | struct page *page; | |
6e8266e3 | 595 | void *ptr = NULL; |
c7909509 | 596 | |
712c604d | 597 | page = dma_alloc_from_contiguous(dev, count, order, gfp); |
c7909509 MS |
598 | if (!page) |
599 | return NULL; | |
600 | ||
f1270896 | 601 | __dma_clear_buffer(page, size, coherent_flag); |
c7909509 | 602 | |
6e8266e3 CC |
603 | if (!want_vaddr) |
604 | goto out; | |
605 | ||
9848e48f MS |
606 | if (PageHighMem(page)) { |
607 | ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller); | |
608 | if (!ptr) { | |
609 | dma_release_from_contiguous(dev, page, count); | |
610 | return NULL; | |
611 | } | |
612 | } else { | |
613 | __dma_remap(page, size, prot); | |
614 | ptr = page_address(page); | |
615 | } | |
6e8266e3 CC |
616 | |
617 | out: | |
c7909509 | 618 | *ret_page = page; |
9848e48f | 619 | return ptr; |
c7909509 MS |
620 | } |
621 | ||
622 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
6e8266e3 | 623 | void *cpu_addr, size_t size, bool want_vaddr) |
c7909509 | 624 | { |
6e8266e3 CC |
625 | if (want_vaddr) { |
626 | if (PageHighMem(page)) | |
627 | __dma_free_remap(cpu_addr, size); | |
628 | else | |
629 | __dma_remap(page, size, PAGE_KERNEL); | |
630 | } | |
c7909509 MS |
631 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); |
632 | } | |
633 | ||
00085f1e | 634 | static inline pgprot_t __get_dma_pgprot(unsigned long attrs, pgprot_t prot) |
f99d6034 | 635 | { |
00085f1e KK |
636 | prot = (attrs & DMA_ATTR_WRITE_COMBINE) ? |
637 | pgprot_writecombine(prot) : | |
638 | pgprot_dmacoherent(prot); | |
f99d6034 MS |
639 | return prot; |
640 | } | |
641 | ||
c7909509 MS |
642 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
643 | struct page **ret_page) | |
ab6494f0 | 644 | { |
c7909509 | 645 | struct page *page; |
f1270896 GC |
646 | /* __alloc_simple_buffer is only called when the device is coherent */ |
647 | page = __dma_alloc_buffer(dev, size, gfp, COHERENT); | |
c7909509 MS |
648 | if (!page) |
649 | return NULL; | |
650 | ||
651 | *ret_page = page; | |
652 | return page_address(page); | |
653 | } | |
654 | ||
b4268676 RV |
655 | static void *simple_allocator_alloc(struct arm_dma_alloc_args *args, |
656 | struct page **ret_page) | |
657 | { | |
658 | return __alloc_simple_buffer(args->dev, args->size, args->gfp, | |
659 | ret_page); | |
660 | } | |
c7909509 | 661 | |
b4268676 RV |
662 | static void simple_allocator_free(struct arm_dma_free_args *args) |
663 | { | |
664 | __dma_free_buffer(args->page, args->size); | |
665 | } | |
666 | ||
667 | static struct arm_dma_allocator simple_allocator = { | |
668 | .alloc = simple_allocator_alloc, | |
669 | .free = simple_allocator_free, | |
670 | }; | |
671 | ||
672 | static void *cma_allocator_alloc(struct arm_dma_alloc_args *args, | |
673 | struct page **ret_page) | |
674 | { | |
675 | return __alloc_from_contiguous(args->dev, args->size, args->prot, | |
676 | ret_page, args->caller, | |
712c604d LS |
677 | args->want_vaddr, args->coherent_flag, |
678 | args->gfp); | |
b4268676 RV |
679 | } |
680 | ||
681 | static void cma_allocator_free(struct arm_dma_free_args *args) | |
682 | { | |
683 | __free_from_contiguous(args->dev, args->page, args->cpu_addr, | |
684 | args->size, args->want_vaddr); | |
685 | } | |
686 | ||
687 | static struct arm_dma_allocator cma_allocator = { | |
688 | .alloc = cma_allocator_alloc, | |
689 | .free = cma_allocator_free, | |
690 | }; | |
691 | ||
692 | static void *pool_allocator_alloc(struct arm_dma_alloc_args *args, | |
693 | struct page **ret_page) | |
694 | { | |
695 | return __alloc_from_pool(args->size, ret_page); | |
696 | } | |
697 | ||
698 | static void pool_allocator_free(struct arm_dma_free_args *args) | |
699 | { | |
700 | __free_from_pool(args->cpu_addr, args->size); | |
701 | } | |
702 | ||
703 | static struct arm_dma_allocator pool_allocator = { | |
704 | .alloc = pool_allocator_alloc, | |
705 | .free = pool_allocator_free, | |
706 | }; | |
707 | ||
708 | static void *remap_allocator_alloc(struct arm_dma_alloc_args *args, | |
709 | struct page **ret_page) | |
710 | { | |
711 | return __alloc_remap_buffer(args->dev, args->size, args->gfp, | |
712 | args->prot, ret_page, args->caller, | |
713 | args->want_vaddr); | |
714 | } | |
715 | ||
716 | static void remap_allocator_free(struct arm_dma_free_args *args) | |
717 | { | |
718 | if (args->want_vaddr) | |
719 | __dma_free_remap(args->cpu_addr, args->size); | |
720 | ||
721 | __dma_free_buffer(args->page, args->size); | |
722 | } | |
723 | ||
724 | static struct arm_dma_allocator remap_allocator = { | |
725 | .alloc = remap_allocator_alloc, | |
726 | .free = remap_allocator_free, | |
727 | }; | |
c7909509 MS |
728 | |
729 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
6e8266e3 | 730 | gfp_t gfp, pgprot_t prot, bool is_coherent, |
00085f1e | 731 | unsigned long attrs, const void *caller) |
c7909509 MS |
732 | { |
733 | u64 mask = get_coherent_dma_mask(dev); | |
3dd7ea92 | 734 | struct page *page = NULL; |
31ebf944 | 735 | void *addr; |
b4268676 | 736 | bool allowblock, cma; |
19e6e5e5 | 737 | struct arm_dma_buffer *buf; |
b4268676 RV |
738 | struct arm_dma_alloc_args args = { |
739 | .dev = dev, | |
740 | .size = PAGE_ALIGN(size), | |
741 | .gfp = gfp, | |
742 | .prot = prot, | |
743 | .caller = caller, | |
00085f1e | 744 | .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0), |
f1270896 | 745 | .coherent_flag = is_coherent ? COHERENT : NORMAL, |
b4268676 | 746 | }; |
ab6494f0 | 747 | |
c7909509 MS |
748 | #ifdef CONFIG_DMA_API_DEBUG |
749 | u64 limit = (mask + 1) & ~mask; | |
750 | if (limit && size >= limit) { | |
751 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
752 | size, mask); | |
753 | return NULL; | |
754 | } | |
755 | #endif | |
756 | ||
757 | if (!mask) | |
758 | return NULL; | |
759 | ||
9c18fcf7 AC |
760 | buf = kzalloc(sizeof(*buf), |
761 | gfp & ~(__GFP_DMA | __GFP_DMA32 | __GFP_HIGHMEM)); | |
19e6e5e5 RV |
762 | if (!buf) |
763 | return NULL; | |
764 | ||
c7909509 MS |
765 | if (mask < 0xffffffffULL) |
766 | gfp |= GFP_DMA; | |
767 | ||
ea2e7057 SB |
768 | /* |
769 | * Following is a work-around (a.k.a. hack) to prevent pages | |
770 | * with __GFP_COMP being passed to split_page() which cannot | |
771 | * handle them. The real problem is that this flag probably | |
772 | * should be 0 on ARM as it is not supported on this | |
773 | * platform; see CONFIG_HUGETLBFS. | |
774 | */ | |
775 | gfp &= ~(__GFP_COMP); | |
b4268676 | 776 | args.gfp = gfp; |
ea2e7057 | 777 | |
9eef8b8c | 778 | *handle = ARM_MAPPING_ERROR; |
b4268676 RV |
779 | allowblock = gfpflags_allow_blocking(gfp); |
780 | cma = allowblock ? dev_get_cma_area(dev) : false; | |
781 | ||
782 | if (cma) | |
783 | buf->allocator = &cma_allocator; | |
1655cf88 | 784 | else if (is_coherent) |
b4268676 RV |
785 | buf->allocator = &simple_allocator; |
786 | else if (allowblock) | |
787 | buf->allocator = &remap_allocator; | |
31ebf944 | 788 | else |
b4268676 RV |
789 | buf->allocator = &pool_allocator; |
790 | ||
791 | addr = buf->allocator->alloc(&args, &page); | |
695ae0af | 792 | |
19e6e5e5 RV |
793 | if (page) { |
794 | unsigned long flags; | |
795 | ||
9eedd963 | 796 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
b4268676 | 797 | buf->virt = args.want_vaddr ? addr : page; |
19e6e5e5 RV |
798 | |
799 | spin_lock_irqsave(&arm_dma_bufs_lock, flags); | |
800 | list_add(&buf->list, &arm_dma_bufs); | |
801 | spin_unlock_irqrestore(&arm_dma_bufs_lock, flags); | |
802 | } else { | |
803 | kfree(buf); | |
804 | } | |
695ae0af | 805 | |
b4268676 | 806 | return args.want_vaddr ? addr : page; |
31ebf944 | 807 | } |
1da177e4 LT |
808 | |
809 | /* | |
810 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
811 | * virtual and bus address for that space. | |
812 | */ | |
f99d6034 | 813 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
00085f1e | 814 | gfp_t gfp, unsigned long attrs) |
1da177e4 | 815 | { |
0ea1ec71 | 816 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
1fe53268 | 817 | |
dd37e940 | 818 | return __dma_alloc(dev, size, handle, gfp, prot, false, |
6e8266e3 | 819 | attrs, __builtin_return_address(0)); |
dd37e940 RH |
820 | } |
821 | ||
822 | static void *arm_coherent_dma_alloc(struct device *dev, size_t size, | |
00085f1e | 823 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs) |
dd37e940 | 824 | { |
21caf3a7 | 825 | return __dma_alloc(dev, size, handle, gfp, PAGE_KERNEL, true, |
6e8266e3 | 826 | attrs, __builtin_return_address(0)); |
1da177e4 | 827 | } |
1da177e4 | 828 | |
55af8a91 | 829 | static int __arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
f99d6034 | 830 | void *cpu_addr, dma_addr_t dma_addr, size_t size, |
00085f1e | 831 | unsigned long attrs) |
1da177e4 | 832 | { |
ea83f515 | 833 | int ret = -ENXIO; |
50262a4b MS |
834 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
835 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 836 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
837 | unsigned long off = vma->vm_pgoff; |
838 | ||
43fc509c | 839 | if (dma_mmap_from_dev_coherent(dev, vma, cpu_addr, size, &ret)) |
47142f07 MS |
840 | return ret; |
841 | ||
50262a4b MS |
842 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
843 | ret = remap_pfn_range(vma, vma->vm_start, | |
844 | pfn + off, | |
845 | vma->vm_end - vma->vm_start, | |
846 | vma->vm_page_prot); | |
847 | } | |
1da177e4 LT |
848 | |
849 | return ret; | |
850 | } | |
851 | ||
55af8a91 ML |
852 | /* |
853 | * Create userspace mapping for the DMA-coherent memory. | |
854 | */ | |
855 | static int arm_coherent_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
856 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
00085f1e | 857 | unsigned long attrs) |
55af8a91 ML |
858 | { |
859 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); | |
860 | } | |
861 | ||
862 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, | |
863 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
00085f1e | 864 | unsigned long attrs) |
55af8a91 | 865 | { |
55af8a91 | 866 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
55af8a91 ML |
867 | return __arm_dma_mmap(dev, vma, cpu_addr, dma_addr, size, attrs); |
868 | } | |
869 | ||
1da177e4 | 870 | /* |
c7909509 | 871 | * Free a buffer as defined by the above mapping. |
1da177e4 | 872 | */ |
dd37e940 | 873 | static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 874 | dma_addr_t handle, unsigned long attrs, |
dd37e940 | 875 | bool is_coherent) |
1da177e4 | 876 | { |
c7909509 | 877 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
19e6e5e5 | 878 | struct arm_dma_buffer *buf; |
b4268676 RV |
879 | struct arm_dma_free_args args = { |
880 | .dev = dev, | |
881 | .size = PAGE_ALIGN(size), | |
882 | .cpu_addr = cpu_addr, | |
883 | .page = page, | |
00085f1e | 884 | .want_vaddr = ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0), |
b4268676 | 885 | }; |
19e6e5e5 RV |
886 | |
887 | buf = arm_dma_buffer_find(cpu_addr); | |
888 | if (WARN(!buf, "Freeing invalid buffer %p\n", cpu_addr)) | |
889 | return; | |
5edf71ae | 890 | |
b4268676 | 891 | buf->allocator->free(&args); |
19e6e5e5 | 892 | kfree(buf); |
1da177e4 | 893 | } |
afd1a321 | 894 | |
dd37e940 | 895 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 896 | dma_addr_t handle, unsigned long attrs) |
dd37e940 RH |
897 | { |
898 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, false); | |
899 | } | |
900 | ||
901 | static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr, | |
00085f1e | 902 | dma_addr_t handle, unsigned long attrs) |
dd37e940 RH |
903 | { |
904 | __arm_dma_free(dev, size, cpu_addr, handle, attrs, true); | |
905 | } | |
906 | ||
916a008b RK |
907 | /* |
908 | * The whole dma_get_sgtable() idea is fundamentally unsafe - it seems | |
909 | * that the intention is to allow exporting memory allocated via the | |
910 | * coherent DMA APIs through the dma_buf API, which only accepts a | |
911 | * scattertable. This presents a couple of problems: | |
912 | * 1. Not all memory allocated via the coherent DMA APIs is backed by | |
913 | * a struct page | |
914 | * 2. Passing coherent DMA memory into the streaming APIs is not allowed | |
915 | * as we will try to flush the memory through a different alias to that | |
916 | * actually being used (and the flushes are redundant.) | |
917 | */ | |
dc2832e1 MS |
918 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
919 | void *cpu_addr, dma_addr_t handle, size_t size, | |
00085f1e | 920 | unsigned long attrs) |
dc2832e1 | 921 | { |
916a008b RK |
922 | unsigned long pfn = dma_to_pfn(dev, handle); |
923 | struct page *page; | |
dc2832e1 MS |
924 | int ret; |
925 | ||
916a008b RK |
926 | /* If the PFN is not valid, we do not have a struct page */ |
927 | if (!pfn_valid(pfn)) | |
928 | return -ENXIO; | |
929 | ||
930 | page = pfn_to_page(pfn); | |
931 | ||
dc2832e1 MS |
932 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); |
933 | if (unlikely(ret)) | |
934 | return ret; | |
935 | ||
936 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
937 | return 0; | |
938 | } | |
939 | ||
4ea0d737 | 940 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
941 | size_t size, enum dma_data_direction dir, |
942 | void (*op)(const void *, size_t, int)) | |
43377453 | 943 | { |
15653371 RK |
944 | unsigned long pfn; |
945 | size_t left = size; | |
946 | ||
947 | pfn = page_to_pfn(page) + offset / PAGE_SIZE; | |
948 | offset %= PAGE_SIZE; | |
949 | ||
43377453 NP |
950 | /* |
951 | * A single sg entry may refer to multiple physically contiguous | |
952 | * pages. But we still need to process highmem pages individually. | |
953 | * If highmem is not configured then the bulk of this loop gets | |
954 | * optimized out. | |
955 | */ | |
43377453 NP |
956 | do { |
957 | size_t len = left; | |
93f1d629 RK |
958 | void *vaddr; |
959 | ||
15653371 RK |
960 | page = pfn_to_page(pfn); |
961 | ||
93f1d629 | 962 | if (PageHighMem(page)) { |
15653371 | 963 | if (len + offset > PAGE_SIZE) |
93f1d629 | 964 | len = PAGE_SIZE - offset; |
dd0f67f4 JK |
965 | |
966 | if (cache_is_vipt_nonaliasing()) { | |
39af22a7 | 967 | vaddr = kmap_atomic(page); |
7e5a69e8 | 968 | op(vaddr + offset, len, dir); |
39af22a7 | 969 | kunmap_atomic(vaddr); |
dd0f67f4 JK |
970 | } else { |
971 | vaddr = kmap_high_get(page); | |
972 | if (vaddr) { | |
973 | op(vaddr + offset, len, dir); | |
974 | kunmap_high(page); | |
975 | } | |
43377453 | 976 | } |
93f1d629 RK |
977 | } else { |
978 | vaddr = page_address(page) + offset; | |
a9c9147e | 979 | op(vaddr, len, dir); |
43377453 | 980 | } |
43377453 | 981 | offset = 0; |
15653371 | 982 | pfn++; |
43377453 NP |
983 | left -= len; |
984 | } while (left); | |
985 | } | |
4ea0d737 | 986 | |
51fde349 MS |
987 | /* |
988 | * Make an area consistent for devices. | |
989 | * Note: Drivers should NOT use this function directly, as it will break | |
990 | * platforms with CONFIG_DMABOUNCE. | |
991 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
992 | */ | |
993 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
994 | size_t size, enum dma_data_direction dir) |
995 | { | |
2161c248 | 996 | phys_addr_t paddr; |
65af191a | 997 | |
a9c9147e | 998 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
999 | |
1000 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
1001 | if (dir == DMA_FROM_DEVICE) { |
1002 | outer_inv_range(paddr, paddr + size); | |
1003 | } else { | |
1004 | outer_clean_range(paddr, paddr + size); | |
1005 | } | |
1006 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 1007 | } |
4ea0d737 | 1008 | |
51fde349 | 1009 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
1010 | size_t size, enum dma_data_direction dir) |
1011 | { | |
2161c248 | 1012 | phys_addr_t paddr = page_to_phys(page) + off; |
2ffe2da3 RK |
1013 | |
1014 | /* FIXME: non-speculating: not required */ | |
deace4a6 RK |
1015 | /* in any case, don't bother invalidating if DMA to device */ |
1016 | if (dir != DMA_TO_DEVICE) { | |
2ffe2da3 RK |
1017 | outer_inv_range(paddr, paddr + size); |
1018 | ||
deace4a6 RK |
1019 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
1020 | } | |
c0177800 CM |
1021 | |
1022 | /* | |
b2a234ed | 1023 | * Mark the D-cache clean for these pages to avoid extra flushing. |
c0177800 | 1024 | */ |
b2a234ed ML |
1025 | if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) { |
1026 | unsigned long pfn; | |
1027 | size_t left = size; | |
1028 | ||
1029 | pfn = page_to_pfn(page) + off / PAGE_SIZE; | |
1030 | off %= PAGE_SIZE; | |
1031 | if (off) { | |
1032 | pfn++; | |
1033 | left -= PAGE_SIZE - off; | |
1034 | } | |
1035 | while (left >= PAGE_SIZE) { | |
1036 | page = pfn_to_page(pfn++); | |
1037 | set_bit(PG_dcache_clean, &page->flags); | |
1038 | left -= PAGE_SIZE; | |
1039 | } | |
1040 | } | |
4ea0d737 | 1041 | } |
43377453 | 1042 | |
afd1a321 | 1043 | /** |
2a550e73 | 1044 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
1045 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1046 | * @sg: list of buffers | |
1047 | * @nents: number of buffers to map | |
1048 | * @dir: DMA transfer direction | |
1049 | * | |
1050 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1051 | * This is the scatter-gather version of the dma_map_single interface. | |
1052 | * Here the scatter gather list elements are each tagged with the | |
1053 | * appropriate dma address and length. They are obtained via | |
1054 | * sg_dma_{address,length}. | |
1055 | * | |
1056 | * Device ownership issues as mentioned for dma_map_single are the same | |
1057 | * here. | |
1058 | */ | |
2dc6a016 | 1059 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
00085f1e | 1060 | enum dma_data_direction dir, unsigned long attrs) |
afd1a321 | 1061 | { |
5299709d | 1062 | const struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 1063 | struct scatterlist *s; |
01135d92 | 1064 | int i, j; |
afd1a321 RK |
1065 | |
1066 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
1067 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
1068 | s->dma_length = s->length; | |
1069 | #endif | |
2a550e73 MS |
1070 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
1071 | s->length, dir, attrs); | |
01135d92 RK |
1072 | if (dma_mapping_error(dev, s->dma_address)) |
1073 | goto bad_mapping; | |
afd1a321 | 1074 | } |
afd1a321 | 1075 | return nents; |
01135d92 RK |
1076 | |
1077 | bad_mapping: | |
1078 | for_each_sg(sg, s, i, j) | |
2a550e73 | 1079 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 1080 | return 0; |
afd1a321 | 1081 | } |
afd1a321 RK |
1082 | |
1083 | /** | |
2a550e73 | 1084 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
1085 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1086 | * @sg: list of buffers | |
0adfca6f | 1087 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
1088 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
1089 | * | |
1090 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1091 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1092 | */ | |
2dc6a016 | 1093 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
00085f1e | 1094 | enum dma_data_direction dir, unsigned long attrs) |
afd1a321 | 1095 | { |
5299709d | 1096 | const struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 1097 | struct scatterlist *s; |
01135d92 | 1098 | |
01135d92 | 1099 | int i; |
24056f52 | 1100 | |
01135d92 | 1101 | for_each_sg(sg, s, nents, i) |
2a550e73 | 1102 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 1103 | } |
afd1a321 RK |
1104 | |
1105 | /** | |
2a550e73 | 1106 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
1107 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1108 | * @sg: list of buffers | |
1109 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1110 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1111 | */ | |
2dc6a016 | 1112 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1113 | int nents, enum dma_data_direction dir) |
1114 | { | |
5299709d | 1115 | const struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1116 | struct scatterlist *s; |
1117 | int i; | |
1118 | ||
2a550e73 MS |
1119 | for_each_sg(sg, s, nents, i) |
1120 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
1121 | dir); | |
afd1a321 | 1122 | } |
afd1a321 RK |
1123 | |
1124 | /** | |
2a550e73 | 1125 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
1126 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
1127 | * @sg: list of buffers | |
1128 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1129 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1130 | */ | |
2dc6a016 | 1131 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
1132 | int nents, enum dma_data_direction dir) |
1133 | { | |
5299709d | 1134 | const struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
1135 | struct scatterlist *s; |
1136 | int i; | |
1137 | ||
2a550e73 MS |
1138 | for_each_sg(sg, s, nents, i) |
1139 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
1140 | dir); | |
afd1a321 | 1141 | } |
24056f52 | 1142 | |
022ae537 RK |
1143 | /* |
1144 | * Return whether the given device DMA address mask can be supported | |
1145 | * properly. For example, if your device can only drive the low 24-bits | |
1146 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
1147 | * to this function. | |
1148 | */ | |
418a7a7e | 1149 | int arm_dma_supported(struct device *dev, u64 mask) |
022ae537 | 1150 | { |
9f28cde0 | 1151 | return __dma_supported(dev, mask, false); |
022ae537 | 1152 | } |
022ae537 | 1153 | |
24056f52 RK |
1154 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
1155 | ||
1156 | static int __init dma_debug_do_init(void) | |
1157 | { | |
1158 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
1159 | return 0; | |
1160 | } | |
256ff1cf | 1161 | core_initcall(dma_debug_do_init); |
4ce63fcd MS |
1162 | |
1163 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
1164 | ||
7d2822df S |
1165 | static int __dma_info_to_prot(enum dma_data_direction dir, unsigned long attrs) |
1166 | { | |
1167 | int prot = 0; | |
1168 | ||
1169 | if (attrs & DMA_ATTR_PRIVILEGED) | |
1170 | prot |= IOMMU_PRIV; | |
1171 | ||
1172 | switch (dir) { | |
1173 | case DMA_BIDIRECTIONAL: | |
1174 | return prot | IOMMU_READ | IOMMU_WRITE; | |
1175 | case DMA_TO_DEVICE: | |
1176 | return prot | IOMMU_READ; | |
1177 | case DMA_FROM_DEVICE: | |
1178 | return prot | IOMMU_WRITE; | |
1179 | default: | |
1180 | return prot; | |
1181 | } | |
1182 | } | |
1183 | ||
4ce63fcd MS |
1184 | /* IOMMU */ |
1185 | ||
4d852ef8 AH |
1186 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping); |
1187 | ||
4ce63fcd MS |
1188 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, |
1189 | size_t size) | |
1190 | { | |
1191 | unsigned int order = get_order(size); | |
1192 | unsigned int align = 0; | |
1193 | unsigned int count, start; | |
006f841d | 1194 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1195 | unsigned long flags; |
4d852ef8 AH |
1196 | dma_addr_t iova; |
1197 | int i; | |
4ce63fcd | 1198 | |
60460abf SWK |
1199 | if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT) |
1200 | order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT; | |
1201 | ||
68efd7d2 MS |
1202 | count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1203 | align = (1 << order) - 1; | |
4ce63fcd MS |
1204 | |
1205 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 AH |
1206 | for (i = 0; i < mapping->nr_bitmaps; i++) { |
1207 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1208 | mapping->bits, 0, count, align); | |
1209 | ||
1210 | if (start > mapping->bits) | |
1211 | continue; | |
1212 | ||
1213 | bitmap_set(mapping->bitmaps[i], start, count); | |
1214 | break; | |
4ce63fcd MS |
1215 | } |
1216 | ||
4d852ef8 AH |
1217 | /* |
1218 | * No unused range found. Try to extend the existing mapping | |
1219 | * and perform a second attempt to reserve an IO virtual | |
1220 | * address range of size bytes. | |
1221 | */ | |
1222 | if (i == mapping->nr_bitmaps) { | |
1223 | if (extend_iommu_mapping(mapping)) { | |
1224 | spin_unlock_irqrestore(&mapping->lock, flags); | |
9eef8b8c | 1225 | return ARM_MAPPING_ERROR; |
4d852ef8 AH |
1226 | } |
1227 | ||
1228 | start = bitmap_find_next_zero_area(mapping->bitmaps[i], | |
1229 | mapping->bits, 0, count, align); | |
1230 | ||
1231 | if (start > mapping->bits) { | |
1232 | spin_unlock_irqrestore(&mapping->lock, flags); | |
9eef8b8c | 1233 | return ARM_MAPPING_ERROR; |
4d852ef8 AH |
1234 | } |
1235 | ||
1236 | bitmap_set(mapping->bitmaps[i], start, count); | |
1237 | } | |
4ce63fcd MS |
1238 | spin_unlock_irqrestore(&mapping->lock, flags); |
1239 | ||
006f841d | 1240 | iova = mapping->base + (mapping_size * i); |
68efd7d2 | 1241 | iova += start << PAGE_SHIFT; |
4d852ef8 AH |
1242 | |
1243 | return iova; | |
4ce63fcd MS |
1244 | } |
1245 | ||
1246 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
1247 | dma_addr_t addr, size_t size) | |
1248 | { | |
4d852ef8 | 1249 | unsigned int start, count; |
006f841d | 1250 | size_t mapping_size = mapping->bits << PAGE_SHIFT; |
4ce63fcd | 1251 | unsigned long flags; |
4d852ef8 AH |
1252 | dma_addr_t bitmap_base; |
1253 | u32 bitmap_index; | |
1254 | ||
1255 | if (!size) | |
1256 | return; | |
1257 | ||
006f841d | 1258 | bitmap_index = (u32) (addr - mapping->base) / (u32) mapping_size; |
4d852ef8 AH |
1259 | BUG_ON(addr < mapping->base || bitmap_index > mapping->extensions); |
1260 | ||
006f841d | 1261 | bitmap_base = mapping->base + mapping_size * bitmap_index; |
4d852ef8 | 1262 | |
68efd7d2 | 1263 | start = (addr - bitmap_base) >> PAGE_SHIFT; |
4d852ef8 | 1264 | |
006f841d | 1265 | if (addr + size > bitmap_base + mapping_size) { |
4d852ef8 AH |
1266 | /* |
1267 | * The address range to be freed reaches into the iova | |
1268 | * range of the next bitmap. This should not happen as | |
1269 | * we don't allow this in __alloc_iova (at the | |
1270 | * moment). | |
1271 | */ | |
1272 | BUG(); | |
1273 | } else | |
68efd7d2 | 1274 | count = size >> PAGE_SHIFT; |
4ce63fcd MS |
1275 | |
1276 | spin_lock_irqsave(&mapping->lock, flags); | |
4d852ef8 | 1277 | bitmap_clear(mapping->bitmaps[bitmap_index], start, count); |
4ce63fcd MS |
1278 | spin_unlock_irqrestore(&mapping->lock, flags); |
1279 | } | |
1280 | ||
33298ef6 DA |
1281 | /* We'll try 2M, 1M, 64K, and finally 4K; array must end with 0! */ |
1282 | static const int iommu_order_array[] = { 9, 8, 4, 0 }; | |
1283 | ||
549a17e4 | 1284 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, |
00085f1e | 1285 | gfp_t gfp, unsigned long attrs, |
f1270896 | 1286 | int coherent_flag) |
4ce63fcd MS |
1287 | { |
1288 | struct page **pages; | |
1289 | int count = size >> PAGE_SHIFT; | |
1290 | int array_size = count * sizeof(struct page *); | |
1291 | int i = 0; | |
33298ef6 | 1292 | int order_idx = 0; |
4ce63fcd MS |
1293 | |
1294 | if (array_size <= PAGE_SIZE) | |
23be7fda | 1295 | pages = kzalloc(array_size, GFP_KERNEL); |
4ce63fcd MS |
1296 | else |
1297 | pages = vzalloc(array_size); | |
1298 | if (!pages) | |
1299 | return NULL; | |
1300 | ||
00085f1e | 1301 | if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) |
549a17e4 MS |
1302 | { |
1303 | unsigned long order = get_order(size); | |
1304 | struct page *page; | |
1305 | ||
712c604d | 1306 | page = dma_alloc_from_contiguous(dev, count, order, gfp); |
549a17e4 MS |
1307 | if (!page) |
1308 | goto error; | |
1309 | ||
f1270896 | 1310 | __dma_clear_buffer(page, size, coherent_flag); |
549a17e4 MS |
1311 | |
1312 | for (i = 0; i < count; i++) | |
1313 | pages[i] = page + i; | |
1314 | ||
1315 | return pages; | |
1316 | } | |
1317 | ||
14d3ae2e | 1318 | /* Go straight to 4K chunks if caller says it's OK. */ |
00085f1e | 1319 | if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES) |
14d3ae2e DA |
1320 | order_idx = ARRAY_SIZE(iommu_order_array) - 1; |
1321 | ||
f8669bef MS |
1322 | /* |
1323 | * IOMMU can map any pages, so himem can also be used here | |
1324 | */ | |
1325 | gfp |= __GFP_NOWARN | __GFP_HIGHMEM; | |
1326 | ||
4ce63fcd | 1327 | while (count) { |
49f28aa6 TF |
1328 | int j, order; |
1329 | ||
33298ef6 DA |
1330 | order = iommu_order_array[order_idx]; |
1331 | ||
1332 | /* Drop down when we get small */ | |
1333 | if (__fls(count) < order) { | |
1334 | order_idx++; | |
1335 | continue; | |
49f28aa6 | 1336 | } |
4ce63fcd | 1337 | |
33298ef6 DA |
1338 | if (order) { |
1339 | /* See if it's easy to allocate a high-order chunk */ | |
1340 | pages[i] = alloc_pages(gfp | __GFP_NORETRY, order); | |
1341 | ||
1342 | /* Go down a notch at first sign of pressure */ | |
1343 | if (!pages[i]) { | |
1344 | order_idx++; | |
1345 | continue; | |
1346 | } | |
1347 | } else { | |
49f28aa6 TF |
1348 | pages[i] = alloc_pages(gfp, 0); |
1349 | if (!pages[i]) | |
1350 | goto error; | |
1351 | } | |
4ce63fcd | 1352 | |
5a796eeb | 1353 | if (order) { |
4ce63fcd | 1354 | split_page(pages[i], order); |
5a796eeb HD |
1355 | j = 1 << order; |
1356 | while (--j) | |
1357 | pages[i + j] = pages[i] + j; | |
1358 | } | |
4ce63fcd | 1359 | |
f1270896 | 1360 | __dma_clear_buffer(pages[i], PAGE_SIZE << order, coherent_flag); |
4ce63fcd MS |
1361 | i += 1 << order; |
1362 | count -= 1 << order; | |
1363 | } | |
1364 | ||
1365 | return pages; | |
1366 | error: | |
9fa8af91 | 1367 | while (i--) |
4ce63fcd MS |
1368 | if (pages[i]) |
1369 | __free_pages(pages[i], 0); | |
1d5cfdb0 | 1370 | kvfree(pages); |
4ce63fcd MS |
1371 | return NULL; |
1372 | } | |
1373 | ||
549a17e4 | 1374 | static int __iommu_free_buffer(struct device *dev, struct page **pages, |
00085f1e | 1375 | size_t size, unsigned long attrs) |
4ce63fcd MS |
1376 | { |
1377 | int count = size >> PAGE_SHIFT; | |
4ce63fcd | 1378 | int i; |
549a17e4 | 1379 | |
00085f1e | 1380 | if (attrs & DMA_ATTR_FORCE_CONTIGUOUS) { |
549a17e4 MS |
1381 | dma_release_from_contiguous(dev, pages[0], count); |
1382 | } else { | |
1383 | for (i = 0; i < count; i++) | |
1384 | if (pages[i]) | |
1385 | __free_pages(pages[i], 0); | |
1386 | } | |
1387 | ||
1d5cfdb0 | 1388 | kvfree(pages); |
4ce63fcd MS |
1389 | return 0; |
1390 | } | |
1391 | ||
1392 | /* | |
1393 | * Create a CPU mapping for a specified pages | |
1394 | */ | |
1395 | static void * | |
e9da6e99 MS |
1396 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1397 | const void *caller) | |
4ce63fcd | 1398 | { |
513510dd LA |
1399 | return dma_common_pages_remap(pages, size, |
1400 | VM_ARM_DMA_CONSISTENT | VM_USERMAP, prot, caller); | |
4ce63fcd MS |
1401 | } |
1402 | ||
1403 | /* | |
1404 | * Create a mapping in device IO address space for specified pages | |
1405 | */ | |
1406 | static dma_addr_t | |
7d2822df S |
1407 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size, |
1408 | unsigned long attrs) | |
4ce63fcd | 1409 | { |
89cfdb19 | 1410 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1411 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1412 | dma_addr_t dma_addr, iova; | |
90cde558 | 1413 | int i; |
4ce63fcd MS |
1414 | |
1415 | dma_addr = __alloc_iova(mapping, size); | |
9eef8b8c | 1416 | if (dma_addr == ARM_MAPPING_ERROR) |
4ce63fcd MS |
1417 | return dma_addr; |
1418 | ||
1419 | iova = dma_addr; | |
1420 | for (i = 0; i < count; ) { | |
90cde558 AP |
1421 | int ret; |
1422 | ||
4ce63fcd MS |
1423 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; |
1424 | phys_addr_t phys = page_to_phys(pages[i]); | |
1425 | unsigned int len, j; | |
1426 | ||
1427 | for (j = i + 1; j < count; j++, next_pfn++) | |
1428 | if (page_to_pfn(pages[j]) != next_pfn) | |
1429 | break; | |
1430 | ||
1431 | len = (j - i) << PAGE_SHIFT; | |
c9b24996 | 1432 | ret = iommu_map(mapping->domain, iova, phys, len, |
7d2822df | 1433 | __dma_info_to_prot(DMA_BIDIRECTIONAL, attrs)); |
4ce63fcd MS |
1434 | if (ret < 0) |
1435 | goto fail; | |
1436 | iova += len; | |
1437 | i = j; | |
1438 | } | |
1439 | return dma_addr; | |
1440 | fail: | |
1441 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1442 | __free_iova(mapping, dma_addr, size); | |
9eef8b8c | 1443 | return ARM_MAPPING_ERROR; |
4ce63fcd MS |
1444 | } |
1445 | ||
1446 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1447 | { | |
89cfdb19 | 1448 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1449 | |
1450 | /* | |
1451 | * add optional in-page offset from iova to size and align | |
1452 | * result to page size | |
1453 | */ | |
1454 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1455 | iova &= PAGE_MASK; | |
1456 | ||
1457 | iommu_unmap(mapping->domain, iova, size); | |
1458 | __free_iova(mapping, iova, size); | |
1459 | return 0; | |
1460 | } | |
1461 | ||
665bad7b HD |
1462 | static struct page **__atomic_get_pages(void *addr) |
1463 | { | |
36d0fd21 LA |
1464 | struct page *page; |
1465 | phys_addr_t phys; | |
1466 | ||
1467 | phys = gen_pool_virt_to_phys(atomic_pool, (unsigned long)addr); | |
1468 | page = phys_to_page(phys); | |
665bad7b | 1469 | |
36d0fd21 | 1470 | return (struct page **)page; |
665bad7b HD |
1471 | } |
1472 | ||
00085f1e | 1473 | static struct page **__iommu_get_pages(void *cpu_addr, unsigned long attrs) |
e9da6e99 MS |
1474 | { |
1475 | struct vm_struct *area; | |
1476 | ||
665bad7b HD |
1477 | if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) |
1478 | return __atomic_get_pages(cpu_addr); | |
1479 | ||
00085f1e | 1480 | if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) |
955c757e MS |
1481 | return cpu_addr; |
1482 | ||
e9da6e99 MS |
1483 | area = find_vm_area(cpu_addr); |
1484 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1485 | return area->pages; | |
1486 | return NULL; | |
1487 | } | |
1488 | ||
56506822 | 1489 | static void *__iommu_alloc_simple(struct device *dev, size_t size, gfp_t gfp, |
7d2822df S |
1490 | dma_addr_t *handle, int coherent_flag, |
1491 | unsigned long attrs) | |
479ed93a HD |
1492 | { |
1493 | struct page *page; | |
1494 | void *addr; | |
1495 | ||
56506822 GC |
1496 | if (coherent_flag == COHERENT) |
1497 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
1498 | else | |
1499 | addr = __alloc_from_pool(size, &page); | |
479ed93a HD |
1500 | if (!addr) |
1501 | return NULL; | |
1502 | ||
7d2822df | 1503 | *handle = __iommu_create_mapping(dev, &page, size, attrs); |
9eef8b8c | 1504 | if (*handle == ARM_MAPPING_ERROR) |
479ed93a HD |
1505 | goto err_mapping; |
1506 | ||
1507 | return addr; | |
1508 | ||
1509 | err_mapping: | |
1510 | __free_from_pool(addr, size); | |
1511 | return NULL; | |
1512 | } | |
1513 | ||
d5898291 | 1514 | static void __iommu_free_atomic(struct device *dev, void *cpu_addr, |
56506822 | 1515 | dma_addr_t handle, size_t size, int coherent_flag) |
479ed93a HD |
1516 | { |
1517 | __iommu_remove_mapping(dev, handle, size); | |
56506822 GC |
1518 | if (coherent_flag == COHERENT) |
1519 | __dma_free_buffer(virt_to_page(cpu_addr), size); | |
1520 | else | |
1521 | __free_from_pool(cpu_addr, size); | |
479ed93a HD |
1522 | } |
1523 | ||
56506822 | 1524 | static void *__arm_iommu_alloc_attrs(struct device *dev, size_t size, |
00085f1e | 1525 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs, |
56506822 | 1526 | int coherent_flag) |
4ce63fcd | 1527 | { |
71b55663 | 1528 | pgprot_t prot = __get_dma_pgprot(attrs, PAGE_KERNEL); |
4ce63fcd MS |
1529 | struct page **pages; |
1530 | void *addr = NULL; | |
1531 | ||
9eef8b8c | 1532 | *handle = ARM_MAPPING_ERROR; |
4ce63fcd MS |
1533 | size = PAGE_ALIGN(size); |
1534 | ||
56506822 GC |
1535 | if (coherent_flag == COHERENT || !gfpflags_allow_blocking(gfp)) |
1536 | return __iommu_alloc_simple(dev, size, gfp, handle, | |
7d2822df | 1537 | coherent_flag, attrs); |
479ed93a | 1538 | |
5b91a98c RZ |
1539 | /* |
1540 | * Following is a work-around (a.k.a. hack) to prevent pages | |
1541 | * with __GFP_COMP being passed to split_page() which cannot | |
1542 | * handle them. The real problem is that this flag probably | |
1543 | * should be 0 on ARM as it is not supported on this | |
1544 | * platform; see CONFIG_HUGETLBFS. | |
1545 | */ | |
1546 | gfp &= ~(__GFP_COMP); | |
1547 | ||
56506822 | 1548 | pages = __iommu_alloc_buffer(dev, size, gfp, attrs, coherent_flag); |
4ce63fcd MS |
1549 | if (!pages) |
1550 | return NULL; | |
1551 | ||
7d2822df | 1552 | *handle = __iommu_create_mapping(dev, pages, size, attrs); |
9eef8b8c | 1553 | if (*handle == ARM_MAPPING_ERROR) |
4ce63fcd MS |
1554 | goto err_buffer; |
1555 | ||
00085f1e | 1556 | if (attrs & DMA_ATTR_NO_KERNEL_MAPPING) |
955c757e MS |
1557 | return pages; |
1558 | ||
e9da6e99 MS |
1559 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1560 | __builtin_return_address(0)); | |
4ce63fcd MS |
1561 | if (!addr) |
1562 | goto err_mapping; | |
1563 | ||
1564 | return addr; | |
1565 | ||
1566 | err_mapping: | |
1567 | __iommu_remove_mapping(dev, *handle, size); | |
1568 | err_buffer: | |
549a17e4 | 1569 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1570 | return NULL; |
1571 | } | |
1572 | ||
56506822 | 1573 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
00085f1e | 1574 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs) |
56506822 GC |
1575 | { |
1576 | return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, NORMAL); | |
1577 | } | |
1578 | ||
1579 | static void *arm_coherent_iommu_alloc_attrs(struct device *dev, size_t size, | |
00085f1e | 1580 | dma_addr_t *handle, gfp_t gfp, unsigned long attrs) |
56506822 GC |
1581 | { |
1582 | return __arm_iommu_alloc_attrs(dev, size, handle, gfp, attrs, COHERENT); | |
1583 | } | |
1584 | ||
1585 | static int __arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
4ce63fcd | 1586 | void *cpu_addr, dma_addr_t dma_addr, size_t size, |
00085f1e | 1587 | unsigned long attrs) |
4ce63fcd | 1588 | { |
e9da6e99 MS |
1589 | unsigned long uaddr = vma->vm_start; |
1590 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1591 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
371f0f08 MS |
1592 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1593 | unsigned long off = vma->vm_pgoff; | |
4ce63fcd | 1594 | |
e9da6e99 MS |
1595 | if (!pages) |
1596 | return -ENXIO; | |
4ce63fcd | 1597 | |
371f0f08 MS |
1598 | if (off >= nr_pages || (usize >> PAGE_SHIFT) > nr_pages - off) |
1599 | return -ENXIO; | |
1600 | ||
7e312103 MS |
1601 | pages += off; |
1602 | ||
e9da6e99 MS |
1603 | do { |
1604 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1605 | if (ret) { | |
1606 | pr_err("Remapping memory failed: %d\n", ret); | |
1607 | return ret; | |
1608 | } | |
1609 | uaddr += PAGE_SIZE; | |
1610 | usize -= PAGE_SIZE; | |
1611 | } while (usize > 0); | |
4ce63fcd | 1612 | |
4ce63fcd MS |
1613 | return 0; |
1614 | } | |
56506822 GC |
1615 | static int arm_iommu_mmap_attrs(struct device *dev, |
1616 | struct vm_area_struct *vma, void *cpu_addr, | |
00085f1e | 1617 | dma_addr_t dma_addr, size_t size, unsigned long attrs) |
56506822 GC |
1618 | { |
1619 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
1620 | ||
1621 | return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs); | |
1622 | } | |
1623 | ||
1624 | static int arm_coherent_iommu_mmap_attrs(struct device *dev, | |
1625 | struct vm_area_struct *vma, void *cpu_addr, | |
00085f1e | 1626 | dma_addr_t dma_addr, size_t size, unsigned long attrs) |
56506822 GC |
1627 | { |
1628 | return __arm_iommu_mmap_attrs(dev, vma, cpu_addr, dma_addr, size, attrs); | |
1629 | } | |
4ce63fcd MS |
1630 | |
1631 | /* | |
1632 | * free a page as defined by the above mapping. | |
1633 | * Must not be called with IRQs disabled. | |
1634 | */ | |
56506822 | 1635 | void __arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, |
00085f1e | 1636 | dma_addr_t handle, unsigned long attrs, int coherent_flag) |
4ce63fcd | 1637 | { |
836bfa0d | 1638 | struct page **pages; |
4ce63fcd MS |
1639 | size = PAGE_ALIGN(size); |
1640 | ||
56506822 GC |
1641 | if (coherent_flag == COHERENT || __in_atomic_pool(cpu_addr, size)) { |
1642 | __iommu_free_atomic(dev, cpu_addr, handle, size, coherent_flag); | |
e9da6e99 | 1643 | return; |
4ce63fcd | 1644 | } |
e9da6e99 | 1645 | |
836bfa0d YC |
1646 | pages = __iommu_get_pages(cpu_addr, attrs); |
1647 | if (!pages) { | |
1648 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
479ed93a HD |
1649 | return; |
1650 | } | |
1651 | ||
00085f1e | 1652 | if ((attrs & DMA_ATTR_NO_KERNEL_MAPPING) == 0) { |
513510dd LA |
1653 | dma_common_free_remap(cpu_addr, size, |
1654 | VM_ARM_DMA_CONSISTENT | VM_USERMAP); | |
955c757e | 1655 | } |
e9da6e99 MS |
1656 | |
1657 | __iommu_remove_mapping(dev, handle, size); | |
549a17e4 | 1658 | __iommu_free_buffer(dev, pages, size, attrs); |
4ce63fcd MS |
1659 | } |
1660 | ||
56506822 | 1661 | void arm_iommu_free_attrs(struct device *dev, size_t size, |
00085f1e | 1662 | void *cpu_addr, dma_addr_t handle, unsigned long attrs) |
56506822 GC |
1663 | { |
1664 | __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, NORMAL); | |
1665 | } | |
1666 | ||
1667 | void arm_coherent_iommu_free_attrs(struct device *dev, size_t size, | |
00085f1e | 1668 | void *cpu_addr, dma_addr_t handle, unsigned long attrs) |
56506822 GC |
1669 | { |
1670 | __arm_iommu_free_attrs(dev, size, cpu_addr, handle, attrs, COHERENT); | |
1671 | } | |
1672 | ||
dc2832e1 MS |
1673 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1674 | void *cpu_addr, dma_addr_t dma_addr, | |
00085f1e | 1675 | size_t size, unsigned long attrs) |
dc2832e1 MS |
1676 | { |
1677 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1678 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1679 | ||
1680 | if (!pages) | |
1681 | return -ENXIO; | |
1682 | ||
1683 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1684 | GFP_KERNEL); | |
4ce63fcd MS |
1685 | } |
1686 | ||
1687 | /* | |
1688 | * Map a part of the scatter-gather list into contiguous io address space | |
1689 | */ | |
1690 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1691 | size_t size, dma_addr_t *handle, | |
00085f1e | 1692 | enum dma_data_direction dir, unsigned long attrs, |
0fa478df | 1693 | bool is_coherent) |
4ce63fcd | 1694 | { |
89cfdb19 | 1695 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1696 | dma_addr_t iova, iova_base; |
1697 | int ret = 0; | |
1698 | unsigned int count; | |
1699 | struct scatterlist *s; | |
c9b24996 | 1700 | int prot; |
4ce63fcd MS |
1701 | |
1702 | size = PAGE_ALIGN(size); | |
9eef8b8c | 1703 | *handle = ARM_MAPPING_ERROR; |
4ce63fcd MS |
1704 | |
1705 | iova_base = iova = __alloc_iova(mapping, size); | |
9eef8b8c | 1706 | if (iova == ARM_MAPPING_ERROR) |
4ce63fcd MS |
1707 | return -ENOMEM; |
1708 | ||
1709 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
3e6110fd | 1710 | phys_addr_t phys = page_to_phys(sg_page(s)); |
4ce63fcd MS |
1711 | unsigned int len = PAGE_ALIGN(s->offset + s->length); |
1712 | ||
00085f1e | 1713 | if (!is_coherent && (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
4ce63fcd MS |
1714 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1715 | ||
7d2822df | 1716 | prot = __dma_info_to_prot(dir, attrs); |
c9b24996 AH |
1717 | |
1718 | ret = iommu_map(mapping->domain, iova, phys, len, prot); | |
4ce63fcd MS |
1719 | if (ret < 0) |
1720 | goto fail; | |
1721 | count += len >> PAGE_SHIFT; | |
1722 | iova += len; | |
1723 | } | |
1724 | *handle = iova_base; | |
1725 | ||
1726 | return 0; | |
1727 | fail: | |
1728 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1729 | __free_iova(mapping, iova_base, size); | |
1730 | return ret; | |
1731 | } | |
1732 | ||
0fa478df | 1733 | static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
00085f1e | 1734 | enum dma_data_direction dir, unsigned long attrs, |
0fa478df | 1735 | bool is_coherent) |
4ce63fcd MS |
1736 | { |
1737 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1738 | int i, count = 0; | |
1739 | unsigned int offset = s->offset; | |
1740 | unsigned int size = s->offset + s->length; | |
1741 | unsigned int max = dma_get_max_seg_size(dev); | |
1742 | ||
1743 | for (i = 1; i < nents; i++) { | |
1744 | s = sg_next(s); | |
1745 | ||
9eef8b8c | 1746 | s->dma_address = ARM_MAPPING_ERROR; |
4ce63fcd MS |
1747 | s->dma_length = 0; |
1748 | ||
1749 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1750 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
0fa478df | 1751 | dir, attrs, is_coherent) < 0) |
4ce63fcd MS |
1752 | goto bad_mapping; |
1753 | ||
1754 | dma->dma_address += offset; | |
1755 | dma->dma_length = size - offset; | |
1756 | ||
1757 | size = offset = s->offset; | |
1758 | start = s; | |
1759 | dma = sg_next(dma); | |
1760 | count += 1; | |
1761 | } | |
1762 | size += s->length; | |
1763 | } | |
0fa478df RH |
1764 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs, |
1765 | is_coherent) < 0) | |
4ce63fcd MS |
1766 | goto bad_mapping; |
1767 | ||
1768 | dma->dma_address += offset; | |
1769 | dma->dma_length = size - offset; | |
1770 | ||
1771 | return count+1; | |
1772 | ||
1773 | bad_mapping: | |
1774 | for_each_sg(sg, s, count, i) | |
1775 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1776 | return 0; | |
1777 | } | |
1778 | ||
1779 | /** | |
0fa478df | 1780 | * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA |
4ce63fcd MS |
1781 | * @dev: valid struct device pointer |
1782 | * @sg: list of buffers | |
0fa478df RH |
1783 | * @nents: number of buffers to map |
1784 | * @dir: DMA transfer direction | |
4ce63fcd | 1785 | * |
0fa478df RH |
1786 | * Map a set of i/o coherent buffers described by scatterlist in streaming |
1787 | * mode for DMA. The scatter gather list elements are merged together (if | |
1788 | * possible) and tagged with the appropriate dma address and length. They are | |
1789 | * obtained via sg_dma_{address,length}. | |
4ce63fcd | 1790 | */ |
0fa478df | 1791 | int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg, |
00085f1e | 1792 | int nents, enum dma_data_direction dir, unsigned long attrs) |
0fa478df RH |
1793 | { |
1794 | return __iommu_map_sg(dev, sg, nents, dir, attrs, true); | |
1795 | } | |
1796 | ||
1797 | /** | |
1798 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1799 | * @dev: valid struct device pointer | |
1800 | * @sg: list of buffers | |
1801 | * @nents: number of buffers to map | |
1802 | * @dir: DMA transfer direction | |
1803 | * | |
1804 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1805 | * The scatter gather list elements are merged together (if possible) and | |
1806 | * tagged with the appropriate dma address and length. They are obtained via | |
1807 | * sg_dma_{address,length}. | |
1808 | */ | |
1809 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, | |
00085f1e | 1810 | int nents, enum dma_data_direction dir, unsigned long attrs) |
0fa478df RH |
1811 | { |
1812 | return __iommu_map_sg(dev, sg, nents, dir, attrs, false); | |
1813 | } | |
1814 | ||
1815 | static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
00085f1e KK |
1816 | int nents, enum dma_data_direction dir, |
1817 | unsigned long attrs, bool is_coherent) | |
4ce63fcd MS |
1818 | { |
1819 | struct scatterlist *s; | |
1820 | int i; | |
1821 | ||
1822 | for_each_sg(sg, s, nents, i) { | |
1823 | if (sg_dma_len(s)) | |
1824 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1825 | sg_dma_len(s)); | |
00085f1e | 1826 | if (!is_coherent && (attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
4ce63fcd MS |
1827 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1828 | s->length, dir); | |
1829 | } | |
1830 | } | |
1831 | ||
0fa478df RH |
1832 | /** |
1833 | * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1834 | * @dev: valid struct device pointer | |
1835 | * @sg: list of buffers | |
1836 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1837 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1838 | * | |
1839 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1840 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1841 | */ | |
1842 | void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, | |
00085f1e KK |
1843 | int nents, enum dma_data_direction dir, |
1844 | unsigned long attrs) | |
0fa478df RH |
1845 | { |
1846 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, true); | |
1847 | } | |
1848 | ||
1849 | /** | |
1850 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1851 | * @dev: valid struct device pointer | |
1852 | * @sg: list of buffers | |
1853 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1854 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1855 | * | |
1856 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1857 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1858 | */ | |
1859 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
00085f1e KK |
1860 | enum dma_data_direction dir, |
1861 | unsigned long attrs) | |
0fa478df RH |
1862 | { |
1863 | __iommu_unmap_sg(dev, sg, nents, dir, attrs, false); | |
1864 | } | |
1865 | ||
4ce63fcd MS |
1866 | /** |
1867 | * arm_iommu_sync_sg_for_cpu | |
1868 | * @dev: valid struct device pointer | |
1869 | * @sg: list of buffers | |
1870 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1871 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1872 | */ | |
1873 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1874 | int nents, enum dma_data_direction dir) | |
1875 | { | |
1876 | struct scatterlist *s; | |
1877 | int i; | |
1878 | ||
1879 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1880 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1881 | |
1882 | } | |
1883 | ||
1884 | /** | |
1885 | * arm_iommu_sync_sg_for_device | |
1886 | * @dev: valid struct device pointer | |
1887 | * @sg: list of buffers | |
1888 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1889 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1890 | */ | |
1891 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1892 | int nents, enum dma_data_direction dir) | |
1893 | { | |
1894 | struct scatterlist *s; | |
1895 | int i; | |
1896 | ||
1897 | for_each_sg(sg, s, nents, i) | |
0fa478df | 1898 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
4ce63fcd MS |
1899 | } |
1900 | ||
1901 | ||
1902 | /** | |
0fa478df | 1903 | * arm_coherent_iommu_map_page |
4ce63fcd MS |
1904 | * @dev: valid struct device pointer |
1905 | * @page: page that buffer resides in | |
1906 | * @offset: offset into page for start of buffer | |
1907 | * @size: size of buffer to map | |
1908 | * @dir: DMA transfer direction | |
1909 | * | |
0fa478df | 1910 | * Coherent IOMMU aware version of arm_dma_map_page() |
4ce63fcd | 1911 | */ |
0fa478df | 1912 | static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page, |
4ce63fcd | 1913 | unsigned long offset, size_t size, enum dma_data_direction dir, |
00085f1e | 1914 | unsigned long attrs) |
4ce63fcd | 1915 | { |
89cfdb19 | 1916 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd | 1917 | dma_addr_t dma_addr; |
13987d68 | 1918 | int ret, prot, len = PAGE_ALIGN(size + offset); |
4ce63fcd | 1919 | |
4ce63fcd | 1920 | dma_addr = __alloc_iova(mapping, len); |
9eef8b8c | 1921 | if (dma_addr == ARM_MAPPING_ERROR) |
4ce63fcd MS |
1922 | return dma_addr; |
1923 | ||
7d2822df | 1924 | prot = __dma_info_to_prot(dir, attrs); |
13987d68 WD |
1925 | |
1926 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot); | |
4ce63fcd MS |
1927 | if (ret < 0) |
1928 | goto fail; | |
1929 | ||
1930 | return dma_addr + offset; | |
1931 | fail: | |
1932 | __free_iova(mapping, dma_addr, len); | |
9eef8b8c | 1933 | return ARM_MAPPING_ERROR; |
4ce63fcd MS |
1934 | } |
1935 | ||
0fa478df RH |
1936 | /** |
1937 | * arm_iommu_map_page | |
1938 | * @dev: valid struct device pointer | |
1939 | * @page: page that buffer resides in | |
1940 | * @offset: offset into page for start of buffer | |
1941 | * @size: size of buffer to map | |
1942 | * @dir: DMA transfer direction | |
1943 | * | |
1944 | * IOMMU aware version of arm_dma_map_page() | |
1945 | */ | |
1946 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1947 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
00085f1e | 1948 | unsigned long attrs) |
0fa478df | 1949 | { |
00085f1e | 1950 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
0fa478df RH |
1951 | __dma_page_cpu_to_dev(page, offset, size, dir); |
1952 | ||
1953 | return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs); | |
1954 | } | |
1955 | ||
1956 | /** | |
1957 | * arm_coherent_iommu_unmap_page | |
1958 | * @dev: valid struct device pointer | |
1959 | * @handle: DMA address of buffer | |
1960 | * @size: size of buffer (same as passed to dma_map_page) | |
1961 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1962 | * | |
1963 | * Coherent IOMMU aware version of arm_dma_unmap_page() | |
1964 | */ | |
1965 | static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
00085f1e | 1966 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
0fa478df | 1967 | { |
89cfdb19 | 1968 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
0fa478df | 1969 | dma_addr_t iova = handle & PAGE_MASK; |
0fa478df RH |
1970 | int offset = handle & ~PAGE_MASK; |
1971 | int len = PAGE_ALIGN(size + offset); | |
1972 | ||
1973 | if (!iova) | |
1974 | return; | |
1975 | ||
1976 | iommu_unmap(mapping->domain, iova, len); | |
1977 | __free_iova(mapping, iova, len); | |
1978 | } | |
1979 | ||
4ce63fcd MS |
1980 | /** |
1981 | * arm_iommu_unmap_page | |
1982 | * @dev: valid struct device pointer | |
1983 | * @handle: DMA address of buffer | |
1984 | * @size: size of buffer (same as passed to dma_map_page) | |
1985 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1986 | * | |
1987 | * IOMMU aware version of arm_dma_unmap_page() | |
1988 | */ | |
1989 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
00085f1e | 1990 | size_t size, enum dma_data_direction dir, unsigned long attrs) |
4ce63fcd | 1991 | { |
89cfdb19 | 1992 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
1993 | dma_addr_t iova = handle & PAGE_MASK; |
1994 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1995 | int offset = handle & ~PAGE_MASK; | |
1996 | int len = PAGE_ALIGN(size + offset); | |
1997 | ||
1998 | if (!iova) | |
1999 | return; | |
2000 | ||
00085f1e | 2001 | if ((attrs & DMA_ATTR_SKIP_CPU_SYNC) == 0) |
4ce63fcd MS |
2002 | __dma_page_dev_to_cpu(page, offset, size, dir); |
2003 | ||
2004 | iommu_unmap(mapping->domain, iova, len); | |
2005 | __free_iova(mapping, iova, len); | |
2006 | } | |
2007 | ||
24ed5d2c NS |
2008 | /** |
2009 | * arm_iommu_map_resource - map a device resource for DMA | |
2010 | * @dev: valid struct device pointer | |
2011 | * @phys_addr: physical address of resource | |
2012 | * @size: size of resource to map | |
2013 | * @dir: DMA transfer direction | |
2014 | */ | |
2015 | static dma_addr_t arm_iommu_map_resource(struct device *dev, | |
2016 | phys_addr_t phys_addr, size_t size, | |
2017 | enum dma_data_direction dir, unsigned long attrs) | |
2018 | { | |
2019 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
2020 | dma_addr_t dma_addr; | |
2021 | int ret, prot; | |
2022 | phys_addr_t addr = phys_addr & PAGE_MASK; | |
2023 | unsigned int offset = phys_addr & ~PAGE_MASK; | |
2024 | size_t len = PAGE_ALIGN(size + offset); | |
2025 | ||
2026 | dma_addr = __alloc_iova(mapping, len); | |
9eef8b8c | 2027 | if (dma_addr == ARM_MAPPING_ERROR) |
24ed5d2c NS |
2028 | return dma_addr; |
2029 | ||
7d2822df | 2030 | prot = __dma_info_to_prot(dir, attrs) | IOMMU_MMIO; |
24ed5d2c NS |
2031 | |
2032 | ret = iommu_map(mapping->domain, dma_addr, addr, len, prot); | |
2033 | if (ret < 0) | |
2034 | goto fail; | |
2035 | ||
2036 | return dma_addr + offset; | |
2037 | fail: | |
2038 | __free_iova(mapping, dma_addr, len); | |
9eef8b8c | 2039 | return ARM_MAPPING_ERROR; |
24ed5d2c NS |
2040 | } |
2041 | ||
2042 | /** | |
2043 | * arm_iommu_unmap_resource - unmap a device DMA resource | |
2044 | * @dev: valid struct device pointer | |
2045 | * @dma_handle: DMA address to resource | |
2046 | * @size: size of resource to map | |
2047 | * @dir: DMA transfer direction | |
2048 | */ | |
2049 | static void arm_iommu_unmap_resource(struct device *dev, dma_addr_t dma_handle, | |
2050 | size_t size, enum dma_data_direction dir, | |
2051 | unsigned long attrs) | |
2052 | { | |
2053 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); | |
2054 | dma_addr_t iova = dma_handle & PAGE_MASK; | |
2055 | unsigned int offset = dma_handle & ~PAGE_MASK; | |
2056 | size_t len = PAGE_ALIGN(size + offset); | |
2057 | ||
2058 | if (!iova) | |
2059 | return; | |
2060 | ||
2061 | iommu_unmap(mapping->domain, iova, len); | |
2062 | __free_iova(mapping, iova, len); | |
2063 | } | |
2064 | ||
4ce63fcd MS |
2065 | static void arm_iommu_sync_single_for_cpu(struct device *dev, |
2066 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
2067 | { | |
89cfdb19 | 2068 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
2069 | dma_addr_t iova = handle & PAGE_MASK; |
2070 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
2071 | unsigned int offset = handle & ~PAGE_MASK; | |
2072 | ||
2073 | if (!iova) | |
2074 | return; | |
2075 | ||
0fa478df | 2076 | __dma_page_dev_to_cpu(page, offset, size, dir); |
4ce63fcd MS |
2077 | } |
2078 | ||
2079 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
2080 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
2081 | { | |
89cfdb19 | 2082 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4ce63fcd MS |
2083 | dma_addr_t iova = handle & PAGE_MASK; |
2084 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
2085 | unsigned int offset = handle & ~PAGE_MASK; | |
2086 | ||
2087 | if (!iova) | |
2088 | return; | |
2089 | ||
2090 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
2091 | } | |
2092 | ||
5299709d | 2093 | const struct dma_map_ops iommu_ops = { |
4ce63fcd MS |
2094 | .alloc = arm_iommu_alloc_attrs, |
2095 | .free = arm_iommu_free_attrs, | |
2096 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 2097 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
2098 | |
2099 | .map_page = arm_iommu_map_page, | |
2100 | .unmap_page = arm_iommu_unmap_page, | |
2101 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
2102 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
2103 | ||
2104 | .map_sg = arm_iommu_map_sg, | |
2105 | .unmap_sg = arm_iommu_unmap_sg, | |
2106 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
2107 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
24ed5d2c NS |
2108 | |
2109 | .map_resource = arm_iommu_map_resource, | |
2110 | .unmap_resource = arm_iommu_unmap_resource, | |
9eef8b8c CH |
2111 | |
2112 | .mapping_error = arm_dma_mapping_error, | |
418a7a7e | 2113 | .dma_supported = arm_dma_supported, |
4ce63fcd MS |
2114 | }; |
2115 | ||
5299709d | 2116 | const struct dma_map_ops iommu_coherent_ops = { |
56506822 GC |
2117 | .alloc = arm_coherent_iommu_alloc_attrs, |
2118 | .free = arm_coherent_iommu_free_attrs, | |
2119 | .mmap = arm_coherent_iommu_mmap_attrs, | |
0fa478df RH |
2120 | .get_sgtable = arm_iommu_get_sgtable, |
2121 | ||
2122 | .map_page = arm_coherent_iommu_map_page, | |
2123 | .unmap_page = arm_coherent_iommu_unmap_page, | |
2124 | ||
2125 | .map_sg = arm_coherent_iommu_map_sg, | |
2126 | .unmap_sg = arm_coherent_iommu_unmap_sg, | |
24ed5d2c NS |
2127 | |
2128 | .map_resource = arm_iommu_map_resource, | |
2129 | .unmap_resource = arm_iommu_unmap_resource, | |
9eef8b8c CH |
2130 | |
2131 | .mapping_error = arm_dma_mapping_error, | |
418a7a7e | 2132 | .dma_supported = arm_dma_supported, |
0fa478df RH |
2133 | }; |
2134 | ||
4ce63fcd MS |
2135 | /** |
2136 | * arm_iommu_create_mapping | |
2137 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
2138 | * @base: start address of the valid IO address space | |
68efd7d2 | 2139 | * @size: maximum size of the valid IO address space |
4ce63fcd MS |
2140 | * |
2141 | * Creates a mapping structure which holds information about used/unused | |
2142 | * IO address ranges, which is required to perform memory allocation and | |
2143 | * mapping with IOMMU aware functions. | |
2144 | * | |
2145 | * The client device need to be attached to the mapping with | |
2146 | * arm_iommu_attach_device function. | |
2147 | */ | |
2148 | struct dma_iommu_mapping * | |
1424532b | 2149 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, u64 size) |
4ce63fcd | 2150 | { |
68efd7d2 MS |
2151 | unsigned int bits = size >> PAGE_SHIFT; |
2152 | unsigned int bitmap_size = BITS_TO_LONGS(bits) * sizeof(long); | |
4ce63fcd | 2153 | struct dma_iommu_mapping *mapping; |
68efd7d2 | 2154 | int extensions = 1; |
4ce63fcd MS |
2155 | int err = -ENOMEM; |
2156 | ||
1424532b MS |
2157 | /* currently only 32-bit DMA address space is supported */ |
2158 | if (size > DMA_BIT_MASK(32) + 1) | |
2159 | return ERR_PTR(-ERANGE); | |
2160 | ||
68efd7d2 | 2161 | if (!bitmap_size) |
4ce63fcd MS |
2162 | return ERR_PTR(-EINVAL); |
2163 | ||
68efd7d2 MS |
2164 | if (bitmap_size > PAGE_SIZE) { |
2165 | extensions = bitmap_size / PAGE_SIZE; | |
2166 | bitmap_size = PAGE_SIZE; | |
2167 | } | |
2168 | ||
4ce63fcd MS |
2169 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); |
2170 | if (!mapping) | |
2171 | goto err; | |
2172 | ||
68efd7d2 MS |
2173 | mapping->bitmap_size = bitmap_size; |
2174 | mapping->bitmaps = kzalloc(extensions * sizeof(unsigned long *), | |
4d852ef8 AH |
2175 | GFP_KERNEL); |
2176 | if (!mapping->bitmaps) | |
4ce63fcd MS |
2177 | goto err2; |
2178 | ||
68efd7d2 | 2179 | mapping->bitmaps[0] = kzalloc(bitmap_size, GFP_KERNEL); |
4d852ef8 AH |
2180 | if (!mapping->bitmaps[0]) |
2181 | goto err3; | |
2182 | ||
2183 | mapping->nr_bitmaps = 1; | |
2184 | mapping->extensions = extensions; | |
4ce63fcd | 2185 | mapping->base = base; |
68efd7d2 | 2186 | mapping->bits = BITS_PER_BYTE * bitmap_size; |
4d852ef8 | 2187 | |
4ce63fcd MS |
2188 | spin_lock_init(&mapping->lock); |
2189 | ||
2190 | mapping->domain = iommu_domain_alloc(bus); | |
2191 | if (!mapping->domain) | |
4d852ef8 | 2192 | goto err4; |
4ce63fcd MS |
2193 | |
2194 | kref_init(&mapping->kref); | |
2195 | return mapping; | |
4d852ef8 AH |
2196 | err4: |
2197 | kfree(mapping->bitmaps[0]); | |
4ce63fcd | 2198 | err3: |
4d852ef8 | 2199 | kfree(mapping->bitmaps); |
4ce63fcd MS |
2200 | err2: |
2201 | kfree(mapping); | |
2202 | err: | |
2203 | return ERR_PTR(err); | |
2204 | } | |
18177d12 | 2205 | EXPORT_SYMBOL_GPL(arm_iommu_create_mapping); |
4ce63fcd MS |
2206 | |
2207 | static void release_iommu_mapping(struct kref *kref) | |
2208 | { | |
4d852ef8 | 2209 | int i; |
4ce63fcd MS |
2210 | struct dma_iommu_mapping *mapping = |
2211 | container_of(kref, struct dma_iommu_mapping, kref); | |
2212 | ||
2213 | iommu_domain_free(mapping->domain); | |
4d852ef8 AH |
2214 | for (i = 0; i < mapping->nr_bitmaps; i++) |
2215 | kfree(mapping->bitmaps[i]); | |
2216 | kfree(mapping->bitmaps); | |
4ce63fcd MS |
2217 | kfree(mapping); |
2218 | } | |
2219 | ||
4d852ef8 AH |
2220 | static int extend_iommu_mapping(struct dma_iommu_mapping *mapping) |
2221 | { | |
2222 | int next_bitmap; | |
2223 | ||
462859aa | 2224 | if (mapping->nr_bitmaps >= mapping->extensions) |
4d852ef8 AH |
2225 | return -EINVAL; |
2226 | ||
2227 | next_bitmap = mapping->nr_bitmaps; | |
2228 | mapping->bitmaps[next_bitmap] = kzalloc(mapping->bitmap_size, | |
2229 | GFP_ATOMIC); | |
2230 | if (!mapping->bitmaps[next_bitmap]) | |
2231 | return -ENOMEM; | |
2232 | ||
2233 | mapping->nr_bitmaps++; | |
2234 | ||
2235 | return 0; | |
2236 | } | |
2237 | ||
4ce63fcd MS |
2238 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) |
2239 | { | |
2240 | if (mapping) | |
2241 | kref_put(&mapping->kref, release_iommu_mapping); | |
2242 | } | |
18177d12 | 2243 | EXPORT_SYMBOL_GPL(arm_iommu_release_mapping); |
4ce63fcd | 2244 | |
eab8d653 LP |
2245 | static int __arm_iommu_attach_device(struct device *dev, |
2246 | struct dma_iommu_mapping *mapping) | |
2247 | { | |
2248 | int err; | |
2249 | ||
2250 | err = iommu_attach_device(mapping->domain, dev); | |
2251 | if (err) | |
2252 | return err; | |
2253 | ||
2254 | kref_get(&mapping->kref); | |
89cfdb19 | 2255 | to_dma_iommu_mapping(dev) = mapping; |
eab8d653 LP |
2256 | |
2257 | pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
2258 | return 0; | |
2259 | } | |
2260 | ||
4ce63fcd MS |
2261 | /** |
2262 | * arm_iommu_attach_device | |
2263 | * @dev: valid struct device pointer | |
2264 | * @mapping: io address space mapping structure (returned from | |
2265 | * arm_iommu_create_mapping) | |
2266 | * | |
eab8d653 LP |
2267 | * Attaches specified io address space mapping to the provided device. |
2268 | * This replaces the dma operations (dma_map_ops pointer) with the | |
2269 | * IOMMU aware version. | |
2270 | * | |
4bb25789 WD |
2271 | * More than one client might be attached to the same io address space |
2272 | * mapping. | |
4ce63fcd MS |
2273 | */ |
2274 | int arm_iommu_attach_device(struct device *dev, | |
2275 | struct dma_iommu_mapping *mapping) | |
2276 | { | |
2277 | int err; | |
2278 | ||
eab8d653 | 2279 | err = __arm_iommu_attach_device(dev, mapping); |
4ce63fcd MS |
2280 | if (err) |
2281 | return err; | |
2282 | ||
eab8d653 | 2283 | set_dma_ops(dev, &iommu_ops); |
4ce63fcd MS |
2284 | return 0; |
2285 | } | |
18177d12 | 2286 | EXPORT_SYMBOL_GPL(arm_iommu_attach_device); |
4ce63fcd | 2287 | |
d3e01c51 S |
2288 | /** |
2289 | * arm_iommu_detach_device | |
2290 | * @dev: valid struct device pointer | |
2291 | * | |
2292 | * Detaches the provided device from a previously attached map. | |
2293 | * This voids the dma operations (dma_map_ops pointer) | |
2294 | */ | |
2295 | void arm_iommu_detach_device(struct device *dev) | |
6fe36758 HD |
2296 | { |
2297 | struct dma_iommu_mapping *mapping; | |
2298 | ||
2299 | mapping = to_dma_iommu_mapping(dev); | |
2300 | if (!mapping) { | |
2301 | dev_warn(dev, "Not attached\n"); | |
2302 | return; | |
2303 | } | |
2304 | ||
2305 | iommu_detach_device(mapping->domain, dev); | |
2306 | kref_put(&mapping->kref, release_iommu_mapping); | |
89cfdb19 | 2307 | to_dma_iommu_mapping(dev) = NULL; |
d3e01c51 | 2308 | set_dma_ops(dev, NULL); |
6fe36758 HD |
2309 | |
2310 | pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev)); | |
2311 | } | |
18177d12 | 2312 | EXPORT_SYMBOL_GPL(arm_iommu_detach_device); |
6fe36758 | 2313 | |
5299709d | 2314 | static const struct dma_map_ops *arm_get_iommu_dma_map_ops(bool coherent) |
4bb25789 WD |
2315 | { |
2316 | return coherent ? &iommu_coherent_ops : &iommu_ops; | |
2317 | } | |
2318 | ||
2319 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
53c92d79 | 2320 | const struct iommu_ops *iommu) |
4bb25789 WD |
2321 | { |
2322 | struct dma_iommu_mapping *mapping; | |
2323 | ||
2324 | if (!iommu) | |
2325 | return false; | |
2326 | ||
2327 | mapping = arm_iommu_create_mapping(dev->bus, dma_base, size); | |
2328 | if (IS_ERR(mapping)) { | |
2329 | pr_warn("Failed to create %llu-byte IOMMU mapping for device %s\n", | |
2330 | size, dev_name(dev)); | |
2331 | return false; | |
2332 | } | |
2333 | ||
eab8d653 | 2334 | if (__arm_iommu_attach_device(dev, mapping)) { |
4bb25789 WD |
2335 | pr_warn("Failed to attached device %s to IOMMU_mapping\n", |
2336 | dev_name(dev)); | |
2337 | arm_iommu_release_mapping(mapping); | |
2338 | return false; | |
2339 | } | |
2340 | ||
2341 | return true; | |
2342 | } | |
2343 | ||
2344 | static void arm_teardown_iommu_dma_ops(struct device *dev) | |
2345 | { | |
89cfdb19 | 2346 | struct dma_iommu_mapping *mapping = to_dma_iommu_mapping(dev); |
4bb25789 | 2347 | |
c2273a18 WD |
2348 | if (!mapping) |
2349 | return; | |
2350 | ||
d3e01c51 | 2351 | arm_iommu_detach_device(dev); |
4bb25789 WD |
2352 | arm_iommu_release_mapping(mapping); |
2353 | } | |
2354 | ||
2355 | #else | |
2356 | ||
2357 | static bool arm_setup_iommu_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
53c92d79 | 2358 | const struct iommu_ops *iommu) |
4bb25789 WD |
2359 | { |
2360 | return false; | |
2361 | } | |
2362 | ||
2363 | static void arm_teardown_iommu_dma_ops(struct device *dev) { } | |
2364 | ||
2365 | #define arm_get_iommu_dma_map_ops arm_get_dma_map_ops | |
2366 | ||
2367 | #endif /* CONFIG_ARM_DMA_USE_IOMMU */ | |
2368 | ||
5299709d | 2369 | static const struct dma_map_ops *arm_get_dma_map_ops(bool coherent) |
4bb25789 WD |
2370 | { |
2371 | return coherent ? &arm_coherent_dma_ops : &arm_dma_ops; | |
2372 | } | |
2373 | ||
2374 | void arch_setup_dma_ops(struct device *dev, u64 dma_base, u64 size, | |
53c92d79 | 2375 | const struct iommu_ops *iommu, bool coherent) |
4bb25789 | 2376 | { |
5299709d | 2377 | const struct dma_map_ops *dma_ops; |
4bb25789 | 2378 | |
6f51ee70 | 2379 | dev->archdata.dma_coherent = coherent; |
26b37b94 LP |
2380 | |
2381 | /* | |
2382 | * Don't override the dma_ops if they have already been set. Ideally | |
2383 | * this should be the only location where dma_ops are set, remove this | |
2384 | * check when all other callers of set_dma_ops will have disappeared. | |
2385 | */ | |
2386 | if (dev->dma_ops) | |
2387 | return; | |
2388 | ||
4bb25789 WD |
2389 | if (arm_setup_iommu_dma_ops(dev, dma_base, size, iommu)) |
2390 | dma_ops = arm_get_iommu_dma_map_ops(coherent); | |
2391 | else | |
2392 | dma_ops = arm_get_dma_map_ops(coherent); | |
2393 | ||
2394 | set_dma_ops(dev, dma_ops); | |
e0586326 SS |
2395 | |
2396 | #ifdef CONFIG_XEN | |
2397 | if (xen_initial_domain()) { | |
2398 | dev->archdata.dev_dma_ops = dev->dma_ops; | |
2399 | dev->dma_ops = xen_dma_ops; | |
2400 | } | |
2401 | #endif | |
a93a121a | 2402 | dev->archdata.dma_ops_setup = true; |
4bb25789 WD |
2403 | } |
2404 | ||
2405 | void arch_teardown_dma_ops(struct device *dev) | |
2406 | { | |
a93a121a LP |
2407 | if (!dev->archdata.dma_ops_setup) |
2408 | return; | |
2409 | ||
4bb25789 | 2410 | arm_teardown_iommu_dma_ops(dev); |
6b315b9b RM |
2411 | /* Let arch_setup_dma_ops() start again from scratch upon re-probe */ |
2412 | set_dma_ops(dev, NULL); | |
4bb25789 | 2413 | } |