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d111e8f9 RK |
1 | /* |
2 | * linux/arch/arm/mm/mmu.c | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ae8f1541 | 10 | #include <linux/module.h> |
d111e8f9 RK |
11 | #include <linux/kernel.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/bootmem.h> | |
15 | #include <linux/mman.h> | |
16 | #include <linux/nodemask.h> | |
17 | ||
0ba8b9b2 | 18 | #include <asm/cputype.h> |
d111e8f9 | 19 | #include <asm/mach-types.h> |
37efe642 | 20 | #include <asm/sections.h> |
3f973e22 | 21 | #include <asm/cachetype.h> |
d111e8f9 RK |
22 | #include <asm/setup.h> |
23 | #include <asm/sizes.h> | |
e616c591 | 24 | #include <asm/smp_plat.h> |
d111e8f9 | 25 | #include <asm/tlb.h> |
d73cd428 | 26 | #include <asm/highmem.h> |
d111e8f9 RK |
27 | |
28 | #include <asm/mach/arch.h> | |
29 | #include <asm/mach/map.h> | |
30 | ||
31 | #include "mm.h" | |
32 | ||
33 | DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); | |
34 | ||
d111e8f9 RK |
35 | /* |
36 | * empty_zero_page is a special page that is used for | |
37 | * zero-initialized data and COW. | |
38 | */ | |
39 | struct page *empty_zero_page; | |
3653f3ab | 40 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
41 | |
42 | /* | |
43 | * The pmd table for the upper-most set of pages. | |
44 | */ | |
45 | pmd_t *top_pmd; | |
46 | ||
ae8f1541 RK |
47 | #define CPOLICY_UNCACHED 0 |
48 | #define CPOLICY_BUFFERED 1 | |
49 | #define CPOLICY_WRITETHROUGH 2 | |
50 | #define CPOLICY_WRITEBACK 3 | |
51 | #define CPOLICY_WRITEALLOC 4 | |
52 | ||
53 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
54 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 55 | pgprot_t pgprot_user; |
ae8f1541 RK |
56 | pgprot_t pgprot_kernel; |
57 | ||
44b18693 | 58 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
59 | EXPORT_SYMBOL(pgprot_kernel); |
60 | ||
61 | struct cachepolicy { | |
62 | const char policy[16]; | |
63 | unsigned int cr_mask; | |
64 | unsigned int pmd; | |
65 | unsigned int pte; | |
66 | }; | |
67 | ||
68 | static struct cachepolicy cache_policies[] __initdata = { | |
69 | { | |
70 | .policy = "uncached", | |
71 | .cr_mask = CR_W|CR_C, | |
72 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 73 | .pte = L_PTE_MT_UNCACHED, |
ae8f1541 RK |
74 | }, { |
75 | .policy = "buffered", | |
76 | .cr_mask = CR_C, | |
77 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 78 | .pte = L_PTE_MT_BUFFERABLE, |
ae8f1541 RK |
79 | }, { |
80 | .policy = "writethrough", | |
81 | .cr_mask = 0, | |
82 | .pmd = PMD_SECT_WT, | |
bb30f36f | 83 | .pte = L_PTE_MT_WRITETHROUGH, |
ae8f1541 RK |
84 | }, { |
85 | .policy = "writeback", | |
86 | .cr_mask = 0, | |
87 | .pmd = PMD_SECT_WB, | |
bb30f36f | 88 | .pte = L_PTE_MT_WRITEBACK, |
ae8f1541 RK |
89 | }, { |
90 | .policy = "writealloc", | |
91 | .cr_mask = 0, | |
92 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 93 | .pte = L_PTE_MT_WRITEALLOC, |
ae8f1541 RK |
94 | } |
95 | }; | |
96 | ||
97 | /* | |
6cbdc8c5 | 98 | * These are useful for identifying cache coherency |
ae8f1541 RK |
99 | * problems by allowing the cache or the cache and |
100 | * writebuffer to be turned off. (Note: the write | |
101 | * buffer should not be on and the cache off). | |
102 | */ | |
2b0d8c25 | 103 | static int __init early_cachepolicy(char *p) |
ae8f1541 RK |
104 | { |
105 | int i; | |
106 | ||
107 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { | |
108 | int len = strlen(cache_policies[i].policy); | |
109 | ||
2b0d8c25 | 110 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ae8f1541 RK |
111 | cachepolicy = i; |
112 | cr_alignment &= ~cache_policies[i].cr_mask; | |
113 | cr_no_alignment &= ~cache_policies[i].cr_mask; | |
ae8f1541 RK |
114 | break; |
115 | } | |
116 | } | |
117 | if (i == ARRAY_SIZE(cache_policies)) | |
118 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); | |
4b46d641 RK |
119 | /* |
120 | * This restriction is partly to do with the way we boot; it is | |
121 | * unpredictable to have memory mapped using two different sets of | |
122 | * memory attributes (shared, type, and cache attribs). We can not | |
123 | * change these attributes once the initial assembly has setup the | |
124 | * page tables. | |
125 | */ | |
11179d8c CM |
126 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
127 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); | |
128 | cachepolicy = CPOLICY_WRITEBACK; | |
129 | } | |
ae8f1541 RK |
130 | flush_cache_all(); |
131 | set_cr(cr_alignment); | |
2b0d8c25 | 132 | return 0; |
ae8f1541 | 133 | } |
2b0d8c25 | 134 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 135 | |
2b0d8c25 | 136 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
137 | { |
138 | char *p = "buffered"; | |
139 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
140 | early_cachepolicy(p); |
141 | return 0; | |
ae8f1541 | 142 | } |
2b0d8c25 | 143 | early_param("nocache", early_nocache); |
ae8f1541 | 144 | |
2b0d8c25 | 145 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
146 | { |
147 | char *p = "uncached"; | |
148 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
149 | early_cachepolicy(p); |
150 | return 0; | |
ae8f1541 | 151 | } |
2b0d8c25 | 152 | early_param("nowb", early_nowrite); |
ae8f1541 | 153 | |
2b0d8c25 | 154 | static int __init early_ecc(char *p) |
ae8f1541 | 155 | { |
2b0d8c25 | 156 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 157 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 158 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 159 | ecc_mask = 0; |
2b0d8c25 | 160 | return 0; |
ae8f1541 | 161 | } |
2b0d8c25 | 162 | early_param("ecc", early_ecc); |
ae8f1541 RK |
163 | |
164 | static int __init noalign_setup(char *__unused) | |
165 | { | |
166 | cr_alignment &= ~CR_A; | |
167 | cr_no_alignment &= ~CR_A; | |
168 | set_cr(cr_alignment); | |
169 | return 1; | |
170 | } | |
171 | __setup("noalign", noalign_setup); | |
172 | ||
255d1f86 RK |
173 | #ifndef CONFIG_SMP |
174 | void adjust_cr(unsigned long mask, unsigned long set) | |
175 | { | |
176 | unsigned long flags; | |
177 | ||
178 | mask &= ~CR_A; | |
179 | ||
180 | set &= mask; | |
181 | ||
182 | local_irq_save(flags); | |
183 | ||
184 | cr_no_alignment = (cr_no_alignment & ~mask) | set; | |
185 | cr_alignment = (cr_alignment & ~mask) | set; | |
186 | ||
187 | set_cr((get_cr() & ~mask) | set); | |
188 | ||
189 | local_irq_restore(flags); | |
190 | } | |
191 | #endif | |
192 | ||
0af92bef | 193 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE |
b1cce6b1 | 194 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 195 | |
b29e9f5e | 196 | static struct mem_type mem_types[] = { |
0af92bef | 197 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
198 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
199 | L_PTE_SHARED, | |
0af92bef | 200 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 201 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
202 | .domain = DOMAIN_IO, |
203 | }, | |
204 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 205 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 206 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 207 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
208 | .domain = DOMAIN_IO, |
209 | }, | |
210 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 211 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
212 | .prot_l1 = PMD_TYPE_TABLE, |
213 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
214 | .domain = DOMAIN_IO, | |
215 | }, | |
1ad77a87 | 216 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 217 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 218 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 219 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 220 | .domain = DOMAIN_IO, |
ae8f1541 | 221 | }, |
ebb4c658 RK |
222 | [MT_UNCACHED] = { |
223 | .prot_pte = PROT_PTE_DEVICE, | |
224 | .prot_l1 = PMD_TYPE_TABLE, | |
225 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
226 | .domain = DOMAIN_IO, | |
227 | }, | |
ae8f1541 | 228 | [MT_CACHECLEAN] = { |
9ef79635 | 229 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
230 | .domain = DOMAIN_KERNEL, |
231 | }, | |
232 | [MT_MINICLEAN] = { | |
9ef79635 | 233 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
234 | .domain = DOMAIN_KERNEL, |
235 | }, | |
236 | [MT_LOW_VECTORS] = { | |
237 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
238 | L_PTE_EXEC, | |
239 | .prot_l1 = PMD_TYPE_TABLE, | |
240 | .domain = DOMAIN_USER, | |
241 | }, | |
242 | [MT_HIGH_VECTORS] = { | |
243 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
244 | L_PTE_USER | L_PTE_EXEC, | |
245 | .prot_l1 = PMD_TYPE_TABLE, | |
246 | .domain = DOMAIN_USER, | |
247 | }, | |
248 | [MT_MEMORY] = { | |
9ef79635 | 249 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
250 | .domain = DOMAIN_KERNEL, |
251 | }, | |
252 | [MT_ROM] = { | |
9ef79635 | 253 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
254 | .domain = DOMAIN_KERNEL, |
255 | }, | |
e4707dd3 PW |
256 | [MT_MEMORY_NONCACHED] = { |
257 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, | |
258 | .domain = DOMAIN_KERNEL, | |
259 | }, | |
ae8f1541 RK |
260 | }; |
261 | ||
b29e9f5e RK |
262 | const struct mem_type *get_mem_type(unsigned int type) |
263 | { | |
264 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
265 | } | |
69d3a84a | 266 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 267 | |
ae8f1541 RK |
268 | /* |
269 | * Adjust the PMD section entries according to the CPU in use. | |
270 | */ | |
271 | static void __init build_mem_type_table(void) | |
272 | { | |
273 | struct cachepolicy *cp; | |
274 | unsigned int cr = get_cr(); | |
bb30f36f | 275 | unsigned int user_pgprot, kern_pgprot, vecs_pgprot; |
ae8f1541 RK |
276 | int cpu_arch = cpu_architecture(); |
277 | int i; | |
278 | ||
11179d8c | 279 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 280 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
281 | if (cachepolicy > CPOLICY_BUFFERED) |
282 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 283 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
284 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
285 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 286 | #endif |
11179d8c | 287 | } |
ae8f1541 RK |
288 | if (cpu_arch < CPU_ARCH_ARMv5) { |
289 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
290 | cachepolicy = CPOLICY_WRITEBACK; | |
291 | ecc_mask = 0; | |
292 | } | |
bb30f36f RK |
293 | #ifdef CONFIG_SMP |
294 | cachepolicy = CPOLICY_WRITEALLOC; | |
295 | #endif | |
ae8f1541 | 296 | |
1ad77a87 | 297 | /* |
b1cce6b1 RK |
298 | * Strip out features not present on earlier architectures. |
299 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
300 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 301 | */ |
b1cce6b1 RK |
302 | if (cpu_arch < CPU_ARCH_ARMv5) |
303 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
304 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
305 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
306 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
307 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
308 | |
309 | /* | |
b1cce6b1 RK |
310 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
311 | * "update-able on write" bit on ARM610). However, Xscale and | |
312 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 313 | */ |
b1cce6b1 | 314 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
9ef79635 | 315 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 316 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
317 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
318 | } | |
319 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
320 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
321 | if (mem_types[i].prot_l1) |
322 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
323 | if (mem_types[i].prot_sect) |
324 | mem_types[i].prot_sect |= PMD_BIT4; | |
325 | } | |
326 | } | |
ae8f1541 | 327 | |
b1cce6b1 RK |
328 | /* |
329 | * Mark the device areas according to the CPU/architecture. | |
330 | */ | |
331 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
332 | if (!cpu_is_xsc3()) { | |
333 | /* | |
334 | * Mark device regions on ARMv6+ as execute-never | |
335 | * to prevent speculative instruction fetches. | |
336 | */ | |
337 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
338 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
339 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
340 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
341 | } | |
342 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
343 | /* | |
344 | * For ARMv7 with TEX remapping, | |
345 | * - shared device is SXCB=1100 | |
346 | * - nonshared device is SXCB=0100 | |
347 | * - write combine device mem is SXCB=0001 | |
348 | * (Uncached Normal memory) | |
349 | */ | |
350 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
351 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
352 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
353 | } else if (cpu_is_xsc3()) { | |
354 | /* | |
355 | * For Xscale3, | |
356 | * - shared device is TEXCB=00101 | |
357 | * - nonshared device is TEXCB=01000 | |
358 | * - write combine device mem is TEXCB=00100 | |
359 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
360 | */ | |
361 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
362 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
363 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
364 | } else { | |
365 | /* | |
366 | * For ARMv6 and ARMv7 without TEX remapping, | |
367 | * - shared device is TEXCB=00001 | |
368 | * - nonshared device is TEXCB=01000 | |
369 | * - write combine device mem is TEXCB=00100 | |
370 | * (Uncached Normal in ARMv6 parlance). | |
371 | */ | |
372 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
373 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
374 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
375 | } | |
376 | } else { | |
377 | /* | |
378 | * On others, write combining is "Uncached/Buffered" | |
379 | */ | |
380 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
381 | } | |
382 | ||
383 | /* | |
384 | * Now deal with the memory-type mappings | |
385 | */ | |
ae8f1541 | 386 | cp = &cache_policies[cachepolicy]; |
bb30f36f RK |
387 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
388 | ||
389 | #ifndef CONFIG_SMP | |
390 | /* | |
391 | * Only use write-through for non-SMP systems | |
392 | */ | |
393 | if (cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) | |
394 | vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; | |
395 | #endif | |
ae8f1541 RK |
396 | |
397 | /* | |
398 | * Enable CPU-specific coherency if supported. | |
399 | * (Only available on XSC3 at the moment.) | |
400 | */ | |
b1cce6b1 RK |
401 | if (arch_is_coherent() && cpu_is_xsc3()) |
402 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; | |
ae8f1541 RK |
403 | |
404 | /* | |
405 | * ARMv6 and above have extended page tables. | |
406 | */ | |
407 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
ae8f1541 RK |
408 | /* |
409 | * Mark cache clean areas and XIP ROM read only | |
410 | * from SVC mode and no access from userspace. | |
411 | */ | |
412 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
413 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
414 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
415 | ||
ae8f1541 RK |
416 | #ifdef CONFIG_SMP |
417 | /* | |
418 | * Mark memory with the "shared" attribute for SMP systems | |
419 | */ | |
420 | user_pgprot |= L_PTE_SHARED; | |
421 | kern_pgprot |= L_PTE_SHARED; | |
bb30f36f | 422 | vecs_pgprot |= L_PTE_SHARED; |
ae8f1541 | 423 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
e4707dd3 | 424 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; |
ae8f1541 RK |
425 | #endif |
426 | } | |
427 | ||
e4707dd3 PW |
428 | /* |
429 | * Non-cacheable Normal - intended for memory areas that must | |
430 | * not cause dirty cache line writebacks when used | |
431 | */ | |
432 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
433 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
434 | /* Non-cacheable Normal is XCB = 001 */ | |
435 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
436 | PMD_SECT_BUFFERED; | |
437 | } else { | |
438 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
439 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
440 | PMD_SECT_TEX(1); | |
441 | } | |
442 | } else { | |
443 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; | |
444 | } | |
445 | ||
ae8f1541 RK |
446 | for (i = 0; i < 16; i++) { |
447 | unsigned long v = pgprot_val(protection_map[i]); | |
bb30f36f | 448 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
449 | } |
450 | ||
bb30f36f RK |
451 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
452 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 453 | |
44b18693 | 454 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 455 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
6dc995a3 | 456 | L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot); |
ae8f1541 RK |
457 | |
458 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
459 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
460 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; | |
461 | mem_types[MT_ROM].prot_sect |= cp->pmd; | |
462 | ||
463 | switch (cp->pmd) { | |
464 | case PMD_SECT_WT: | |
465 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
466 | break; | |
467 | case PMD_SECT_WB: | |
468 | case PMD_SECT_WBWA: | |
469 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
470 | break; | |
471 | } | |
472 | printk("Memory policy: ECC %sabled, Data cache %s\n", | |
473 | ecc_mask ? "en" : "dis", cp->policy); | |
2497f0a8 RK |
474 | |
475 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
476 | struct mem_type *t = &mem_types[i]; | |
477 | if (t->prot_l1) | |
478 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
479 | if (t->prot_sect) | |
480 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
481 | } | |
ae8f1541 RK |
482 | } |
483 | ||
484 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) | |
485 | ||
24e6c699 RK |
486 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
487 | unsigned long end, unsigned long pfn, | |
488 | const struct mem_type *type) | |
ae8f1541 | 489 | { |
24e6c699 | 490 | pte_t *pte; |
ae8f1541 | 491 | |
24e6c699 RK |
492 | if (pmd_none(*pmd)) { |
493 | pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); | |
494 | __pmd_populate(pmd, __pa(pte) | type->prot_l1); | |
495 | } | |
ae8f1541 | 496 | |
24e6c699 RK |
497 | pte = pte_offset_kernel(pmd, addr); |
498 | do { | |
40d192b6 | 499 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
24e6c699 RK |
500 | pfn++; |
501 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
502 | } |
503 | ||
24e6c699 RK |
504 | static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, |
505 | unsigned long end, unsigned long phys, | |
506 | const struct mem_type *type) | |
ae8f1541 | 507 | { |
24e6c699 | 508 | pmd_t *pmd = pmd_offset(pgd, addr); |
ae8f1541 | 509 | |
24e6c699 RK |
510 | /* |
511 | * Try a section mapping - end, addr and phys must all be aligned | |
512 | * to a section boundary. Note that PMDs refer to the individual | |
513 | * L1 entries, whereas PGDs refer to a group of L1 entries making | |
514 | * up one logical pointer to an L2 table. | |
515 | */ | |
516 | if (((addr | end | phys) & ~SECTION_MASK) == 0) { | |
517 | pmd_t *p = pmd; | |
ae8f1541 | 518 | |
24e6c699 RK |
519 | if (addr & SECTION_SIZE) |
520 | pmd++; | |
521 | ||
522 | do { | |
523 | *pmd = __pmd(phys | type->prot_sect); | |
524 | phys += SECTION_SIZE; | |
525 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
ae8f1541 | 526 | |
24e6c699 RK |
527 | flush_pmd_entry(p); |
528 | } else { | |
529 | /* | |
530 | * No need to loop; pte's aren't interested in the | |
531 | * individual L1 entries. | |
532 | */ | |
533 | alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); | |
534 | } | |
ae8f1541 RK |
535 | } |
536 | ||
4a56c1e4 RK |
537 | static void __init create_36bit_mapping(struct map_desc *md, |
538 | const struct mem_type *type) | |
539 | { | |
540 | unsigned long phys, addr, length, end; | |
541 | pgd_t *pgd; | |
542 | ||
543 | addr = md->virtual; | |
544 | phys = (unsigned long)__pfn_to_phys(md->pfn); | |
545 | length = PAGE_ALIGN(md->length); | |
546 | ||
547 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
548 | printk(KERN_ERR "MM: CPU does not support supersection " | |
549 | "mapping for 0x%08llx at 0x%08lx\n", | |
550 | __pfn_to_phys((u64)md->pfn), addr); | |
551 | return; | |
552 | } | |
553 | ||
554 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
555 | * Since domain assignments can in fact be arbitrary, the | |
556 | * 'domain == 0' check below is required to insure that ARMv6 | |
557 | * supersections are only allocated for domain 0 regardless | |
558 | * of the actual domain assignments in use. | |
559 | */ | |
560 | if (type->domain) { | |
561 | printk(KERN_ERR "MM: invalid domain in supersection " | |
562 | "mapping for 0x%08llx at 0x%08lx\n", | |
563 | __pfn_to_phys((u64)md->pfn), addr); | |
564 | return; | |
565 | } | |
566 | ||
567 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
568 | printk(KERN_ERR "MM: cannot create mapping for " | |
569 | "0x%08llx at 0x%08lx invalid alignment\n", | |
570 | __pfn_to_phys((u64)md->pfn), addr); | |
571 | return; | |
572 | } | |
573 | ||
574 | /* | |
575 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
576 | * (See ARMv6 spec). | |
577 | */ | |
578 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
579 | ||
580 | pgd = pgd_offset_k(addr); | |
581 | end = addr + length; | |
582 | do { | |
583 | pmd_t *pmd = pmd_offset(pgd, addr); | |
584 | int i; | |
585 | ||
586 | for (i = 0; i < 16; i++) | |
587 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); | |
588 | ||
589 | addr += SUPERSECTION_SIZE; | |
590 | phys += SUPERSECTION_SIZE; | |
591 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
592 | } while (addr != end); | |
593 | } | |
594 | ||
ae8f1541 RK |
595 | /* |
596 | * Create the page directory entries and any necessary | |
597 | * page tables for the mapping specified by `md'. We | |
598 | * are able to cope here with varying sizes and address | |
599 | * offsets, and we take full advantage of sections and | |
600 | * supersections. | |
601 | */ | |
602 | void __init create_mapping(struct map_desc *md) | |
603 | { | |
24e6c699 | 604 | unsigned long phys, addr, length, end; |
d5c98176 | 605 | const struct mem_type *type; |
24e6c699 | 606 | pgd_t *pgd; |
ae8f1541 RK |
607 | |
608 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
609 | printk(KERN_WARNING "BUG: not creating mapping for " | |
610 | "0x%08llx at 0x%08lx in user region\n", | |
611 | __pfn_to_phys((u64)md->pfn), md->virtual); | |
612 | return; | |
613 | } | |
614 | ||
615 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
616 | md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { | |
617 | printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx " | |
618 | "overlaps vmalloc space\n", | |
619 | __pfn_to_phys((u64)md->pfn), md->virtual); | |
620 | } | |
621 | ||
d5c98176 | 622 | type = &mem_types[md->type]; |
ae8f1541 RK |
623 | |
624 | /* | |
625 | * Catch 36-bit addresses | |
626 | */ | |
4a56c1e4 RK |
627 | if (md->pfn >= 0x100000) { |
628 | create_36bit_mapping(md, type); | |
629 | return; | |
ae8f1541 RK |
630 | } |
631 | ||
7b9c7b4d | 632 | addr = md->virtual & PAGE_MASK; |
24e6c699 | 633 | phys = (unsigned long)__pfn_to_phys(md->pfn); |
7b9c7b4d | 634 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 635 | |
24e6c699 | 636 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
ae8f1541 RK |
637 | printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " |
638 | "be mapped using pages, ignoring.\n", | |
24e6c699 | 639 | __pfn_to_phys(md->pfn), addr); |
ae8f1541 RK |
640 | return; |
641 | } | |
642 | ||
24e6c699 RK |
643 | pgd = pgd_offset_k(addr); |
644 | end = addr + length; | |
645 | do { | |
646 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 647 | |
24e6c699 | 648 | alloc_init_section(pgd, addr, next, phys, type); |
ae8f1541 | 649 | |
24e6c699 RK |
650 | phys += next - addr; |
651 | addr = next; | |
652 | } while (pgd++, addr != end); | |
ae8f1541 RK |
653 | } |
654 | ||
655 | /* | |
656 | * Create the architecture specific mappings | |
657 | */ | |
658 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
659 | { | |
660 | int i; | |
661 | ||
662 | for (i = 0; i < nr; i++) | |
663 | create_mapping(io_desc + i); | |
664 | } | |
665 | ||
6c5da7ac RK |
666 | static unsigned long __initdata vmalloc_reserve = SZ_128M; |
667 | ||
668 | /* | |
669 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
670 | * bytes. This can be used to increase (or decrease) the vmalloc | |
671 | * area - the default is 128m. | |
672 | */ | |
2b0d8c25 | 673 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 674 | { |
2b0d8c25 | 675 | vmalloc_reserve = memparse(arg, NULL); |
6c5da7ac RK |
676 | |
677 | if (vmalloc_reserve < SZ_16M) { | |
678 | vmalloc_reserve = SZ_16M; | |
679 | printk(KERN_WARNING | |
680 | "vmalloc area too small, limiting to %luMB\n", | |
681 | vmalloc_reserve >> 20); | |
682 | } | |
9210807c NP |
683 | |
684 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { | |
685 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); | |
686 | printk(KERN_WARNING | |
687 | "vmalloc area is too big, limiting to %luMB\n", | |
688 | vmalloc_reserve >> 20); | |
689 | } | |
2b0d8c25 | 690 | return 0; |
6c5da7ac | 691 | } |
2b0d8c25 | 692 | early_param("vmalloc", early_vmalloc); |
6c5da7ac RK |
693 | |
694 | #define VMALLOC_MIN (void *)(VMALLOC_END - vmalloc_reserve) | |
695 | ||
4b5f32ce | 696 | static void __init sanity_check_meminfo(void) |
60296c71 | 697 | { |
dde5828f | 698 | int i, j, highmem = 0; |
60296c71 | 699 | |
4b5f32ce | 700 | for (i = 0, j = 0; i < meminfo.nr_banks; i++) { |
a1bbaec0 NP |
701 | struct membank *bank = &meminfo.bank[j]; |
702 | *bank = meminfo.bank[i]; | |
60296c71 | 703 | |
a1bbaec0 | 704 | #ifdef CONFIG_HIGHMEM |
dde5828f RK |
705 | if (__va(bank->start) > VMALLOC_MIN || |
706 | __va(bank->start) < (void *)PAGE_OFFSET) | |
707 | highmem = 1; | |
708 | ||
709 | bank->highmem = highmem; | |
710 | ||
a1bbaec0 NP |
711 | /* |
712 | * Split those memory banks which are partially overlapping | |
713 | * the vmalloc area greatly simplifying things later. | |
714 | */ | |
715 | if (__va(bank->start) < VMALLOC_MIN && | |
716 | bank->size > VMALLOC_MIN - __va(bank->start)) { | |
717 | if (meminfo.nr_banks >= NR_BANKS) { | |
718 | printk(KERN_CRIT "NR_BANKS too low, " | |
719 | "ignoring high memory\n"); | |
720 | } else { | |
721 | memmove(bank + 1, bank, | |
722 | (meminfo.nr_banks - i) * sizeof(*bank)); | |
723 | meminfo.nr_banks++; | |
724 | i++; | |
725 | bank[1].size -= VMALLOC_MIN - __va(bank->start); | |
726 | bank[1].start = __pa(VMALLOC_MIN - 1) + 1; | |
dde5828f | 727 | bank[1].highmem = highmem = 1; |
a1bbaec0 NP |
728 | j++; |
729 | } | |
730 | bank->size = VMALLOC_MIN - __va(bank->start); | |
731 | } | |
732 | #else | |
041d785f RK |
733 | bank->highmem = highmem; |
734 | ||
a1bbaec0 NP |
735 | /* |
736 | * Check whether this memory bank would entirely overlap | |
737 | * the vmalloc area. | |
738 | */ | |
3fd9825c | 739 | if (__va(bank->start) >= VMALLOC_MIN || |
f0bba9f9 | 740 | __va(bank->start) < (void *)PAGE_OFFSET) { |
a1bbaec0 NP |
741 | printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " |
742 | "(vmalloc region overlap).\n", | |
743 | bank->start, bank->start + bank->size - 1); | |
744 | continue; | |
745 | } | |
60296c71 | 746 | |
a1bbaec0 NP |
747 | /* |
748 | * Check whether this memory bank would partially overlap | |
749 | * the vmalloc area. | |
750 | */ | |
751 | if (__va(bank->start + bank->size) > VMALLOC_MIN || | |
752 | __va(bank->start + bank->size) < __va(bank->start)) { | |
753 | unsigned long newsize = VMALLOC_MIN - __va(bank->start); | |
754 | printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx " | |
755 | "to -%.8lx (vmalloc region overlap).\n", | |
756 | bank->start, bank->start + bank->size - 1, | |
757 | bank->start + newsize - 1); | |
758 | bank->size = newsize; | |
759 | } | |
760 | #endif | |
761 | j++; | |
60296c71 | 762 | } |
e616c591 RK |
763 | #ifdef CONFIG_HIGHMEM |
764 | if (highmem) { | |
765 | const char *reason = NULL; | |
766 | ||
767 | if (cache_is_vipt_aliasing()) { | |
768 | /* | |
769 | * Interactions between kmap and other mappings | |
770 | * make highmem support with aliasing VIPT caches | |
771 | * rather difficult. | |
772 | */ | |
773 | reason = "with VIPT aliasing cache"; | |
774 | #ifdef CONFIG_SMP | |
775 | } else if (tlb_ops_need_broadcast()) { | |
776 | /* | |
777 | * kmap_high needs to occasionally flush TLB entries, | |
778 | * however, if the TLB entries need to be broadcast | |
779 | * we may deadlock: | |
780 | * kmap_high(irqs off)->flush_all_zero_pkmaps-> | |
781 | * flush_tlb_kernel_range->smp_call_function_many | |
782 | * (must not be called with irqs off) | |
783 | */ | |
784 | reason = "without hardware TLB ops broadcasting"; | |
785 | #endif | |
786 | } | |
787 | if (reason) { | |
788 | printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", | |
789 | reason); | |
790 | while (j > 0 && meminfo.bank[j - 1].highmem) | |
791 | j--; | |
792 | } | |
793 | } | |
794 | #endif | |
4b5f32ce | 795 | meminfo.nr_banks = j; |
60296c71 LB |
796 | } |
797 | ||
4b5f32ce | 798 | static inline void prepare_page_table(void) |
d111e8f9 RK |
799 | { |
800 | unsigned long addr; | |
801 | ||
802 | /* | |
803 | * Clear out all the mappings below the kernel image. | |
804 | */ | |
ab4f2ee1 | 805 | for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE) |
d111e8f9 RK |
806 | pmd_clear(pmd_off_k(addr)); |
807 | ||
808 | #ifdef CONFIG_XIP_KERNEL | |
809 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
37efe642 | 810 | addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK; |
d111e8f9 RK |
811 | #endif |
812 | for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) | |
813 | pmd_clear(pmd_off_k(addr)); | |
814 | ||
815 | /* | |
816 | * Clear out all the kernel space mappings, except for the first | |
817 | * memory bank, up to the end of the vmalloc region. | |
818 | */ | |
4b5f32ce | 819 | for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0])); |
d111e8f9 RK |
820 | addr < VMALLOC_END; addr += PGDIR_SIZE) |
821 | pmd_clear(pmd_off_k(addr)); | |
822 | } | |
823 | ||
824 | /* | |
825 | * Reserve the various regions of node 0 | |
826 | */ | |
827 | void __init reserve_node_zero(pg_data_t *pgdat) | |
828 | { | |
829 | unsigned long res_size = 0; | |
830 | ||
831 | /* | |
832 | * Register the kernel text and data with bootmem. | |
833 | * Note that this can only be in node 0. | |
834 | */ | |
835 | #ifdef CONFIG_XIP_KERNEL | |
37efe642 | 836 | reserve_bootmem_node(pgdat, __pa(_data), _end - _data, |
72a7fe39 | 837 | BOOTMEM_DEFAULT); |
d111e8f9 | 838 | #else |
37efe642 | 839 | reserve_bootmem_node(pgdat, __pa(_stext), _end - _stext, |
72a7fe39 | 840 | BOOTMEM_DEFAULT); |
d111e8f9 RK |
841 | #endif |
842 | ||
843 | /* | |
844 | * Reserve the page tables. These are already in use, | |
845 | * and can only be in node 0. | |
846 | */ | |
847 | reserve_bootmem_node(pgdat, __pa(swapper_pg_dir), | |
72a7fe39 | 848 | PTRS_PER_PGD * sizeof(pgd_t), BOOTMEM_DEFAULT); |
d111e8f9 RK |
849 | |
850 | /* | |
851 | * Hmm... This should go elsewhere, but we really really need to | |
852 | * stop things allocating the low memory; ideally we need a better | |
853 | * implementation of GFP_DMA which does not assume that DMA-able | |
854 | * memory starts at zero. | |
855 | */ | |
856 | if (machine_is_integrator() || machine_is_cintegrator()) | |
857 | res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; | |
858 | ||
859 | /* | |
860 | * These should likewise go elsewhere. They pre-reserve the | |
861 | * screen memory region at the start of main system memory. | |
862 | */ | |
863 | if (machine_is_edb7211()) | |
864 | res_size = 0x00020000; | |
865 | if (machine_is_p720t()) | |
866 | res_size = 0x00014000; | |
867 | ||
bbf6f280 BD |
868 | /* H1940 and RX3715 need to reserve this for suspend */ |
869 | ||
870 | if (machine_is_h1940() || machine_is_rx3715()) { | |
72a7fe39 BW |
871 | reserve_bootmem_node(pgdat, 0x30003000, 0x1000, |
872 | BOOTMEM_DEFAULT); | |
873 | reserve_bootmem_node(pgdat, 0x30081000, 0x1000, | |
874 | BOOTMEM_DEFAULT); | |
9073341c BD |
875 | } |
876 | ||
81854f82 MV |
877 | if (machine_is_palmld() || machine_is_palmtx()) { |
878 | reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, | |
879 | BOOTMEM_EXCLUSIVE); | |
880 | reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, | |
881 | BOOTMEM_EXCLUSIVE); | |
882 | } | |
883 | ||
d0a92fd3 | 884 | if (machine_is_treo680() || machine_is_centro()) { |
e6c3f4b8 TSC |
885 | reserve_bootmem_node(pgdat, 0xa0000000, 0x1000, |
886 | BOOTMEM_EXCLUSIVE); | |
887 | reserve_bootmem_node(pgdat, 0xa2000000, 0x1000, | |
888 | BOOTMEM_EXCLUSIVE); | |
889 | } | |
890 | ||
81854f82 MV |
891 | if (machine_is_palmt5()) |
892 | reserve_bootmem_node(pgdat, 0xa0200000, 0x1000, | |
893 | BOOTMEM_EXCLUSIVE); | |
894 | ||
d98aac75 LW |
895 | /* |
896 | * U300 - This platform family can share physical memory | |
897 | * between two ARM cpus, one running Linux and the other | |
898 | * running another OS. | |
899 | */ | |
900 | if (machine_is_u300()) { | |
901 | #ifdef CONFIG_MACH_U300_SINGLE_RAM | |
902 | #if ((CONFIG_MACH_U300_ACCESS_MEM_SIZE & 1) == 1) && \ | |
903 | CONFIG_MACH_U300_2MB_ALIGNMENT_FIX | |
904 | res_size = 0x00100000; | |
905 | #endif | |
906 | #endif | |
907 | } | |
908 | ||
d111e8f9 RK |
909 | #ifdef CONFIG_SA1111 |
910 | /* | |
911 | * Because of the SA1111 DMA bug, we want to preserve our | |
912 | * precious DMA-able memory... | |
913 | */ | |
914 | res_size = __pa(swapper_pg_dir) - PHYS_OFFSET; | |
915 | #endif | |
916 | if (res_size) | |
72a7fe39 BW |
917 | reserve_bootmem_node(pgdat, PHYS_OFFSET, res_size, |
918 | BOOTMEM_DEFAULT); | |
d111e8f9 RK |
919 | } |
920 | ||
921 | /* | |
922 | * Set up device the mappings. Since we clear out the page tables for all | |
923 | * mappings above VMALLOC_END, we will remove any debug device mappings. | |
924 | * This means you have to be careful how you debug this function, or any | |
925 | * called function. This means you can't use any function or debugging | |
926 | * method which may touch any device, otherwise the kernel _will_ crash. | |
927 | */ | |
928 | static void __init devicemaps_init(struct machine_desc *mdesc) | |
929 | { | |
930 | struct map_desc map; | |
931 | unsigned long addr; | |
932 | void *vectors; | |
933 | ||
934 | /* | |
935 | * Allocate the vector page early. | |
936 | */ | |
937 | vectors = alloc_bootmem_low_pages(PAGE_SIZE); | |
d111e8f9 RK |
938 | |
939 | for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) | |
940 | pmd_clear(pmd_off_k(addr)); | |
941 | ||
942 | /* | |
943 | * Map the kernel if it is XIP. | |
944 | * It is always first in the modulearea. | |
945 | */ | |
946 | #ifdef CONFIG_XIP_KERNEL | |
947 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 948 | map.virtual = MODULES_VADDR; |
37efe642 | 949 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
950 | map.type = MT_ROM; |
951 | create_mapping(&map); | |
952 | #endif | |
953 | ||
954 | /* | |
955 | * Map the cache flushing regions. | |
956 | */ | |
957 | #ifdef FLUSH_BASE | |
958 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
959 | map.virtual = FLUSH_BASE; | |
960 | map.length = SZ_1M; | |
961 | map.type = MT_CACHECLEAN; | |
962 | create_mapping(&map); | |
963 | #endif | |
964 | #ifdef FLUSH_BASE_MINICACHE | |
965 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
966 | map.virtual = FLUSH_BASE_MINICACHE; | |
967 | map.length = SZ_1M; | |
968 | map.type = MT_MINICLEAN; | |
969 | create_mapping(&map); | |
970 | #endif | |
971 | ||
972 | /* | |
973 | * Create a mapping for the machine vectors at the high-vectors | |
974 | * location (0xffff0000). If we aren't using high-vectors, also | |
975 | * create a mapping at the low-vectors virtual address. | |
976 | */ | |
977 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); | |
978 | map.virtual = 0xffff0000; | |
979 | map.length = PAGE_SIZE; | |
980 | map.type = MT_HIGH_VECTORS; | |
981 | create_mapping(&map); | |
982 | ||
983 | if (!vectors_high()) { | |
984 | map.virtual = 0; | |
985 | map.type = MT_LOW_VECTORS; | |
986 | create_mapping(&map); | |
987 | } | |
988 | ||
989 | /* | |
990 | * Ask the machine support to map in the statically mapped devices. | |
991 | */ | |
992 | if (mdesc->map_io) | |
993 | mdesc->map_io(); | |
994 | ||
995 | /* | |
996 | * Finally flush the caches and tlb to ensure that we're in a | |
997 | * consistent state wrt the writebuffer. This also ensures that | |
998 | * any write-allocated cache lines in the vector page are written | |
999 | * back. After this point, we can start to touch devices again. | |
1000 | */ | |
1001 | local_flush_tlb_all(); | |
1002 | flush_cache_all(); | |
1003 | } | |
1004 | ||
d73cd428 NP |
1005 | static void __init kmap_init(void) |
1006 | { | |
1007 | #ifdef CONFIG_HIGHMEM | |
1008 | pmd_t *pmd = pmd_off_k(PKMAP_BASE); | |
1009 | pte_t *pte = alloc_bootmem_low_pages(2 * PTRS_PER_PTE * sizeof(pte_t)); | |
1010 | BUG_ON(!pmd_none(*pmd) || !pte); | |
1011 | __pmd_populate(pmd, __pa(pte) | _PAGE_KERNEL_TABLE); | |
1012 | pkmap_page_table = pte + PTRS_PER_PTE; | |
1013 | #endif | |
1014 | } | |
1015 | ||
d111e8f9 RK |
1016 | /* |
1017 | * paging_init() sets up the page tables, initialises the zone memory | |
1018 | * maps, and sets up the zero page, bad page and bad page tables. | |
1019 | */ | |
4b5f32ce | 1020 | void __init paging_init(struct machine_desc *mdesc) |
d111e8f9 RK |
1021 | { |
1022 | void *zero_page; | |
1023 | ||
1024 | build_mem_type_table(); | |
4b5f32ce NP |
1025 | sanity_check_meminfo(); |
1026 | prepare_page_table(); | |
1027 | bootmem_init(); | |
d111e8f9 | 1028 | devicemaps_init(mdesc); |
d73cd428 | 1029 | kmap_init(); |
d111e8f9 RK |
1030 | |
1031 | top_pmd = pmd_off_k(0xffff0000); | |
1032 | ||
1033 | /* | |
6ce1b871 JL |
1034 | * allocate the zero page. Note that this always succeeds and |
1035 | * returns a zeroed result. | |
d111e8f9 RK |
1036 | */ |
1037 | zero_page = alloc_bootmem_low_pages(PAGE_SIZE); | |
d111e8f9 | 1038 | empty_zero_page = virt_to_page(zero_page); |
421fe93c | 1039 | __flush_dcache_page(NULL, empty_zero_page); |
d111e8f9 | 1040 | } |
ae8f1541 RK |
1041 | |
1042 | /* | |
1043 | * In order to soft-boot, we need to insert a 1:1 mapping in place of | |
1044 | * the user-mode pages. This will then ensure that we have predictable | |
1045 | * results when turning the mmu off | |
1046 | */ | |
1047 | void setup_mm_for_reboot(char mode) | |
1048 | { | |
1049 | unsigned long base_pmdval; | |
1050 | pgd_t *pgd; | |
1051 | int i; | |
1052 | ||
1053 | if (current->mm && current->mm->pgd) | |
1054 | pgd = current->mm->pgd; | |
1055 | else | |
1056 | pgd = init_mm.pgd; | |
1057 | ||
1058 | base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; | |
1059 | if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) | |
1060 | base_pmdval |= PMD_BIT4; | |
1061 | ||
1062 | for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { | |
1063 | unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval; | |
1064 | pmd_t *pmd; | |
1065 | ||
1066 | pmd = pmd_off(pgd, i << PGDIR_SHIFT); | |
1067 | pmd[0] = __pmd(pmdval); | |
1068 | pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); | |
1069 | flush_pmd_entry(pmd); | |
1070 | } | |
ad3e6c0b TL |
1071 | |
1072 | local_flush_tlb_all(); | |
ae8f1541 | 1073 | } |