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d111e8f9 RK |
1 | /* |
2 | * linux/arch/arm/mm/mmu.c | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ae8f1541 | 10 | #include <linux/module.h> |
d111e8f9 RK |
11 | #include <linux/kernel.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/init.h> | |
d111e8f9 RK |
14 | #include <linux/mman.h> |
15 | #include <linux/nodemask.h> | |
2778f620 | 16 | #include <linux/memblock.h> |
d907387c | 17 | #include <linux/fs.h> |
0536bdf3 | 18 | #include <linux/vmalloc.h> |
158e8bfe | 19 | #include <linux/sizes.h> |
d111e8f9 | 20 | |
15d07dc9 | 21 | #include <asm/cp15.h> |
0ba8b9b2 | 22 | #include <asm/cputype.h> |
37efe642 | 23 | #include <asm/sections.h> |
3f973e22 | 24 | #include <asm/cachetype.h> |
d111e8f9 | 25 | #include <asm/setup.h> |
e616c591 | 26 | #include <asm/smp_plat.h> |
d111e8f9 | 27 | #include <asm/tlb.h> |
d73cd428 | 28 | #include <asm/highmem.h> |
9f97da78 | 29 | #include <asm/system_info.h> |
247055aa | 30 | #include <asm/traps.h> |
d111e8f9 RK |
31 | |
32 | #include <asm/mach/arch.h> | |
33 | #include <asm/mach/map.h> | |
c2794437 | 34 | #include <asm/mach/pci.h> |
d111e8f9 RK |
35 | |
36 | #include "mm.h" | |
37 | ||
d111e8f9 RK |
38 | /* |
39 | * empty_zero_page is a special page that is used for | |
40 | * zero-initialized data and COW. | |
41 | */ | |
42 | struct page *empty_zero_page; | |
3653f3ab | 43 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
44 | |
45 | /* | |
46 | * The pmd table for the upper-most set of pages. | |
47 | */ | |
48 | pmd_t *top_pmd; | |
49 | ||
ae8f1541 RK |
50 | #define CPOLICY_UNCACHED 0 |
51 | #define CPOLICY_BUFFERED 1 | |
52 | #define CPOLICY_WRITETHROUGH 2 | |
53 | #define CPOLICY_WRITEBACK 3 | |
54 | #define CPOLICY_WRITEALLOC 4 | |
55 | ||
56 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
57 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 58 | pgprot_t pgprot_user; |
ae8f1541 | 59 | pgprot_t pgprot_kernel; |
cc577c26 CD |
60 | pgprot_t pgprot_hyp_device; |
61 | pgprot_t pgprot_s2; | |
62 | pgprot_t pgprot_s2_device; | |
ae8f1541 | 63 | |
44b18693 | 64 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
65 | EXPORT_SYMBOL(pgprot_kernel); |
66 | ||
67 | struct cachepolicy { | |
68 | const char policy[16]; | |
69 | unsigned int cr_mask; | |
442e70c0 | 70 | pmdval_t pmd; |
f6e3354d | 71 | pteval_t pte; |
cc577c26 | 72 | pteval_t pte_s2; |
ae8f1541 RK |
73 | }; |
74 | ||
cc577c26 CD |
75 | #ifdef CONFIG_ARM_LPAE |
76 | #define s2_policy(policy) policy | |
77 | #else | |
78 | #define s2_policy(policy) 0 | |
79 | #endif | |
80 | ||
ae8f1541 RK |
81 | static struct cachepolicy cache_policies[] __initdata = { |
82 | { | |
83 | .policy = "uncached", | |
84 | .cr_mask = CR_W|CR_C, | |
85 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 86 | .pte = L_PTE_MT_UNCACHED, |
cc577c26 | 87 | .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), |
ae8f1541 RK |
88 | }, { |
89 | .policy = "buffered", | |
90 | .cr_mask = CR_C, | |
91 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 92 | .pte = L_PTE_MT_BUFFERABLE, |
cc577c26 | 93 | .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), |
ae8f1541 RK |
94 | }, { |
95 | .policy = "writethrough", | |
96 | .cr_mask = 0, | |
97 | .pmd = PMD_SECT_WT, | |
bb30f36f | 98 | .pte = L_PTE_MT_WRITETHROUGH, |
cc577c26 | 99 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH), |
ae8f1541 RK |
100 | }, { |
101 | .policy = "writeback", | |
102 | .cr_mask = 0, | |
103 | .pmd = PMD_SECT_WB, | |
bb30f36f | 104 | .pte = L_PTE_MT_WRITEBACK, |
cc577c26 | 105 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), |
ae8f1541 RK |
106 | }, { |
107 | .policy = "writealloc", | |
108 | .cr_mask = 0, | |
109 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 110 | .pte = L_PTE_MT_WRITEALLOC, |
cc577c26 | 111 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), |
ae8f1541 RK |
112 | } |
113 | }; | |
114 | ||
115 | /* | |
6cbdc8c5 | 116 | * These are useful for identifying cache coherency |
ae8f1541 RK |
117 | * problems by allowing the cache or the cache and |
118 | * writebuffer to be turned off. (Note: the write | |
119 | * buffer should not be on and the cache off). | |
120 | */ | |
2b0d8c25 | 121 | static int __init early_cachepolicy(char *p) |
ae8f1541 RK |
122 | { |
123 | int i; | |
124 | ||
125 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { | |
126 | int len = strlen(cache_policies[i].policy); | |
127 | ||
2b0d8c25 | 128 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ae8f1541 RK |
129 | cachepolicy = i; |
130 | cr_alignment &= ~cache_policies[i].cr_mask; | |
131 | cr_no_alignment &= ~cache_policies[i].cr_mask; | |
ae8f1541 RK |
132 | break; |
133 | } | |
134 | } | |
135 | if (i == ARRAY_SIZE(cache_policies)) | |
136 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); | |
4b46d641 RK |
137 | /* |
138 | * This restriction is partly to do with the way we boot; it is | |
139 | * unpredictable to have memory mapped using two different sets of | |
140 | * memory attributes (shared, type, and cache attribs). We can not | |
141 | * change these attributes once the initial assembly has setup the | |
142 | * page tables. | |
143 | */ | |
11179d8c CM |
144 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
145 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); | |
146 | cachepolicy = CPOLICY_WRITEBACK; | |
147 | } | |
ae8f1541 RK |
148 | flush_cache_all(); |
149 | set_cr(cr_alignment); | |
2b0d8c25 | 150 | return 0; |
ae8f1541 | 151 | } |
2b0d8c25 | 152 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 153 | |
2b0d8c25 | 154 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
155 | { |
156 | char *p = "buffered"; | |
157 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
158 | early_cachepolicy(p); |
159 | return 0; | |
ae8f1541 | 160 | } |
2b0d8c25 | 161 | early_param("nocache", early_nocache); |
ae8f1541 | 162 | |
2b0d8c25 | 163 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
164 | { |
165 | char *p = "uncached"; | |
166 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
167 | early_cachepolicy(p); |
168 | return 0; | |
ae8f1541 | 169 | } |
2b0d8c25 | 170 | early_param("nowb", early_nowrite); |
ae8f1541 | 171 | |
1b6ba46b | 172 | #ifndef CONFIG_ARM_LPAE |
2b0d8c25 | 173 | static int __init early_ecc(char *p) |
ae8f1541 | 174 | { |
2b0d8c25 | 175 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 176 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 177 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 178 | ecc_mask = 0; |
2b0d8c25 | 179 | return 0; |
ae8f1541 | 180 | } |
2b0d8c25 | 181 | early_param("ecc", early_ecc); |
1b6ba46b | 182 | #endif |
ae8f1541 RK |
183 | |
184 | static int __init noalign_setup(char *__unused) | |
185 | { | |
186 | cr_alignment &= ~CR_A; | |
187 | cr_no_alignment &= ~CR_A; | |
188 | set_cr(cr_alignment); | |
189 | return 1; | |
190 | } | |
191 | __setup("noalign", noalign_setup); | |
192 | ||
255d1f86 RK |
193 | #ifndef CONFIG_SMP |
194 | void adjust_cr(unsigned long mask, unsigned long set) | |
195 | { | |
196 | unsigned long flags; | |
197 | ||
198 | mask &= ~CR_A; | |
199 | ||
200 | set &= mask; | |
201 | ||
202 | local_irq_save(flags); | |
203 | ||
204 | cr_no_alignment = (cr_no_alignment & ~mask) | set; | |
205 | cr_alignment = (cr_alignment & ~mask) | set; | |
206 | ||
207 | set_cr((get_cr() & ~mask) | set); | |
208 | ||
209 | local_irq_restore(flags); | |
210 | } | |
211 | #endif | |
212 | ||
36bb94ba | 213 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
b1cce6b1 | 214 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 215 | |
b29e9f5e | 216 | static struct mem_type mem_types[] = { |
0af92bef | 217 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
218 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
219 | L_PTE_SHARED, | |
0af92bef | 220 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 221 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
222 | .domain = DOMAIN_IO, |
223 | }, | |
224 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 225 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 226 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 227 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
228 | .domain = DOMAIN_IO, |
229 | }, | |
230 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 231 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
232 | .prot_l1 = PMD_TYPE_TABLE, |
233 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
234 | .domain = DOMAIN_IO, | |
c2794437 | 235 | }, |
1ad77a87 | 236 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 237 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 238 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 239 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 240 | .domain = DOMAIN_IO, |
ae8f1541 | 241 | }, |
ebb4c658 RK |
242 | [MT_UNCACHED] = { |
243 | .prot_pte = PROT_PTE_DEVICE, | |
244 | .prot_l1 = PMD_TYPE_TABLE, | |
245 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
246 | .domain = DOMAIN_IO, | |
247 | }, | |
ae8f1541 | 248 | [MT_CACHECLEAN] = { |
9ef79635 | 249 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
250 | .domain = DOMAIN_KERNEL, |
251 | }, | |
1b6ba46b | 252 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 | 253 | [MT_MINICLEAN] = { |
9ef79635 | 254 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
255 | .domain = DOMAIN_KERNEL, |
256 | }, | |
1b6ba46b | 257 | #endif |
ae8f1541 RK |
258 | [MT_LOW_VECTORS] = { |
259 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 260 | L_PTE_RDONLY, |
ae8f1541 RK |
261 | .prot_l1 = PMD_TYPE_TABLE, |
262 | .domain = DOMAIN_USER, | |
263 | }, | |
264 | [MT_HIGH_VECTORS] = { | |
265 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 266 | L_PTE_USER | L_PTE_RDONLY, |
ae8f1541 RK |
267 | .prot_l1 = PMD_TYPE_TABLE, |
268 | .domain = DOMAIN_USER, | |
269 | }, | |
270 | [MT_MEMORY] = { | |
36bb94ba | 271 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
f1a2481c | 272 | .prot_l1 = PMD_TYPE_TABLE, |
9ef79635 | 273 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
274 | .domain = DOMAIN_KERNEL, |
275 | }, | |
276 | [MT_ROM] = { | |
9ef79635 | 277 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
278 | .domain = DOMAIN_KERNEL, |
279 | }, | |
e4707dd3 | 280 | [MT_MEMORY_NONCACHED] = { |
f1a2481c | 281 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 282 | L_PTE_MT_BUFFERABLE, |
f1a2481c | 283 | .prot_l1 = PMD_TYPE_TABLE, |
e4707dd3 PW |
284 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
285 | .domain = DOMAIN_KERNEL, | |
286 | }, | |
cb9d7707 | 287 | [MT_MEMORY_DTCM] = { |
f444fce3 | 288 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 289 | L_PTE_XN, |
f444fce3 LW |
290 | .prot_l1 = PMD_TYPE_TABLE, |
291 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
292 | .domain = DOMAIN_KERNEL, | |
cb9d7707 LW |
293 | }, |
294 | [MT_MEMORY_ITCM] = { | |
36bb94ba | 295 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
cb9d7707 | 296 | .prot_l1 = PMD_TYPE_TABLE, |
f444fce3 | 297 | .domain = DOMAIN_KERNEL, |
cb9d7707 | 298 | }, |
8fb54284 SS |
299 | [MT_MEMORY_SO] = { |
300 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
93d5bf07 | 301 | L_PTE_MT_UNCACHED | L_PTE_XN, |
8fb54284 SS |
302 | .prot_l1 = PMD_TYPE_TABLE, |
303 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | | |
304 | PMD_SECT_UNCACHED | PMD_SECT_XN, | |
305 | .domain = DOMAIN_KERNEL, | |
306 | }, | |
c7909509 MS |
307 | [MT_MEMORY_DMA_READY] = { |
308 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, | |
309 | .prot_l1 = PMD_TYPE_TABLE, | |
310 | .domain = DOMAIN_KERNEL, | |
311 | }, | |
ae8f1541 RK |
312 | }; |
313 | ||
b29e9f5e RK |
314 | const struct mem_type *get_mem_type(unsigned int type) |
315 | { | |
316 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
317 | } | |
69d3a84a | 318 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 319 | |
ae8f1541 RK |
320 | /* |
321 | * Adjust the PMD section entries according to the CPU in use. | |
322 | */ | |
323 | static void __init build_mem_type_table(void) | |
324 | { | |
325 | struct cachepolicy *cp; | |
326 | unsigned int cr = get_cr(); | |
442e70c0 | 327 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
cc577c26 | 328 | pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot; |
ae8f1541 RK |
329 | int cpu_arch = cpu_architecture(); |
330 | int i; | |
331 | ||
11179d8c | 332 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 333 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
334 | if (cachepolicy > CPOLICY_BUFFERED) |
335 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 336 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
337 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
338 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 339 | #endif |
11179d8c | 340 | } |
ae8f1541 RK |
341 | if (cpu_arch < CPU_ARCH_ARMv5) { |
342 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
343 | cachepolicy = CPOLICY_WRITEBACK; | |
344 | ecc_mask = 0; | |
345 | } | |
f00ec48f RK |
346 | if (is_smp()) |
347 | cachepolicy = CPOLICY_WRITEALLOC; | |
ae8f1541 | 348 | |
1ad77a87 | 349 | /* |
b1cce6b1 RK |
350 | * Strip out features not present on earlier architectures. |
351 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
352 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 353 | */ |
b1cce6b1 RK |
354 | if (cpu_arch < CPU_ARCH_ARMv5) |
355 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
356 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
357 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
358 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
359 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
360 | |
361 | /* | |
b1cce6b1 RK |
362 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
363 | * "update-able on write" bit on ARM610). However, Xscale and | |
364 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 365 | */ |
b1cce6b1 | 366 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
9ef79635 | 367 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 368 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
369 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
370 | } | |
371 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
372 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
373 | if (mem_types[i].prot_l1) |
374 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
375 | if (mem_types[i].prot_sect) |
376 | mem_types[i].prot_sect |= PMD_BIT4; | |
377 | } | |
378 | } | |
ae8f1541 | 379 | |
b1cce6b1 RK |
380 | /* |
381 | * Mark the device areas according to the CPU/architecture. | |
382 | */ | |
383 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
384 | if (!cpu_is_xsc3()) { | |
385 | /* | |
386 | * Mark device regions on ARMv6+ as execute-never | |
387 | * to prevent speculative instruction fetches. | |
388 | */ | |
389 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
390 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
391 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
392 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
393 | } | |
394 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
395 | /* | |
396 | * For ARMv7 with TEX remapping, | |
397 | * - shared device is SXCB=1100 | |
398 | * - nonshared device is SXCB=0100 | |
399 | * - write combine device mem is SXCB=0001 | |
400 | * (Uncached Normal memory) | |
401 | */ | |
402 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
403 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
404 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
405 | } else if (cpu_is_xsc3()) { | |
406 | /* | |
407 | * For Xscale3, | |
408 | * - shared device is TEXCB=00101 | |
409 | * - nonshared device is TEXCB=01000 | |
410 | * - write combine device mem is TEXCB=00100 | |
411 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
412 | */ | |
413 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
414 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
415 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
416 | } else { | |
417 | /* | |
418 | * For ARMv6 and ARMv7 without TEX remapping, | |
419 | * - shared device is TEXCB=00001 | |
420 | * - nonshared device is TEXCB=01000 | |
421 | * - write combine device mem is TEXCB=00100 | |
422 | * (Uncached Normal in ARMv6 parlance). | |
423 | */ | |
424 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
425 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
426 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
427 | } | |
428 | } else { | |
429 | /* | |
430 | * On others, write combining is "Uncached/Buffered" | |
431 | */ | |
432 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
433 | } | |
434 | ||
435 | /* | |
436 | * Now deal with the memory-type mappings | |
437 | */ | |
ae8f1541 | 438 | cp = &cache_policies[cachepolicy]; |
bb30f36f | 439 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
cc577c26 CD |
440 | s2_pgprot = cp->pte_s2; |
441 | hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte; | |
bb30f36f | 442 | |
ae8f1541 RK |
443 | /* |
444 | * ARMv6 and above have extended page tables. | |
445 | */ | |
446 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
1b6ba46b | 447 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
448 | /* |
449 | * Mark cache clean areas and XIP ROM read only | |
450 | * from SVC mode and no access from userspace. | |
451 | */ | |
452 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
453 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
454 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
1b6ba46b | 455 | #endif |
ae8f1541 | 456 | |
f00ec48f RK |
457 | if (is_smp()) { |
458 | /* | |
459 | * Mark memory with the "shared" attribute | |
460 | * for SMP systems | |
461 | */ | |
462 | user_pgprot |= L_PTE_SHARED; | |
463 | kern_pgprot |= L_PTE_SHARED; | |
464 | vecs_pgprot |= L_PTE_SHARED; | |
cc577c26 | 465 | s2_pgprot |= L_PTE_SHARED; |
f00ec48f RK |
466 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; |
467 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; | |
468 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; | |
469 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; | |
470 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; | |
471 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; | |
c7909509 | 472 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
f00ec48f RK |
473 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; |
474 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
475 | } | |
ae8f1541 RK |
476 | } |
477 | ||
e4707dd3 PW |
478 | /* |
479 | * Non-cacheable Normal - intended for memory areas that must | |
480 | * not cause dirty cache line writebacks when used | |
481 | */ | |
482 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
483 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
484 | /* Non-cacheable Normal is XCB = 001 */ | |
485 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
486 | PMD_SECT_BUFFERED; | |
487 | } else { | |
488 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
489 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
490 | PMD_SECT_TEX(1); | |
491 | } | |
492 | } else { | |
493 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; | |
494 | } | |
495 | ||
1b6ba46b CM |
496 | #ifdef CONFIG_ARM_LPAE |
497 | /* | |
498 | * Do not generate access flag faults for the kernel mappings. | |
499 | */ | |
500 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
501 | mem_types[i].prot_pte |= PTE_EXT_AF; | |
1a3abcf4 VA |
502 | if (mem_types[i].prot_sect) |
503 | mem_types[i].prot_sect |= PMD_SECT_AF; | |
1b6ba46b CM |
504 | } |
505 | kern_pgprot |= PTE_EXT_AF; | |
506 | vecs_pgprot |= PTE_EXT_AF; | |
507 | #endif | |
508 | ||
ae8f1541 | 509 | for (i = 0; i < 16; i++) { |
864aa04c | 510 | pteval_t v = pgprot_val(protection_map[i]); |
bb30f36f | 511 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
512 | } |
513 | ||
bb30f36f RK |
514 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
515 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 516 | |
44b18693 | 517 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 518 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
36bb94ba | 519 | L_PTE_DIRTY | kern_pgprot); |
cc577c26 CD |
520 | pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot); |
521 | pgprot_s2_device = __pgprot(s2_device_pgprot); | |
522 | pgprot_hyp_device = __pgprot(hyp_device_pgprot); | |
ae8f1541 RK |
523 | |
524 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
525 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
526 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; | |
f1a2481c | 527 | mem_types[MT_MEMORY].prot_pte |= kern_pgprot; |
c7909509 | 528 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; |
f1a2481c | 529 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; |
ae8f1541 RK |
530 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
531 | ||
532 | switch (cp->pmd) { | |
533 | case PMD_SECT_WT: | |
534 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
535 | break; | |
536 | case PMD_SECT_WB: | |
537 | case PMD_SECT_WBWA: | |
538 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
539 | break; | |
540 | } | |
541 | printk("Memory policy: ECC %sabled, Data cache %s\n", | |
542 | ecc_mask ? "en" : "dis", cp->policy); | |
2497f0a8 RK |
543 | |
544 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
545 | struct mem_type *t = &mem_types[i]; | |
546 | if (t->prot_l1) | |
547 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
548 | if (t->prot_sect) | |
549 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
550 | } | |
ae8f1541 RK |
551 | } |
552 | ||
d907387c CM |
553 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
554 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
555 | unsigned long size, pgprot_t vma_prot) | |
556 | { | |
557 | if (!pfn_valid(pfn)) | |
558 | return pgprot_noncached(vma_prot); | |
559 | else if (file->f_flags & O_SYNC) | |
560 | return pgprot_writecombine(vma_prot); | |
561 | return vma_prot; | |
562 | } | |
563 | EXPORT_SYMBOL(phys_mem_access_prot); | |
564 | #endif | |
565 | ||
ae8f1541 RK |
566 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
567 | ||
0536bdf3 | 568 | static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) |
3abe9d33 | 569 | { |
0536bdf3 | 570 | void *ptr = __va(memblock_alloc(sz, align)); |
2778f620 RK |
571 | memset(ptr, 0, sz); |
572 | return ptr; | |
3abe9d33 RK |
573 | } |
574 | ||
0536bdf3 NP |
575 | static void __init *early_alloc(unsigned long sz) |
576 | { | |
577 | return early_alloc_aligned(sz, sz); | |
578 | } | |
579 | ||
4bb2e27d | 580 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) |
ae8f1541 | 581 | { |
24e6c699 | 582 | if (pmd_none(*pmd)) { |
410f1483 | 583 | pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
97092e0c | 584 | __pmd_populate(pmd, __pa(pte), prot); |
24e6c699 | 585 | } |
4bb2e27d RK |
586 | BUG_ON(pmd_bad(*pmd)); |
587 | return pte_offset_kernel(pmd, addr); | |
588 | } | |
ae8f1541 | 589 | |
4bb2e27d RK |
590 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
591 | unsigned long end, unsigned long pfn, | |
592 | const struct mem_type *type) | |
593 | { | |
594 | pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); | |
24e6c699 | 595 | do { |
40d192b6 | 596 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
24e6c699 RK |
597 | pfn++; |
598 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
599 | } |
600 | ||
516295e5 | 601 | static void __init alloc_init_section(pud_t *pud, unsigned long addr, |
97092e0c | 602 | unsigned long end, phys_addr_t phys, |
24e6c699 | 603 | const struct mem_type *type) |
ae8f1541 | 604 | { |
516295e5 | 605 | pmd_t *pmd = pmd_offset(pud, addr); |
ae8f1541 | 606 | |
24e6c699 RK |
607 | /* |
608 | * Try a section mapping - end, addr and phys must all be aligned | |
609 | * to a section boundary. Note that PMDs refer to the individual | |
610 | * L1 entries, whereas PGDs refer to a group of L1 entries making | |
611 | * up one logical pointer to an L2 table. | |
612 | */ | |
c7909509 | 613 | if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) { |
24e6c699 | 614 | pmd_t *p = pmd; |
ae8f1541 | 615 | |
1b6ba46b | 616 | #ifndef CONFIG_ARM_LPAE |
24e6c699 RK |
617 | if (addr & SECTION_SIZE) |
618 | pmd++; | |
1b6ba46b | 619 | #endif |
24e6c699 RK |
620 | |
621 | do { | |
622 | *pmd = __pmd(phys | type->prot_sect); | |
623 | phys += SECTION_SIZE; | |
624 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
ae8f1541 | 625 | |
24e6c699 RK |
626 | flush_pmd_entry(p); |
627 | } else { | |
628 | /* | |
629 | * No need to loop; pte's aren't interested in the | |
630 | * individual L1 entries. | |
631 | */ | |
632 | alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); | |
633 | } | |
ae8f1541 RK |
634 | } |
635 | ||
14904927 SB |
636 | static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, |
637 | unsigned long end, unsigned long phys, const struct mem_type *type) | |
516295e5 RK |
638 | { |
639 | pud_t *pud = pud_offset(pgd, addr); | |
640 | unsigned long next; | |
641 | ||
642 | do { | |
643 | next = pud_addr_end(addr, end); | |
644 | alloc_init_section(pud, addr, next, phys, type); | |
645 | phys += next - addr; | |
646 | } while (pud++, addr = next, addr != end); | |
647 | } | |
648 | ||
1b6ba46b | 649 | #ifndef CONFIG_ARM_LPAE |
4a56c1e4 RK |
650 | static void __init create_36bit_mapping(struct map_desc *md, |
651 | const struct mem_type *type) | |
652 | { | |
97092e0c RK |
653 | unsigned long addr, length, end; |
654 | phys_addr_t phys; | |
4a56c1e4 RK |
655 | pgd_t *pgd; |
656 | ||
657 | addr = md->virtual; | |
cae6292b | 658 | phys = __pfn_to_phys(md->pfn); |
4a56c1e4 RK |
659 | length = PAGE_ALIGN(md->length); |
660 | ||
661 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
662 | printk(KERN_ERR "MM: CPU does not support supersection " | |
663 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 664 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
665 | return; |
666 | } | |
667 | ||
668 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
669 | * Since domain assignments can in fact be arbitrary, the | |
670 | * 'domain == 0' check below is required to insure that ARMv6 | |
671 | * supersections are only allocated for domain 0 regardless | |
672 | * of the actual domain assignments in use. | |
673 | */ | |
674 | if (type->domain) { | |
675 | printk(KERN_ERR "MM: invalid domain in supersection " | |
676 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 677 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
678 | return; |
679 | } | |
680 | ||
681 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
29a38193 WD |
682 | printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" |
683 | " at 0x%08lx invalid alignment\n", | |
684 | (long long)__pfn_to_phys((u64)md->pfn), addr); | |
4a56c1e4 RK |
685 | return; |
686 | } | |
687 | ||
688 | /* | |
689 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
690 | * (See ARMv6 spec). | |
691 | */ | |
692 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
693 | ||
694 | pgd = pgd_offset_k(addr); | |
695 | end = addr + length; | |
696 | do { | |
516295e5 RK |
697 | pud_t *pud = pud_offset(pgd, addr); |
698 | pmd_t *pmd = pmd_offset(pud, addr); | |
4a56c1e4 RK |
699 | int i; |
700 | ||
701 | for (i = 0; i < 16; i++) | |
702 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); | |
703 | ||
704 | addr += SUPERSECTION_SIZE; | |
705 | phys += SUPERSECTION_SIZE; | |
706 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
707 | } while (addr != end); | |
708 | } | |
1b6ba46b | 709 | #endif /* !CONFIG_ARM_LPAE */ |
4a56c1e4 | 710 | |
ae8f1541 RK |
711 | /* |
712 | * Create the page directory entries and any necessary | |
713 | * page tables for the mapping specified by `md'. We | |
714 | * are able to cope here with varying sizes and address | |
715 | * offsets, and we take full advantage of sections and | |
716 | * supersections. | |
717 | */ | |
a2227120 | 718 | static void __init create_mapping(struct map_desc *md) |
ae8f1541 | 719 | { |
cae6292b WD |
720 | unsigned long addr, length, end; |
721 | phys_addr_t phys; | |
d5c98176 | 722 | const struct mem_type *type; |
24e6c699 | 723 | pgd_t *pgd; |
ae8f1541 RK |
724 | |
725 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
29a38193 WD |
726 | printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" |
727 | " at 0x%08lx in user region\n", | |
728 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
ae8f1541 RK |
729 | return; |
730 | } | |
731 | ||
732 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
0536bdf3 NP |
733 | md->virtual >= PAGE_OFFSET && |
734 | (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { | |
29a38193 | 735 | printk(KERN_WARNING "BUG: mapping for 0x%08llx" |
0536bdf3 | 736 | " at 0x%08lx out of vmalloc space\n", |
29a38193 | 737 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); |
ae8f1541 RK |
738 | } |
739 | ||
d5c98176 | 740 | type = &mem_types[md->type]; |
ae8f1541 | 741 | |
1b6ba46b | 742 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
743 | /* |
744 | * Catch 36-bit addresses | |
745 | */ | |
4a56c1e4 RK |
746 | if (md->pfn >= 0x100000) { |
747 | create_36bit_mapping(md, type); | |
748 | return; | |
ae8f1541 | 749 | } |
1b6ba46b | 750 | #endif |
ae8f1541 | 751 | |
7b9c7b4d | 752 | addr = md->virtual & PAGE_MASK; |
cae6292b | 753 | phys = __pfn_to_phys(md->pfn); |
7b9c7b4d | 754 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 755 | |
24e6c699 | 756 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
29a38193 | 757 | printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " |
ae8f1541 | 758 | "be mapped using pages, ignoring.\n", |
29a38193 | 759 | (long long)__pfn_to_phys(md->pfn), addr); |
ae8f1541 RK |
760 | return; |
761 | } | |
762 | ||
24e6c699 RK |
763 | pgd = pgd_offset_k(addr); |
764 | end = addr + length; | |
765 | do { | |
766 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 767 | |
516295e5 | 768 | alloc_init_pud(pgd, addr, next, phys, type); |
ae8f1541 | 769 | |
24e6c699 RK |
770 | phys += next - addr; |
771 | addr = next; | |
772 | } while (pgd++, addr != end); | |
ae8f1541 RK |
773 | } |
774 | ||
775 | /* | |
776 | * Create the architecture specific mappings | |
777 | */ | |
778 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
779 | { | |
0536bdf3 NP |
780 | struct map_desc *md; |
781 | struct vm_struct *vm; | |
101eeda3 | 782 | struct static_vm *svm; |
0536bdf3 NP |
783 | |
784 | if (!nr) | |
785 | return; | |
ae8f1541 | 786 | |
101eeda3 | 787 | svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm)); |
0536bdf3 NP |
788 | |
789 | for (md = io_desc; nr; md++, nr--) { | |
790 | create_mapping(md); | |
101eeda3 JK |
791 | |
792 | vm = &svm->vm; | |
0536bdf3 NP |
793 | vm->addr = (void *)(md->virtual & PAGE_MASK); |
794 | vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); | |
c2794437 RH |
795 | vm->phys_addr = __pfn_to_phys(md->pfn); |
796 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; | |
576d2f25 | 797 | vm->flags |= VM_ARM_MTYPE(md->type); |
0536bdf3 | 798 | vm->caller = iotable_init; |
101eeda3 | 799 | add_static_vm_early(svm++); |
0536bdf3 | 800 | } |
ae8f1541 RK |
801 | } |
802 | ||
c2794437 RH |
803 | void __init vm_reserve_area_early(unsigned long addr, unsigned long size, |
804 | void *caller) | |
805 | { | |
806 | struct vm_struct *vm; | |
101eeda3 JK |
807 | struct static_vm *svm; |
808 | ||
809 | svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm)); | |
c2794437 | 810 | |
101eeda3 | 811 | vm = &svm->vm; |
c2794437 RH |
812 | vm->addr = (void *)addr; |
813 | vm->size = size; | |
863e99a8 | 814 | vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; |
c2794437 | 815 | vm->caller = caller; |
101eeda3 | 816 | add_static_vm_early(svm); |
c2794437 RH |
817 | } |
818 | ||
19b52abe NP |
819 | #ifndef CONFIG_ARM_LPAE |
820 | ||
821 | /* | |
822 | * The Linux PMD is made of two consecutive section entries covering 2MB | |
823 | * (see definition in include/asm/pgtable-2level.h). However a call to | |
824 | * create_mapping() may optimize static mappings by using individual | |
825 | * 1MB section mappings. This leaves the actual PMD potentially half | |
826 | * initialized if the top or bottom section entry isn't used, leaving it | |
827 | * open to problems if a subsequent ioremap() or vmalloc() tries to use | |
828 | * the virtual space left free by that unused section entry. | |
829 | * | |
830 | * Let's avoid the issue by inserting dummy vm entries covering the unused | |
831 | * PMD halves once the static mappings are in place. | |
832 | */ | |
833 | ||
834 | static void __init pmd_empty_section_gap(unsigned long addr) | |
835 | { | |
c2794437 | 836 | vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); |
19b52abe NP |
837 | } |
838 | ||
839 | static void __init fill_pmd_gaps(void) | |
840 | { | |
101eeda3 | 841 | struct static_vm *svm; |
19b52abe NP |
842 | struct vm_struct *vm; |
843 | unsigned long addr, next = 0; | |
844 | pmd_t *pmd; | |
845 | ||
101eeda3 JK |
846 | list_for_each_entry(svm, &static_vmlist, list) { |
847 | vm = &svm->vm; | |
19b52abe NP |
848 | addr = (unsigned long)vm->addr; |
849 | if (addr < next) | |
850 | continue; | |
851 | ||
852 | /* | |
853 | * Check if this vm starts on an odd section boundary. | |
854 | * If so and the first section entry for this PMD is free | |
855 | * then we block the corresponding virtual address. | |
856 | */ | |
857 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
858 | pmd = pmd_off_k(addr); | |
859 | if (pmd_none(*pmd)) | |
860 | pmd_empty_section_gap(addr & PMD_MASK); | |
861 | } | |
862 | ||
863 | /* | |
864 | * Then check if this vm ends on an odd section boundary. | |
865 | * If so and the second section entry for this PMD is empty | |
866 | * then we block the corresponding virtual address. | |
867 | */ | |
868 | addr += vm->size; | |
869 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
870 | pmd = pmd_off_k(addr) + 1; | |
871 | if (pmd_none(*pmd)) | |
872 | pmd_empty_section_gap(addr); | |
873 | } | |
874 | ||
875 | /* no need to look at any vm entry until we hit the next PMD */ | |
876 | next = (addr + PMD_SIZE - 1) & PMD_MASK; | |
877 | } | |
878 | } | |
879 | ||
880 | #else | |
881 | #define fill_pmd_gaps() do { } while (0) | |
882 | #endif | |
883 | ||
c2794437 RH |
884 | #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) |
885 | static void __init pci_reserve_io(void) | |
886 | { | |
101eeda3 | 887 | struct static_vm *svm; |
c2794437 | 888 | |
101eeda3 JK |
889 | svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); |
890 | if (svm) | |
891 | return; | |
c2794437 | 892 | |
c2794437 RH |
893 | vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); |
894 | } | |
895 | #else | |
896 | #define pci_reserve_io() do { } while (0) | |
897 | #endif | |
898 | ||
e5c5f2ad RH |
899 | #ifdef CONFIG_DEBUG_LL |
900 | void __init debug_ll_io_init(void) | |
901 | { | |
902 | struct map_desc map; | |
903 | ||
904 | debug_ll_addr(&map.pfn, &map.virtual); | |
905 | if (!map.pfn || !map.virtual) | |
906 | return; | |
907 | map.pfn = __phys_to_pfn(map.pfn); | |
908 | map.virtual &= PAGE_MASK; | |
909 | map.length = PAGE_SIZE; | |
910 | map.type = MT_DEVICE; | |
911 | create_mapping(&map); | |
912 | } | |
913 | #endif | |
914 | ||
0536bdf3 NP |
915 | static void * __initdata vmalloc_min = |
916 | (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); | |
6c5da7ac RK |
917 | |
918 | /* | |
919 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
920 | * bytes. This can be used to increase (or decrease) the vmalloc | |
0536bdf3 | 921 | * area - the default is 240m. |
6c5da7ac | 922 | */ |
2b0d8c25 | 923 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 924 | { |
79612395 | 925 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
6c5da7ac RK |
926 | |
927 | if (vmalloc_reserve < SZ_16M) { | |
928 | vmalloc_reserve = SZ_16M; | |
929 | printk(KERN_WARNING | |
930 | "vmalloc area too small, limiting to %luMB\n", | |
931 | vmalloc_reserve >> 20); | |
932 | } | |
9210807c NP |
933 | |
934 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { | |
935 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); | |
936 | printk(KERN_WARNING | |
937 | "vmalloc area is too big, limiting to %luMB\n", | |
938 | vmalloc_reserve >> 20); | |
939 | } | |
79612395 RK |
940 | |
941 | vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); | |
2b0d8c25 | 942 | return 0; |
6c5da7ac | 943 | } |
2b0d8c25 | 944 | early_param("vmalloc", early_vmalloc); |
6c5da7ac | 945 | |
c7909509 | 946 | phys_addr_t arm_lowmem_limit __initdata = 0; |
8df65168 | 947 | |
0371d3f7 | 948 | void __init sanity_check_meminfo(void) |
60296c71 | 949 | { |
dde5828f | 950 | int i, j, highmem = 0; |
60296c71 | 951 | |
4b5f32ce | 952 | for (i = 0, j = 0; i < meminfo.nr_banks; i++) { |
a1bbaec0 NP |
953 | struct membank *bank = &meminfo.bank[j]; |
954 | *bank = meminfo.bank[i]; | |
60296c71 | 955 | |
77f73a2c WD |
956 | if (bank->start > ULONG_MAX) |
957 | highmem = 1; | |
958 | ||
a1bbaec0 | 959 | #ifdef CONFIG_HIGHMEM |
40f7bfe4 | 960 | if (__va(bank->start) >= vmalloc_min || |
dde5828f RK |
961 | __va(bank->start) < (void *)PAGE_OFFSET) |
962 | highmem = 1; | |
963 | ||
964 | bank->highmem = highmem; | |
965 | ||
a1bbaec0 NP |
966 | /* |
967 | * Split those memory banks which are partially overlapping | |
968 | * the vmalloc area greatly simplifying things later. | |
969 | */ | |
77f73a2c | 970 | if (!highmem && __va(bank->start) < vmalloc_min && |
79612395 | 971 | bank->size > vmalloc_min - __va(bank->start)) { |
a1bbaec0 NP |
972 | if (meminfo.nr_banks >= NR_BANKS) { |
973 | printk(KERN_CRIT "NR_BANKS too low, " | |
974 | "ignoring high memory\n"); | |
975 | } else { | |
976 | memmove(bank + 1, bank, | |
977 | (meminfo.nr_banks - i) * sizeof(*bank)); | |
978 | meminfo.nr_banks++; | |
979 | i++; | |
79612395 RK |
980 | bank[1].size -= vmalloc_min - __va(bank->start); |
981 | bank[1].start = __pa(vmalloc_min - 1) + 1; | |
dde5828f | 982 | bank[1].highmem = highmem = 1; |
a1bbaec0 NP |
983 | j++; |
984 | } | |
79612395 | 985 | bank->size = vmalloc_min - __va(bank->start); |
a1bbaec0 NP |
986 | } |
987 | #else | |
041d785f RK |
988 | bank->highmem = highmem; |
989 | ||
77f73a2c WD |
990 | /* |
991 | * Highmem banks not allowed with !CONFIG_HIGHMEM. | |
992 | */ | |
993 | if (highmem) { | |
994 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " | |
995 | "(!CONFIG_HIGHMEM).\n", | |
996 | (unsigned long long)bank->start, | |
997 | (unsigned long long)bank->start + bank->size - 1); | |
998 | continue; | |
999 | } | |
1000 | ||
a1bbaec0 NP |
1001 | /* |
1002 | * Check whether this memory bank would entirely overlap | |
1003 | * the vmalloc area. | |
1004 | */ | |
79612395 | 1005 | if (__va(bank->start) >= vmalloc_min || |
f0bba9f9 | 1006 | __va(bank->start) < (void *)PAGE_OFFSET) { |
e33b9d08 | 1007 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " |
a1bbaec0 | 1008 | "(vmalloc region overlap).\n", |
e33b9d08 RK |
1009 | (unsigned long long)bank->start, |
1010 | (unsigned long long)bank->start + bank->size - 1); | |
a1bbaec0 NP |
1011 | continue; |
1012 | } | |
60296c71 | 1013 | |
a1bbaec0 NP |
1014 | /* |
1015 | * Check whether this memory bank would partially overlap | |
1016 | * the vmalloc area. | |
1017 | */ | |
36418c51 JA |
1018 | if (__va(bank->start + bank->size - 1) >= vmalloc_min || |
1019 | __va(bank->start + bank->size - 1) <= __va(bank->start)) { | |
79612395 | 1020 | unsigned long newsize = vmalloc_min - __va(bank->start); |
e33b9d08 RK |
1021 | printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " |
1022 | "to -%.8llx (vmalloc region overlap).\n", | |
1023 | (unsigned long long)bank->start, | |
1024 | (unsigned long long)bank->start + bank->size - 1, | |
1025 | (unsigned long long)bank->start + newsize - 1); | |
a1bbaec0 NP |
1026 | bank->size = newsize; |
1027 | } | |
1028 | #endif | |
c7909509 MS |
1029 | if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit) |
1030 | arm_lowmem_limit = bank->start + bank->size; | |
40f7bfe4 | 1031 | |
a1bbaec0 | 1032 | j++; |
60296c71 | 1033 | } |
e616c591 RK |
1034 | #ifdef CONFIG_HIGHMEM |
1035 | if (highmem) { | |
1036 | const char *reason = NULL; | |
1037 | ||
1038 | if (cache_is_vipt_aliasing()) { | |
1039 | /* | |
1040 | * Interactions between kmap and other mappings | |
1041 | * make highmem support with aliasing VIPT caches | |
1042 | * rather difficult. | |
1043 | */ | |
1044 | reason = "with VIPT aliasing cache"; | |
e616c591 RK |
1045 | } |
1046 | if (reason) { | |
1047 | printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", | |
1048 | reason); | |
1049 | while (j > 0 && meminfo.bank[j - 1].highmem) | |
1050 | j--; | |
1051 | } | |
1052 | } | |
1053 | #endif | |
4b5f32ce | 1054 | meminfo.nr_banks = j; |
c7909509 MS |
1055 | high_memory = __va(arm_lowmem_limit - 1) + 1; |
1056 | memblock_set_current_limit(arm_lowmem_limit); | |
60296c71 LB |
1057 | } |
1058 | ||
4b5f32ce | 1059 | static inline void prepare_page_table(void) |
d111e8f9 RK |
1060 | { |
1061 | unsigned long addr; | |
8df65168 | 1062 | phys_addr_t end; |
d111e8f9 RK |
1063 | |
1064 | /* | |
1065 | * Clear out all the mappings below the kernel image. | |
1066 | */ | |
e73fc88e | 1067 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
d111e8f9 RK |
1068 | pmd_clear(pmd_off_k(addr)); |
1069 | ||
1070 | #ifdef CONFIG_XIP_KERNEL | |
1071 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
e73fc88e | 1072 | addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; |
d111e8f9 | 1073 | #endif |
e73fc88e | 1074 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
d111e8f9 RK |
1075 | pmd_clear(pmd_off_k(addr)); |
1076 | ||
8df65168 RK |
1077 | /* |
1078 | * Find the end of the first block of lowmem. | |
1079 | */ | |
1080 | end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; | |
c7909509 MS |
1081 | if (end >= arm_lowmem_limit) |
1082 | end = arm_lowmem_limit; | |
8df65168 | 1083 | |
d111e8f9 RK |
1084 | /* |
1085 | * Clear out all the kernel space mappings, except for the first | |
0536bdf3 | 1086 | * memory bank, up to the vmalloc region. |
d111e8f9 | 1087 | */ |
8df65168 | 1088 | for (addr = __phys_to_virt(end); |
0536bdf3 | 1089 | addr < VMALLOC_START; addr += PMD_SIZE) |
d111e8f9 RK |
1090 | pmd_clear(pmd_off_k(addr)); |
1091 | } | |
1092 | ||
1b6ba46b CM |
1093 | #ifdef CONFIG_ARM_LPAE |
1094 | /* the first page is reserved for pgd */ | |
1095 | #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ | |
1096 | PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) | |
1097 | #else | |
e73fc88e | 1098 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
1b6ba46b | 1099 | #endif |
e73fc88e | 1100 | |
d111e8f9 | 1101 | /* |
2778f620 | 1102 | * Reserve the special regions of memory |
d111e8f9 | 1103 | */ |
2778f620 | 1104 | void __init arm_mm_memblock_reserve(void) |
d111e8f9 | 1105 | { |
d111e8f9 RK |
1106 | /* |
1107 | * Reserve the page tables. These are already in use, | |
1108 | * and can only be in node 0. | |
1109 | */ | |
e73fc88e | 1110 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
d111e8f9 | 1111 | |
d111e8f9 RK |
1112 | #ifdef CONFIG_SA1111 |
1113 | /* | |
1114 | * Because of the SA1111 DMA bug, we want to preserve our | |
1115 | * precious DMA-able memory... | |
1116 | */ | |
2778f620 | 1117 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
d111e8f9 | 1118 | #endif |
d111e8f9 RK |
1119 | } |
1120 | ||
1121 | /* | |
0536bdf3 NP |
1122 | * Set up the device mappings. Since we clear out the page tables for all |
1123 | * mappings above VMALLOC_START, we will remove any debug device mappings. | |
d111e8f9 RK |
1124 | * This means you have to be careful how you debug this function, or any |
1125 | * called function. This means you can't use any function or debugging | |
1126 | * method which may touch any device, otherwise the kernel _will_ crash. | |
1127 | */ | |
1128 | static void __init devicemaps_init(struct machine_desc *mdesc) | |
1129 | { | |
1130 | struct map_desc map; | |
1131 | unsigned long addr; | |
94e5a85b | 1132 | void *vectors; |
d111e8f9 RK |
1133 | |
1134 | /* | |
1135 | * Allocate the vector page early. | |
1136 | */ | |
94e5a85b RK |
1137 | vectors = early_alloc(PAGE_SIZE); |
1138 | ||
1139 | early_trap_init(vectors); | |
d111e8f9 | 1140 | |
0536bdf3 | 1141 | for (addr = VMALLOC_START; addr; addr += PMD_SIZE) |
d111e8f9 RK |
1142 | pmd_clear(pmd_off_k(addr)); |
1143 | ||
1144 | /* | |
1145 | * Map the kernel if it is XIP. | |
1146 | * It is always first in the modulearea. | |
1147 | */ | |
1148 | #ifdef CONFIG_XIP_KERNEL | |
1149 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 1150 | map.virtual = MODULES_VADDR; |
37efe642 | 1151 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
1152 | map.type = MT_ROM; |
1153 | create_mapping(&map); | |
1154 | #endif | |
1155 | ||
1156 | /* | |
1157 | * Map the cache flushing regions. | |
1158 | */ | |
1159 | #ifdef FLUSH_BASE | |
1160 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
1161 | map.virtual = FLUSH_BASE; | |
1162 | map.length = SZ_1M; | |
1163 | map.type = MT_CACHECLEAN; | |
1164 | create_mapping(&map); | |
1165 | #endif | |
1166 | #ifdef FLUSH_BASE_MINICACHE | |
1167 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
1168 | map.virtual = FLUSH_BASE_MINICACHE; | |
1169 | map.length = SZ_1M; | |
1170 | map.type = MT_MINICLEAN; | |
1171 | create_mapping(&map); | |
1172 | #endif | |
1173 | ||
1174 | /* | |
1175 | * Create a mapping for the machine vectors at the high-vectors | |
1176 | * location (0xffff0000). If we aren't using high-vectors, also | |
1177 | * create a mapping at the low-vectors virtual address. | |
1178 | */ | |
94e5a85b | 1179 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
d111e8f9 RK |
1180 | map.virtual = 0xffff0000; |
1181 | map.length = PAGE_SIZE; | |
1182 | map.type = MT_HIGH_VECTORS; | |
1183 | create_mapping(&map); | |
1184 | ||
1185 | if (!vectors_high()) { | |
1186 | map.virtual = 0; | |
1187 | map.type = MT_LOW_VECTORS; | |
1188 | create_mapping(&map); | |
1189 | } | |
1190 | ||
1191 | /* | |
1192 | * Ask the machine support to map in the statically mapped devices. | |
1193 | */ | |
1194 | if (mdesc->map_io) | |
1195 | mdesc->map_io(); | |
19b52abe | 1196 | fill_pmd_gaps(); |
d111e8f9 | 1197 | |
c2794437 RH |
1198 | /* Reserve fixed i/o space in VMALLOC region */ |
1199 | pci_reserve_io(); | |
1200 | ||
d111e8f9 RK |
1201 | /* |
1202 | * Finally flush the caches and tlb to ensure that we're in a | |
1203 | * consistent state wrt the writebuffer. This also ensures that | |
1204 | * any write-allocated cache lines in the vector page are written | |
1205 | * back. After this point, we can start to touch devices again. | |
1206 | */ | |
1207 | local_flush_tlb_all(); | |
1208 | flush_cache_all(); | |
1209 | } | |
1210 | ||
d73cd428 NP |
1211 | static void __init kmap_init(void) |
1212 | { | |
1213 | #ifdef CONFIG_HIGHMEM | |
4bb2e27d RK |
1214 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
1215 | PKMAP_BASE, _PAGE_KERNEL_TABLE); | |
d73cd428 NP |
1216 | #endif |
1217 | } | |
1218 | ||
a2227120 RK |
1219 | static void __init map_lowmem(void) |
1220 | { | |
8df65168 | 1221 | struct memblock_region *reg; |
a2227120 RK |
1222 | |
1223 | /* Map all the lowmem memory banks. */ | |
8df65168 RK |
1224 | for_each_memblock(memory, reg) { |
1225 | phys_addr_t start = reg->base; | |
1226 | phys_addr_t end = start + reg->size; | |
1227 | struct map_desc map; | |
1228 | ||
c7909509 MS |
1229 | if (end > arm_lowmem_limit) |
1230 | end = arm_lowmem_limit; | |
8df65168 RK |
1231 | if (start >= end) |
1232 | break; | |
1233 | ||
1234 | map.pfn = __phys_to_pfn(start); | |
1235 | map.virtual = __phys_to_virt(start); | |
1236 | map.length = end - start; | |
1237 | map.type = MT_MEMORY; | |
a2227120 | 1238 | |
8df65168 | 1239 | create_mapping(&map); |
a2227120 RK |
1240 | } |
1241 | } | |
1242 | ||
d111e8f9 RK |
1243 | /* |
1244 | * paging_init() sets up the page tables, initialises the zone memory | |
1245 | * maps, and sets up the zero page, bad page and bad page tables. | |
1246 | */ | |
4b5f32ce | 1247 | void __init paging_init(struct machine_desc *mdesc) |
d111e8f9 RK |
1248 | { |
1249 | void *zero_page; | |
1250 | ||
c7909509 | 1251 | memblock_set_current_limit(arm_lowmem_limit); |
0371d3f7 | 1252 | |
d111e8f9 | 1253 | build_mem_type_table(); |
4b5f32ce | 1254 | prepare_page_table(); |
a2227120 | 1255 | map_lowmem(); |
c7909509 | 1256 | dma_contiguous_remap(); |
d111e8f9 | 1257 | devicemaps_init(mdesc); |
d73cd428 | 1258 | kmap_init(); |
d111e8f9 RK |
1259 | |
1260 | top_pmd = pmd_off_k(0xffff0000); | |
1261 | ||
3abe9d33 RK |
1262 | /* allocate the zero page. */ |
1263 | zero_page = early_alloc(PAGE_SIZE); | |
2778f620 | 1264 | |
8d717a52 | 1265 | bootmem_init(); |
2778f620 | 1266 | |
d111e8f9 | 1267 | empty_zero_page = virt_to_page(zero_page); |
421fe93c | 1268 | __flush_dcache_page(NULL, empty_zero_page); |
d111e8f9 | 1269 | } |