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d111e8f9 RK |
1 | /* |
2 | * linux/arch/arm/mm/mmu.c | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ae8f1541 | 10 | #include <linux/module.h> |
d111e8f9 RK |
11 | #include <linux/kernel.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/init.h> | |
d111e8f9 RK |
14 | #include <linux/mman.h> |
15 | #include <linux/nodemask.h> | |
2778f620 | 16 | #include <linux/memblock.h> |
d907387c | 17 | #include <linux/fs.h> |
0536bdf3 | 18 | #include <linux/vmalloc.h> |
158e8bfe | 19 | #include <linux/sizes.h> |
d111e8f9 | 20 | |
15d07dc9 | 21 | #include <asm/cp15.h> |
0ba8b9b2 | 22 | #include <asm/cputype.h> |
37efe642 | 23 | #include <asm/sections.h> |
3f973e22 | 24 | #include <asm/cachetype.h> |
ebd4922e | 25 | #include <asm/sections.h> |
d111e8f9 | 26 | #include <asm/setup.h> |
e616c591 | 27 | #include <asm/smp_plat.h> |
d111e8f9 | 28 | #include <asm/tlb.h> |
d73cd428 | 29 | #include <asm/highmem.h> |
9f97da78 | 30 | #include <asm/system_info.h> |
247055aa | 31 | #include <asm/traps.h> |
a77e0c7b SS |
32 | #include <asm/procinfo.h> |
33 | #include <asm/memory.h> | |
d111e8f9 RK |
34 | |
35 | #include <asm/mach/arch.h> | |
36 | #include <asm/mach/map.h> | |
c2794437 | 37 | #include <asm/mach/pci.h> |
d111e8f9 RK |
38 | |
39 | #include "mm.h" | |
de40614e | 40 | #include "tcm.h" |
d111e8f9 | 41 | |
d111e8f9 RK |
42 | /* |
43 | * empty_zero_page is a special page that is used for | |
44 | * zero-initialized data and COW. | |
45 | */ | |
46 | struct page *empty_zero_page; | |
3653f3ab | 47 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
48 | |
49 | /* | |
50 | * The pmd table for the upper-most set of pages. | |
51 | */ | |
52 | pmd_t *top_pmd; | |
53 | ||
ae8f1541 RK |
54 | #define CPOLICY_UNCACHED 0 |
55 | #define CPOLICY_BUFFERED 1 | |
56 | #define CPOLICY_WRITETHROUGH 2 | |
57 | #define CPOLICY_WRITEBACK 3 | |
58 | #define CPOLICY_WRITEALLOC 4 | |
59 | ||
60 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
61 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 62 | pgprot_t pgprot_user; |
ae8f1541 | 63 | pgprot_t pgprot_kernel; |
cc577c26 CD |
64 | pgprot_t pgprot_hyp_device; |
65 | pgprot_t pgprot_s2; | |
66 | pgprot_t pgprot_s2_device; | |
ae8f1541 | 67 | |
44b18693 | 68 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
69 | EXPORT_SYMBOL(pgprot_kernel); |
70 | ||
71 | struct cachepolicy { | |
72 | const char policy[16]; | |
73 | unsigned int cr_mask; | |
442e70c0 | 74 | pmdval_t pmd; |
f6e3354d | 75 | pteval_t pte; |
cc577c26 | 76 | pteval_t pte_s2; |
ae8f1541 RK |
77 | }; |
78 | ||
cc577c26 CD |
79 | #ifdef CONFIG_ARM_LPAE |
80 | #define s2_policy(policy) policy | |
81 | #else | |
82 | #define s2_policy(policy) 0 | |
83 | #endif | |
84 | ||
ae8f1541 RK |
85 | static struct cachepolicy cache_policies[] __initdata = { |
86 | { | |
87 | .policy = "uncached", | |
88 | .cr_mask = CR_W|CR_C, | |
89 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 90 | .pte = L_PTE_MT_UNCACHED, |
cc577c26 | 91 | .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), |
ae8f1541 RK |
92 | }, { |
93 | .policy = "buffered", | |
94 | .cr_mask = CR_C, | |
95 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 96 | .pte = L_PTE_MT_BUFFERABLE, |
cc577c26 | 97 | .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED), |
ae8f1541 RK |
98 | }, { |
99 | .policy = "writethrough", | |
100 | .cr_mask = 0, | |
101 | .pmd = PMD_SECT_WT, | |
bb30f36f | 102 | .pte = L_PTE_MT_WRITETHROUGH, |
cc577c26 | 103 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH), |
ae8f1541 RK |
104 | }, { |
105 | .policy = "writeback", | |
106 | .cr_mask = 0, | |
107 | .pmd = PMD_SECT_WB, | |
bb30f36f | 108 | .pte = L_PTE_MT_WRITEBACK, |
cc577c26 | 109 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), |
ae8f1541 RK |
110 | }, { |
111 | .policy = "writealloc", | |
112 | .cr_mask = 0, | |
113 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 114 | .pte = L_PTE_MT_WRITEALLOC, |
cc577c26 | 115 | .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK), |
ae8f1541 RK |
116 | } |
117 | }; | |
118 | ||
b849a60e | 119 | #ifdef CONFIG_CPU_CP15 |
ae8f1541 | 120 | /* |
6cbdc8c5 | 121 | * These are useful for identifying cache coherency |
ae8f1541 RK |
122 | * problems by allowing the cache or the cache and |
123 | * writebuffer to be turned off. (Note: the write | |
124 | * buffer should not be on and the cache off). | |
125 | */ | |
2b0d8c25 | 126 | static int __init early_cachepolicy(char *p) |
ae8f1541 RK |
127 | { |
128 | int i; | |
129 | ||
130 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { | |
131 | int len = strlen(cache_policies[i].policy); | |
132 | ||
2b0d8c25 | 133 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ae8f1541 RK |
134 | cachepolicy = i; |
135 | cr_alignment &= ~cache_policies[i].cr_mask; | |
136 | cr_no_alignment &= ~cache_policies[i].cr_mask; | |
ae8f1541 RK |
137 | break; |
138 | } | |
139 | } | |
140 | if (i == ARRAY_SIZE(cache_policies)) | |
141 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); | |
4b46d641 RK |
142 | /* |
143 | * This restriction is partly to do with the way we boot; it is | |
144 | * unpredictable to have memory mapped using two different sets of | |
145 | * memory attributes (shared, type, and cache attribs). We can not | |
146 | * change these attributes once the initial assembly has setup the | |
147 | * page tables. | |
148 | */ | |
11179d8c CM |
149 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
150 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); | |
151 | cachepolicy = CPOLICY_WRITEBACK; | |
152 | } | |
ae8f1541 RK |
153 | flush_cache_all(); |
154 | set_cr(cr_alignment); | |
2b0d8c25 | 155 | return 0; |
ae8f1541 | 156 | } |
2b0d8c25 | 157 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 158 | |
2b0d8c25 | 159 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
160 | { |
161 | char *p = "buffered"; | |
162 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
163 | early_cachepolicy(p); |
164 | return 0; | |
ae8f1541 | 165 | } |
2b0d8c25 | 166 | early_param("nocache", early_nocache); |
ae8f1541 | 167 | |
2b0d8c25 | 168 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
169 | { |
170 | char *p = "uncached"; | |
171 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
172 | early_cachepolicy(p); |
173 | return 0; | |
ae8f1541 | 174 | } |
2b0d8c25 | 175 | early_param("nowb", early_nowrite); |
ae8f1541 | 176 | |
1b6ba46b | 177 | #ifndef CONFIG_ARM_LPAE |
2b0d8c25 | 178 | static int __init early_ecc(char *p) |
ae8f1541 | 179 | { |
2b0d8c25 | 180 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 181 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 182 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 183 | ecc_mask = 0; |
2b0d8c25 | 184 | return 0; |
ae8f1541 | 185 | } |
2b0d8c25 | 186 | early_param("ecc", early_ecc); |
1b6ba46b | 187 | #endif |
ae8f1541 RK |
188 | |
189 | static int __init noalign_setup(char *__unused) | |
190 | { | |
191 | cr_alignment &= ~CR_A; | |
192 | cr_no_alignment &= ~CR_A; | |
193 | set_cr(cr_alignment); | |
194 | return 1; | |
195 | } | |
196 | __setup("noalign", noalign_setup); | |
197 | ||
255d1f86 RK |
198 | #ifndef CONFIG_SMP |
199 | void adjust_cr(unsigned long mask, unsigned long set) | |
200 | { | |
201 | unsigned long flags; | |
202 | ||
203 | mask &= ~CR_A; | |
204 | ||
205 | set &= mask; | |
206 | ||
207 | local_irq_save(flags); | |
208 | ||
209 | cr_no_alignment = (cr_no_alignment & ~mask) | set; | |
210 | cr_alignment = (cr_alignment & ~mask) | set; | |
211 | ||
212 | set_cr((get_cr() & ~mask) | set); | |
213 | ||
214 | local_irq_restore(flags); | |
215 | } | |
216 | #endif | |
217 | ||
b849a60e UKK |
218 | #else /* ifdef CONFIG_CPU_CP15 */ |
219 | ||
220 | static int __init early_cachepolicy(char *p) | |
221 | { | |
222 | pr_warning("cachepolicy kernel parameter not supported without cp15\n"); | |
223 | } | |
224 | early_param("cachepolicy", early_cachepolicy); | |
225 | ||
226 | static int __init noalign_setup(char *__unused) | |
227 | { | |
228 | pr_warning("noalign kernel parameter not supported without cp15\n"); | |
229 | } | |
230 | __setup("noalign", noalign_setup); | |
231 | ||
232 | #endif /* ifdef CONFIG_CPU_CP15 / else */ | |
233 | ||
36bb94ba | 234 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
b1cce6b1 | 235 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 236 | |
b29e9f5e | 237 | static struct mem_type mem_types[] = { |
0af92bef | 238 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
239 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
240 | L_PTE_SHARED, | |
0af92bef | 241 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 242 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
243 | .domain = DOMAIN_IO, |
244 | }, | |
245 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 246 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 247 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 248 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
249 | .domain = DOMAIN_IO, |
250 | }, | |
251 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 252 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
253 | .prot_l1 = PMD_TYPE_TABLE, |
254 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
255 | .domain = DOMAIN_IO, | |
c2794437 | 256 | }, |
1ad77a87 | 257 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 258 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 259 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 260 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 261 | .domain = DOMAIN_IO, |
ae8f1541 | 262 | }, |
ebb4c658 RK |
263 | [MT_UNCACHED] = { |
264 | .prot_pte = PROT_PTE_DEVICE, | |
265 | .prot_l1 = PMD_TYPE_TABLE, | |
266 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
267 | .domain = DOMAIN_IO, | |
268 | }, | |
ae8f1541 | 269 | [MT_CACHECLEAN] = { |
9ef79635 | 270 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
271 | .domain = DOMAIN_KERNEL, |
272 | }, | |
1b6ba46b | 273 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 | 274 | [MT_MINICLEAN] = { |
9ef79635 | 275 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
276 | .domain = DOMAIN_KERNEL, |
277 | }, | |
1b6ba46b | 278 | #endif |
ae8f1541 RK |
279 | [MT_LOW_VECTORS] = { |
280 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 281 | L_PTE_RDONLY, |
ae8f1541 RK |
282 | .prot_l1 = PMD_TYPE_TABLE, |
283 | .domain = DOMAIN_USER, | |
284 | }, | |
285 | [MT_HIGH_VECTORS] = { | |
286 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 287 | L_PTE_USER | L_PTE_RDONLY, |
ae8f1541 RK |
288 | .prot_l1 = PMD_TYPE_TABLE, |
289 | .domain = DOMAIN_USER, | |
290 | }, | |
2e2c9de2 | 291 | [MT_MEMORY_RWX] = { |
36bb94ba | 292 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
f1a2481c | 293 | .prot_l1 = PMD_TYPE_TABLE, |
9ef79635 | 294 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
295 | .domain = DOMAIN_KERNEL, |
296 | }, | |
ebd4922e RK |
297 | [MT_MEMORY_RW] = { |
298 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
299 | L_PTE_XN, | |
300 | .prot_l1 = PMD_TYPE_TABLE, | |
301 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, | |
302 | .domain = DOMAIN_KERNEL, | |
303 | }, | |
ae8f1541 | 304 | [MT_ROM] = { |
9ef79635 | 305 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
306 | .domain = DOMAIN_KERNEL, |
307 | }, | |
2e2c9de2 | 308 | [MT_MEMORY_RWX_NONCACHED] = { |
f1a2481c | 309 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 310 | L_PTE_MT_BUFFERABLE, |
f1a2481c | 311 | .prot_l1 = PMD_TYPE_TABLE, |
e4707dd3 PW |
312 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
313 | .domain = DOMAIN_KERNEL, | |
314 | }, | |
2e2c9de2 | 315 | [MT_MEMORY_RW_DTCM] = { |
f444fce3 | 316 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 317 | L_PTE_XN, |
f444fce3 LW |
318 | .prot_l1 = PMD_TYPE_TABLE, |
319 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
320 | .domain = DOMAIN_KERNEL, | |
cb9d7707 | 321 | }, |
2e2c9de2 | 322 | [MT_MEMORY_RWX_ITCM] = { |
36bb94ba | 323 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
cb9d7707 | 324 | .prot_l1 = PMD_TYPE_TABLE, |
f444fce3 | 325 | .domain = DOMAIN_KERNEL, |
cb9d7707 | 326 | }, |
2e2c9de2 | 327 | [MT_MEMORY_RW_SO] = { |
8fb54284 | 328 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
93d5bf07 | 329 | L_PTE_MT_UNCACHED | L_PTE_XN, |
8fb54284 SS |
330 | .prot_l1 = PMD_TYPE_TABLE, |
331 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | | |
332 | PMD_SECT_UNCACHED | PMD_SECT_XN, | |
333 | .domain = DOMAIN_KERNEL, | |
334 | }, | |
c7909509 | 335 | [MT_MEMORY_DMA_READY] = { |
71b55663 RK |
336 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
337 | L_PTE_XN, | |
c7909509 MS |
338 | .prot_l1 = PMD_TYPE_TABLE, |
339 | .domain = DOMAIN_KERNEL, | |
340 | }, | |
ae8f1541 RK |
341 | }; |
342 | ||
b29e9f5e RK |
343 | const struct mem_type *get_mem_type(unsigned int type) |
344 | { | |
345 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
346 | } | |
69d3a84a | 347 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 348 | |
75374ad4 LA |
349 | #define PTE_SET_FN(_name, pteop) \ |
350 | static int pte_set_##_name(pte_t *ptep, pgtable_t token, unsigned long addr, \ | |
351 | void *data) \ | |
352 | { \ | |
353 | pte_t pte = pteop(*ptep); \ | |
354 | \ | |
355 | set_pte_ext(ptep, pte, 0); \ | |
356 | return 0; \ | |
357 | } \ | |
358 | ||
359 | #define SET_MEMORY_FN(_name, callback) \ | |
360 | int set_memory_##_name(unsigned long addr, int numpages) \ | |
361 | { \ | |
362 | unsigned long start = addr; \ | |
363 | unsigned long size = PAGE_SIZE*numpages; \ | |
364 | unsigned end = start + size; \ | |
365 | \ | |
366 | if (start < MODULES_VADDR || start >= MODULES_END) \ | |
367 | return -EINVAL;\ | |
368 | \ | |
369 | if (end < MODULES_VADDR || end >= MODULES_END) \ | |
370 | return -EINVAL; \ | |
371 | \ | |
372 | apply_to_page_range(&init_mm, start, size, callback, NULL); \ | |
373 | flush_tlb_kernel_range(start, end); \ | |
374 | return 0;\ | |
375 | } | |
376 | ||
377 | PTE_SET_FN(ro, pte_wrprotect) | |
378 | PTE_SET_FN(rw, pte_mkwrite) | |
379 | PTE_SET_FN(x, pte_mkexec) | |
380 | PTE_SET_FN(nx, pte_mknexec) | |
381 | ||
382 | SET_MEMORY_FN(ro, pte_set_ro) | |
383 | SET_MEMORY_FN(rw, pte_set_rw) | |
384 | SET_MEMORY_FN(x, pte_set_x) | |
385 | SET_MEMORY_FN(nx, pte_set_nx) | |
386 | ||
ae8f1541 RK |
387 | /* |
388 | * Adjust the PMD section entries according to the CPU in use. | |
389 | */ | |
390 | static void __init build_mem_type_table(void) | |
391 | { | |
392 | struct cachepolicy *cp; | |
393 | unsigned int cr = get_cr(); | |
442e70c0 | 394 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
cc577c26 | 395 | pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot; |
ae8f1541 RK |
396 | int cpu_arch = cpu_architecture(); |
397 | int i; | |
398 | ||
11179d8c | 399 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 400 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
401 | if (cachepolicy > CPOLICY_BUFFERED) |
402 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 403 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
404 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
405 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 406 | #endif |
11179d8c | 407 | } |
ae8f1541 RK |
408 | if (cpu_arch < CPU_ARCH_ARMv5) { |
409 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
410 | cachepolicy = CPOLICY_WRITEBACK; | |
411 | ecc_mask = 0; | |
412 | } | |
f00ec48f RK |
413 | if (is_smp()) |
414 | cachepolicy = CPOLICY_WRITEALLOC; | |
ae8f1541 | 415 | |
1ad77a87 | 416 | /* |
b1cce6b1 RK |
417 | * Strip out features not present on earlier architectures. |
418 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
419 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 420 | */ |
b1cce6b1 RK |
421 | if (cpu_arch < CPU_ARCH_ARMv5) |
422 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
423 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
424 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
425 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
426 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
427 | |
428 | /* | |
b1cce6b1 RK |
429 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
430 | * "update-able on write" bit on ARM610). However, Xscale and | |
431 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 432 | */ |
b1cce6b1 | 433 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
9ef79635 | 434 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 435 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
436 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
437 | } | |
438 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
439 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
440 | if (mem_types[i].prot_l1) |
441 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
442 | if (mem_types[i].prot_sect) |
443 | mem_types[i].prot_sect |= PMD_BIT4; | |
444 | } | |
445 | } | |
ae8f1541 | 446 | |
b1cce6b1 RK |
447 | /* |
448 | * Mark the device areas according to the CPU/architecture. | |
449 | */ | |
450 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
451 | if (!cpu_is_xsc3()) { | |
452 | /* | |
453 | * Mark device regions on ARMv6+ as execute-never | |
454 | * to prevent speculative instruction fetches. | |
455 | */ | |
456 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
457 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
458 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
459 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
ebd4922e RK |
460 | |
461 | /* Also setup NX memory mapping */ | |
462 | mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN; | |
b1cce6b1 RK |
463 | } |
464 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
465 | /* | |
466 | * For ARMv7 with TEX remapping, | |
467 | * - shared device is SXCB=1100 | |
468 | * - nonshared device is SXCB=0100 | |
469 | * - write combine device mem is SXCB=0001 | |
470 | * (Uncached Normal memory) | |
471 | */ | |
472 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
473 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
474 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
475 | } else if (cpu_is_xsc3()) { | |
476 | /* | |
477 | * For Xscale3, | |
478 | * - shared device is TEXCB=00101 | |
479 | * - nonshared device is TEXCB=01000 | |
480 | * - write combine device mem is TEXCB=00100 | |
481 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
482 | */ | |
483 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
484 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
485 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
486 | } else { | |
487 | /* | |
488 | * For ARMv6 and ARMv7 without TEX remapping, | |
489 | * - shared device is TEXCB=00001 | |
490 | * - nonshared device is TEXCB=01000 | |
491 | * - write combine device mem is TEXCB=00100 | |
492 | * (Uncached Normal in ARMv6 parlance). | |
493 | */ | |
494 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
495 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
496 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
497 | } | |
498 | } else { | |
499 | /* | |
500 | * On others, write combining is "Uncached/Buffered" | |
501 | */ | |
502 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
503 | } | |
504 | ||
505 | /* | |
506 | * Now deal with the memory-type mappings | |
507 | */ | |
ae8f1541 | 508 | cp = &cache_policies[cachepolicy]; |
bb30f36f | 509 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
cc577c26 CD |
510 | s2_pgprot = cp->pte_s2; |
511 | hyp_device_pgprot = s2_device_pgprot = mem_types[MT_DEVICE].prot_pte; | |
bb30f36f | 512 | |
ae8f1541 RK |
513 | /* |
514 | * ARMv6 and above have extended page tables. | |
515 | */ | |
516 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
1b6ba46b | 517 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
518 | /* |
519 | * Mark cache clean areas and XIP ROM read only | |
520 | * from SVC mode and no access from userspace. | |
521 | */ | |
522 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
523 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
524 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
1b6ba46b | 525 | #endif |
ae8f1541 | 526 | |
f00ec48f RK |
527 | if (is_smp()) { |
528 | /* | |
529 | * Mark memory with the "shared" attribute | |
530 | * for SMP systems | |
531 | */ | |
532 | user_pgprot |= L_PTE_SHARED; | |
533 | kern_pgprot |= L_PTE_SHARED; | |
534 | vecs_pgprot |= L_PTE_SHARED; | |
cc577c26 | 535 | s2_pgprot |= L_PTE_SHARED; |
f00ec48f RK |
536 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; |
537 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; | |
538 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; | |
539 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; | |
2e2c9de2 RK |
540 | mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S; |
541 | mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED; | |
ebd4922e RK |
542 | mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S; |
543 | mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED; | |
c7909509 | 544 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
2e2c9de2 RK |
545 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S; |
546 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED; | |
f00ec48f | 547 | } |
ae8f1541 RK |
548 | } |
549 | ||
e4707dd3 PW |
550 | /* |
551 | * Non-cacheable Normal - intended for memory areas that must | |
552 | * not cause dirty cache line writebacks when used | |
553 | */ | |
554 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
555 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
556 | /* Non-cacheable Normal is XCB = 001 */ | |
2e2c9de2 | 557 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= |
e4707dd3 PW |
558 | PMD_SECT_BUFFERED; |
559 | } else { | |
560 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
2e2c9de2 | 561 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= |
e4707dd3 PW |
562 | PMD_SECT_TEX(1); |
563 | } | |
564 | } else { | |
2e2c9de2 | 565 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; |
e4707dd3 PW |
566 | } |
567 | ||
1b6ba46b CM |
568 | #ifdef CONFIG_ARM_LPAE |
569 | /* | |
570 | * Do not generate access flag faults for the kernel mappings. | |
571 | */ | |
572 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
573 | mem_types[i].prot_pte |= PTE_EXT_AF; | |
1a3abcf4 VA |
574 | if (mem_types[i].prot_sect) |
575 | mem_types[i].prot_sect |= PMD_SECT_AF; | |
1b6ba46b CM |
576 | } |
577 | kern_pgprot |= PTE_EXT_AF; | |
578 | vecs_pgprot |= PTE_EXT_AF; | |
579 | #endif | |
580 | ||
ae8f1541 | 581 | for (i = 0; i < 16; i++) { |
864aa04c | 582 | pteval_t v = pgprot_val(protection_map[i]); |
bb30f36f | 583 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
584 | } |
585 | ||
bb30f36f RK |
586 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
587 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 588 | |
44b18693 | 589 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 590 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
36bb94ba | 591 | L_PTE_DIRTY | kern_pgprot); |
cc577c26 CD |
592 | pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot); |
593 | pgprot_s2_device = __pgprot(s2_device_pgprot); | |
594 | pgprot_hyp_device = __pgprot(hyp_device_pgprot); | |
ae8f1541 RK |
595 | |
596 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
597 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
2e2c9de2 RK |
598 | mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd; |
599 | mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot; | |
ebd4922e RK |
600 | mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd; |
601 | mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot; | |
c7909509 | 602 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; |
2e2c9de2 | 603 | mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask; |
ae8f1541 RK |
604 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
605 | ||
606 | switch (cp->pmd) { | |
607 | case PMD_SECT_WT: | |
608 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
609 | break; | |
610 | case PMD_SECT_WB: | |
611 | case PMD_SECT_WBWA: | |
612 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
613 | break; | |
614 | } | |
905b5797 MS |
615 | pr_info("Memory policy: %sData cache %s\n", |
616 | ecc_mask ? "ECC enabled, " : "", cp->policy); | |
2497f0a8 RK |
617 | |
618 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
619 | struct mem_type *t = &mem_types[i]; | |
620 | if (t->prot_l1) | |
621 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
622 | if (t->prot_sect) | |
623 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
624 | } | |
ae8f1541 RK |
625 | } |
626 | ||
d907387c CM |
627 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
628 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
629 | unsigned long size, pgprot_t vma_prot) | |
630 | { | |
631 | if (!pfn_valid(pfn)) | |
632 | return pgprot_noncached(vma_prot); | |
633 | else if (file->f_flags & O_SYNC) | |
634 | return pgprot_writecombine(vma_prot); | |
635 | return vma_prot; | |
636 | } | |
637 | EXPORT_SYMBOL(phys_mem_access_prot); | |
638 | #endif | |
639 | ||
ae8f1541 RK |
640 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
641 | ||
0536bdf3 | 642 | static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) |
3abe9d33 | 643 | { |
0536bdf3 | 644 | void *ptr = __va(memblock_alloc(sz, align)); |
2778f620 RK |
645 | memset(ptr, 0, sz); |
646 | return ptr; | |
3abe9d33 RK |
647 | } |
648 | ||
0536bdf3 NP |
649 | static void __init *early_alloc(unsigned long sz) |
650 | { | |
651 | return early_alloc_aligned(sz, sz); | |
652 | } | |
653 | ||
4bb2e27d | 654 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) |
ae8f1541 | 655 | { |
24e6c699 | 656 | if (pmd_none(*pmd)) { |
410f1483 | 657 | pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
97092e0c | 658 | __pmd_populate(pmd, __pa(pte), prot); |
24e6c699 | 659 | } |
4bb2e27d RK |
660 | BUG_ON(pmd_bad(*pmd)); |
661 | return pte_offset_kernel(pmd, addr); | |
662 | } | |
ae8f1541 | 663 | |
4bb2e27d RK |
664 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
665 | unsigned long end, unsigned long pfn, | |
666 | const struct mem_type *type) | |
667 | { | |
668 | pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); | |
24e6c699 | 669 | do { |
40d192b6 | 670 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
24e6c699 RK |
671 | pfn++; |
672 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
673 | } |
674 | ||
37468b30 | 675 | static void __init __map_init_section(pmd_t *pmd, unsigned long addr, |
e651eab0 S |
676 | unsigned long end, phys_addr_t phys, |
677 | const struct mem_type *type) | |
ae8f1541 | 678 | { |
37468b30 PYC |
679 | pmd_t *p = pmd; |
680 | ||
e651eab0 | 681 | #ifndef CONFIG_ARM_LPAE |
24e6c699 | 682 | /* |
e651eab0 S |
683 | * In classic MMU format, puds and pmds are folded in to |
684 | * the pgds. pmd_offset gives the PGD entry. PGDs refer to a | |
685 | * group of L1 entries making up one logical pointer to | |
686 | * an L2 table (2MB), where as PMDs refer to the individual | |
687 | * L1 entries (1MB). Hence increment to get the correct | |
688 | * offset for odd 1MB sections. | |
689 | * (See arch/arm/include/asm/pgtable-2level.h) | |
24e6c699 | 690 | */ |
e651eab0 S |
691 | if (addr & SECTION_SIZE) |
692 | pmd++; | |
1b6ba46b | 693 | #endif |
e651eab0 S |
694 | do { |
695 | *pmd = __pmd(phys | type->prot_sect); | |
696 | phys += SECTION_SIZE; | |
697 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
24e6c699 | 698 | |
37468b30 | 699 | flush_pmd_entry(p); |
e651eab0 | 700 | } |
ae8f1541 | 701 | |
e651eab0 S |
702 | static void __init alloc_init_pmd(pud_t *pud, unsigned long addr, |
703 | unsigned long end, phys_addr_t phys, | |
704 | const struct mem_type *type) | |
705 | { | |
706 | pmd_t *pmd = pmd_offset(pud, addr); | |
707 | unsigned long next; | |
708 | ||
709 | do { | |
24e6c699 | 710 | /* |
e651eab0 S |
711 | * With LPAE, we must loop over to map |
712 | * all the pmds for the given range. | |
24e6c699 | 713 | */ |
e651eab0 S |
714 | next = pmd_addr_end(addr, end); |
715 | ||
716 | /* | |
717 | * Try a section mapping - addr, next and phys must all be | |
718 | * aligned to a section boundary. | |
719 | */ | |
720 | if (type->prot_sect && | |
721 | ((addr | next | phys) & ~SECTION_MASK) == 0) { | |
37468b30 | 722 | __map_init_section(pmd, addr, next, phys, type); |
e651eab0 S |
723 | } else { |
724 | alloc_init_pte(pmd, addr, next, | |
725 | __phys_to_pfn(phys), type); | |
726 | } | |
727 | ||
728 | phys += next - addr; | |
729 | ||
730 | } while (pmd++, addr = next, addr != end); | |
ae8f1541 RK |
731 | } |
732 | ||
14904927 | 733 | static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, |
20d6956d VA |
734 | unsigned long end, phys_addr_t phys, |
735 | const struct mem_type *type) | |
516295e5 RK |
736 | { |
737 | pud_t *pud = pud_offset(pgd, addr); | |
738 | unsigned long next; | |
739 | ||
740 | do { | |
741 | next = pud_addr_end(addr, end); | |
e651eab0 | 742 | alloc_init_pmd(pud, addr, next, phys, type); |
516295e5 RK |
743 | phys += next - addr; |
744 | } while (pud++, addr = next, addr != end); | |
745 | } | |
746 | ||
1b6ba46b | 747 | #ifndef CONFIG_ARM_LPAE |
4a56c1e4 RK |
748 | static void __init create_36bit_mapping(struct map_desc *md, |
749 | const struct mem_type *type) | |
750 | { | |
97092e0c RK |
751 | unsigned long addr, length, end; |
752 | phys_addr_t phys; | |
4a56c1e4 RK |
753 | pgd_t *pgd; |
754 | ||
755 | addr = md->virtual; | |
cae6292b | 756 | phys = __pfn_to_phys(md->pfn); |
4a56c1e4 RK |
757 | length = PAGE_ALIGN(md->length); |
758 | ||
759 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
760 | printk(KERN_ERR "MM: CPU does not support supersection " | |
761 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 762 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
763 | return; |
764 | } | |
765 | ||
766 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
767 | * Since domain assignments can in fact be arbitrary, the | |
768 | * 'domain == 0' check below is required to insure that ARMv6 | |
769 | * supersections are only allocated for domain 0 regardless | |
770 | * of the actual domain assignments in use. | |
771 | */ | |
772 | if (type->domain) { | |
773 | printk(KERN_ERR "MM: invalid domain in supersection " | |
774 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 775 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
776 | return; |
777 | } | |
778 | ||
779 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
29a38193 WD |
780 | printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" |
781 | " at 0x%08lx invalid alignment\n", | |
782 | (long long)__pfn_to_phys((u64)md->pfn), addr); | |
4a56c1e4 RK |
783 | return; |
784 | } | |
785 | ||
786 | /* | |
787 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
788 | * (See ARMv6 spec). | |
789 | */ | |
790 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
791 | ||
792 | pgd = pgd_offset_k(addr); | |
793 | end = addr + length; | |
794 | do { | |
516295e5 RK |
795 | pud_t *pud = pud_offset(pgd, addr); |
796 | pmd_t *pmd = pmd_offset(pud, addr); | |
4a56c1e4 RK |
797 | int i; |
798 | ||
799 | for (i = 0; i < 16; i++) | |
800 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); | |
801 | ||
802 | addr += SUPERSECTION_SIZE; | |
803 | phys += SUPERSECTION_SIZE; | |
804 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
805 | } while (addr != end); | |
806 | } | |
1b6ba46b | 807 | #endif /* !CONFIG_ARM_LPAE */ |
4a56c1e4 | 808 | |
ae8f1541 RK |
809 | /* |
810 | * Create the page directory entries and any necessary | |
811 | * page tables for the mapping specified by `md'. We | |
812 | * are able to cope here with varying sizes and address | |
813 | * offsets, and we take full advantage of sections and | |
814 | * supersections. | |
815 | */ | |
a2227120 | 816 | static void __init create_mapping(struct map_desc *md) |
ae8f1541 | 817 | { |
cae6292b WD |
818 | unsigned long addr, length, end; |
819 | phys_addr_t phys; | |
d5c98176 | 820 | const struct mem_type *type; |
24e6c699 | 821 | pgd_t *pgd; |
ae8f1541 RK |
822 | |
823 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
29a38193 WD |
824 | printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" |
825 | " at 0x%08lx in user region\n", | |
826 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
ae8f1541 RK |
827 | return; |
828 | } | |
829 | ||
830 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
0536bdf3 NP |
831 | md->virtual >= PAGE_OFFSET && |
832 | (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { | |
29a38193 | 833 | printk(KERN_WARNING "BUG: mapping for 0x%08llx" |
0536bdf3 | 834 | " at 0x%08lx out of vmalloc space\n", |
29a38193 | 835 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); |
ae8f1541 RK |
836 | } |
837 | ||
d5c98176 | 838 | type = &mem_types[md->type]; |
ae8f1541 | 839 | |
1b6ba46b | 840 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
841 | /* |
842 | * Catch 36-bit addresses | |
843 | */ | |
4a56c1e4 RK |
844 | if (md->pfn >= 0x100000) { |
845 | create_36bit_mapping(md, type); | |
846 | return; | |
ae8f1541 | 847 | } |
1b6ba46b | 848 | #endif |
ae8f1541 | 849 | |
7b9c7b4d | 850 | addr = md->virtual & PAGE_MASK; |
cae6292b | 851 | phys = __pfn_to_phys(md->pfn); |
7b9c7b4d | 852 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 853 | |
24e6c699 | 854 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
29a38193 | 855 | printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " |
ae8f1541 | 856 | "be mapped using pages, ignoring.\n", |
29a38193 | 857 | (long long)__pfn_to_phys(md->pfn), addr); |
ae8f1541 RK |
858 | return; |
859 | } | |
860 | ||
24e6c699 RK |
861 | pgd = pgd_offset_k(addr); |
862 | end = addr + length; | |
863 | do { | |
864 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 865 | |
516295e5 | 866 | alloc_init_pud(pgd, addr, next, phys, type); |
ae8f1541 | 867 | |
24e6c699 RK |
868 | phys += next - addr; |
869 | addr = next; | |
870 | } while (pgd++, addr != end); | |
ae8f1541 RK |
871 | } |
872 | ||
873 | /* | |
874 | * Create the architecture specific mappings | |
875 | */ | |
876 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
877 | { | |
0536bdf3 NP |
878 | struct map_desc *md; |
879 | struct vm_struct *vm; | |
101eeda3 | 880 | struct static_vm *svm; |
0536bdf3 NP |
881 | |
882 | if (!nr) | |
883 | return; | |
ae8f1541 | 884 | |
101eeda3 | 885 | svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm)); |
0536bdf3 NP |
886 | |
887 | for (md = io_desc; nr; md++, nr--) { | |
888 | create_mapping(md); | |
101eeda3 JK |
889 | |
890 | vm = &svm->vm; | |
0536bdf3 NP |
891 | vm->addr = (void *)(md->virtual & PAGE_MASK); |
892 | vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); | |
c2794437 RH |
893 | vm->phys_addr = __pfn_to_phys(md->pfn); |
894 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; | |
576d2f25 | 895 | vm->flags |= VM_ARM_MTYPE(md->type); |
0536bdf3 | 896 | vm->caller = iotable_init; |
101eeda3 | 897 | add_static_vm_early(svm++); |
0536bdf3 | 898 | } |
ae8f1541 RK |
899 | } |
900 | ||
c2794437 RH |
901 | void __init vm_reserve_area_early(unsigned long addr, unsigned long size, |
902 | void *caller) | |
903 | { | |
904 | struct vm_struct *vm; | |
101eeda3 JK |
905 | struct static_vm *svm; |
906 | ||
907 | svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm)); | |
c2794437 | 908 | |
101eeda3 | 909 | vm = &svm->vm; |
c2794437 RH |
910 | vm->addr = (void *)addr; |
911 | vm->size = size; | |
863e99a8 | 912 | vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING; |
c2794437 | 913 | vm->caller = caller; |
101eeda3 | 914 | add_static_vm_early(svm); |
c2794437 RH |
915 | } |
916 | ||
19b52abe NP |
917 | #ifndef CONFIG_ARM_LPAE |
918 | ||
919 | /* | |
920 | * The Linux PMD is made of two consecutive section entries covering 2MB | |
921 | * (see definition in include/asm/pgtable-2level.h). However a call to | |
922 | * create_mapping() may optimize static mappings by using individual | |
923 | * 1MB section mappings. This leaves the actual PMD potentially half | |
924 | * initialized if the top or bottom section entry isn't used, leaving it | |
925 | * open to problems if a subsequent ioremap() or vmalloc() tries to use | |
926 | * the virtual space left free by that unused section entry. | |
927 | * | |
928 | * Let's avoid the issue by inserting dummy vm entries covering the unused | |
929 | * PMD halves once the static mappings are in place. | |
930 | */ | |
931 | ||
932 | static void __init pmd_empty_section_gap(unsigned long addr) | |
933 | { | |
c2794437 | 934 | vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); |
19b52abe NP |
935 | } |
936 | ||
937 | static void __init fill_pmd_gaps(void) | |
938 | { | |
101eeda3 | 939 | struct static_vm *svm; |
19b52abe NP |
940 | struct vm_struct *vm; |
941 | unsigned long addr, next = 0; | |
942 | pmd_t *pmd; | |
943 | ||
101eeda3 JK |
944 | list_for_each_entry(svm, &static_vmlist, list) { |
945 | vm = &svm->vm; | |
19b52abe NP |
946 | addr = (unsigned long)vm->addr; |
947 | if (addr < next) | |
948 | continue; | |
949 | ||
950 | /* | |
951 | * Check if this vm starts on an odd section boundary. | |
952 | * If so and the first section entry for this PMD is free | |
953 | * then we block the corresponding virtual address. | |
954 | */ | |
955 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
956 | pmd = pmd_off_k(addr); | |
957 | if (pmd_none(*pmd)) | |
958 | pmd_empty_section_gap(addr & PMD_MASK); | |
959 | } | |
960 | ||
961 | /* | |
962 | * Then check if this vm ends on an odd section boundary. | |
963 | * If so and the second section entry for this PMD is empty | |
964 | * then we block the corresponding virtual address. | |
965 | */ | |
966 | addr += vm->size; | |
967 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
968 | pmd = pmd_off_k(addr) + 1; | |
969 | if (pmd_none(*pmd)) | |
970 | pmd_empty_section_gap(addr); | |
971 | } | |
972 | ||
973 | /* no need to look at any vm entry until we hit the next PMD */ | |
974 | next = (addr + PMD_SIZE - 1) & PMD_MASK; | |
975 | } | |
976 | } | |
977 | ||
978 | #else | |
979 | #define fill_pmd_gaps() do { } while (0) | |
980 | #endif | |
981 | ||
c2794437 RH |
982 | #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) |
983 | static void __init pci_reserve_io(void) | |
984 | { | |
101eeda3 | 985 | struct static_vm *svm; |
c2794437 | 986 | |
101eeda3 JK |
987 | svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE); |
988 | if (svm) | |
989 | return; | |
c2794437 | 990 | |
c2794437 RH |
991 | vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); |
992 | } | |
993 | #else | |
994 | #define pci_reserve_io() do { } while (0) | |
995 | #endif | |
996 | ||
e5c5f2ad RH |
997 | #ifdef CONFIG_DEBUG_LL |
998 | void __init debug_ll_io_init(void) | |
999 | { | |
1000 | struct map_desc map; | |
1001 | ||
1002 | debug_ll_addr(&map.pfn, &map.virtual); | |
1003 | if (!map.pfn || !map.virtual) | |
1004 | return; | |
1005 | map.pfn = __phys_to_pfn(map.pfn); | |
1006 | map.virtual &= PAGE_MASK; | |
1007 | map.length = PAGE_SIZE; | |
1008 | map.type = MT_DEVICE; | |
ee4de5d9 | 1009 | iotable_init(&map, 1); |
e5c5f2ad RH |
1010 | } |
1011 | #endif | |
1012 | ||
0536bdf3 NP |
1013 | static void * __initdata vmalloc_min = |
1014 | (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); | |
6c5da7ac RK |
1015 | |
1016 | /* | |
1017 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
1018 | * bytes. This can be used to increase (or decrease) the vmalloc | |
0536bdf3 | 1019 | * area - the default is 240m. |
6c5da7ac | 1020 | */ |
2b0d8c25 | 1021 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 1022 | { |
79612395 | 1023 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
6c5da7ac RK |
1024 | |
1025 | if (vmalloc_reserve < SZ_16M) { | |
1026 | vmalloc_reserve = SZ_16M; | |
1027 | printk(KERN_WARNING | |
1028 | "vmalloc area too small, limiting to %luMB\n", | |
1029 | vmalloc_reserve >> 20); | |
1030 | } | |
9210807c NP |
1031 | |
1032 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { | |
1033 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); | |
1034 | printk(KERN_WARNING | |
1035 | "vmalloc area is too big, limiting to %luMB\n", | |
1036 | vmalloc_reserve >> 20); | |
1037 | } | |
79612395 RK |
1038 | |
1039 | vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); | |
2b0d8c25 | 1040 | return 0; |
6c5da7ac | 1041 | } |
2b0d8c25 | 1042 | early_param("vmalloc", early_vmalloc); |
6c5da7ac | 1043 | |
c7909509 | 1044 | phys_addr_t arm_lowmem_limit __initdata = 0; |
8df65168 | 1045 | |
0371d3f7 | 1046 | void __init sanity_check_meminfo(void) |
60296c71 | 1047 | { |
c65b7e98 | 1048 | phys_addr_t memblock_limit = 0; |
dde5828f | 1049 | int i, j, highmem = 0; |
82f66704 | 1050 | phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1; |
60296c71 | 1051 | |
4b5f32ce | 1052 | for (i = 0, j = 0; i < meminfo.nr_banks; i++) { |
a1bbaec0 | 1053 | struct membank *bank = &meminfo.bank[j]; |
28d4bf7a | 1054 | phys_addr_t size_limit; |
60296c71 | 1055 | |
a1bbaec0 | 1056 | *bank = meminfo.bank[i]; |
28d4bf7a | 1057 | size_limit = bank->size; |
77f73a2c | 1058 | |
82f66704 | 1059 | if (bank->start >= vmalloc_limit) |
dde5828f | 1060 | highmem = 1; |
28d4bf7a CC |
1061 | else |
1062 | size_limit = vmalloc_limit - bank->start; | |
dde5828f RK |
1063 | |
1064 | bank->highmem = highmem; | |
1065 | ||
adf2e9fd | 1066 | #ifdef CONFIG_HIGHMEM |
a1bbaec0 NP |
1067 | /* |
1068 | * Split those memory banks which are partially overlapping | |
1069 | * the vmalloc area greatly simplifying things later. | |
1070 | */ | |
28d4bf7a | 1071 | if (!highmem && bank->size > size_limit) { |
a1bbaec0 NP |
1072 | if (meminfo.nr_banks >= NR_BANKS) { |
1073 | printk(KERN_CRIT "NR_BANKS too low, " | |
1074 | "ignoring high memory\n"); | |
1075 | } else { | |
1076 | memmove(bank + 1, bank, | |
1077 | (meminfo.nr_banks - i) * sizeof(*bank)); | |
1078 | meminfo.nr_banks++; | |
1079 | i++; | |
28d4bf7a | 1080 | bank[1].size -= size_limit; |
82f66704 | 1081 | bank[1].start = vmalloc_limit; |
dde5828f | 1082 | bank[1].highmem = highmem = 1; |
a1bbaec0 NP |
1083 | j++; |
1084 | } | |
28d4bf7a | 1085 | bank->size = size_limit; |
a1bbaec0 NP |
1086 | } |
1087 | #else | |
77f73a2c WD |
1088 | /* |
1089 | * Highmem banks not allowed with !CONFIG_HIGHMEM. | |
1090 | */ | |
1091 | if (highmem) { | |
1092 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " | |
1093 | "(!CONFIG_HIGHMEM).\n", | |
1094 | (unsigned long long)bank->start, | |
1095 | (unsigned long long)bank->start + bank->size - 1); | |
1096 | continue; | |
1097 | } | |
1098 | ||
a1bbaec0 NP |
1099 | /* |
1100 | * Check whether this memory bank would partially overlap | |
1101 | * the vmalloc area. | |
1102 | */ | |
28d4bf7a | 1103 | if (bank->size > size_limit) { |
e33b9d08 RK |
1104 | printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " |
1105 | "to -%.8llx (vmalloc region overlap).\n", | |
1106 | (unsigned long long)bank->start, | |
1107 | (unsigned long long)bank->start + bank->size - 1, | |
28d4bf7a CC |
1108 | (unsigned long long)bank->start + size_limit - 1); |
1109 | bank->size = size_limit; | |
a1bbaec0 NP |
1110 | } |
1111 | #endif | |
c65b7e98 RK |
1112 | if (!bank->highmem) { |
1113 | phys_addr_t bank_end = bank->start + bank->size; | |
40f7bfe4 | 1114 | |
c65b7e98 RK |
1115 | if (bank_end > arm_lowmem_limit) |
1116 | arm_lowmem_limit = bank_end; | |
1117 | ||
1118 | /* | |
1119 | * Find the first non-section-aligned page, and point | |
1120 | * memblock_limit at it. This relies on rounding the | |
1121 | * limit down to be section-aligned, which happens at | |
1122 | * the end of this function. | |
1123 | * | |
1124 | * With this algorithm, the start or end of almost any | |
1125 | * bank can be non-section-aligned. The only exception | |
1126 | * is that the start of the bank 0 must be section- | |
1127 | * aligned, since otherwise memory would need to be | |
1128 | * allocated when mapping the start of bank 0, which | |
1129 | * occurs before any free memory is mapped. | |
1130 | */ | |
1131 | if (!memblock_limit) { | |
1132 | if (!IS_ALIGNED(bank->start, SECTION_SIZE)) | |
1133 | memblock_limit = bank->start; | |
1134 | else if (!IS_ALIGNED(bank_end, SECTION_SIZE)) | |
1135 | memblock_limit = bank_end; | |
1136 | } | |
1137 | } | |
a1bbaec0 | 1138 | j++; |
60296c71 | 1139 | } |
e616c591 RK |
1140 | #ifdef CONFIG_HIGHMEM |
1141 | if (highmem) { | |
1142 | const char *reason = NULL; | |
1143 | ||
1144 | if (cache_is_vipt_aliasing()) { | |
1145 | /* | |
1146 | * Interactions between kmap and other mappings | |
1147 | * make highmem support with aliasing VIPT caches | |
1148 | * rather difficult. | |
1149 | */ | |
1150 | reason = "with VIPT aliasing cache"; | |
e616c591 RK |
1151 | } |
1152 | if (reason) { | |
1153 | printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", | |
1154 | reason); | |
1155 | while (j > 0 && meminfo.bank[j - 1].highmem) | |
1156 | j--; | |
1157 | } | |
1158 | } | |
1159 | #endif | |
4b5f32ce | 1160 | meminfo.nr_banks = j; |
c7909509 | 1161 | high_memory = __va(arm_lowmem_limit - 1) + 1; |
c65b7e98 RK |
1162 | |
1163 | /* | |
1164 | * Round the memblock limit down to a section size. This | |
1165 | * helps to ensure that we will allocate memory from the | |
1166 | * last full section, which should be mapped. | |
1167 | */ | |
1168 | if (memblock_limit) | |
1169 | memblock_limit = round_down(memblock_limit, SECTION_SIZE); | |
1170 | if (!memblock_limit) | |
1171 | memblock_limit = arm_lowmem_limit; | |
1172 | ||
1173 | memblock_set_current_limit(memblock_limit); | |
60296c71 LB |
1174 | } |
1175 | ||
4b5f32ce | 1176 | static inline void prepare_page_table(void) |
d111e8f9 RK |
1177 | { |
1178 | unsigned long addr; | |
8df65168 | 1179 | phys_addr_t end; |
d111e8f9 RK |
1180 | |
1181 | /* | |
1182 | * Clear out all the mappings below the kernel image. | |
1183 | */ | |
e73fc88e | 1184 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
d111e8f9 RK |
1185 | pmd_clear(pmd_off_k(addr)); |
1186 | ||
1187 | #ifdef CONFIG_XIP_KERNEL | |
1188 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
e73fc88e | 1189 | addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; |
d111e8f9 | 1190 | #endif |
e73fc88e | 1191 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
d111e8f9 RK |
1192 | pmd_clear(pmd_off_k(addr)); |
1193 | ||
8df65168 RK |
1194 | /* |
1195 | * Find the end of the first block of lowmem. | |
1196 | */ | |
1197 | end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; | |
c7909509 MS |
1198 | if (end >= arm_lowmem_limit) |
1199 | end = arm_lowmem_limit; | |
8df65168 | 1200 | |
d111e8f9 RK |
1201 | /* |
1202 | * Clear out all the kernel space mappings, except for the first | |
0536bdf3 | 1203 | * memory bank, up to the vmalloc region. |
d111e8f9 | 1204 | */ |
8df65168 | 1205 | for (addr = __phys_to_virt(end); |
0536bdf3 | 1206 | addr < VMALLOC_START; addr += PMD_SIZE) |
d111e8f9 RK |
1207 | pmd_clear(pmd_off_k(addr)); |
1208 | } | |
1209 | ||
1b6ba46b CM |
1210 | #ifdef CONFIG_ARM_LPAE |
1211 | /* the first page is reserved for pgd */ | |
1212 | #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ | |
1213 | PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) | |
1214 | #else | |
e73fc88e | 1215 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
1b6ba46b | 1216 | #endif |
e73fc88e | 1217 | |
d111e8f9 | 1218 | /* |
2778f620 | 1219 | * Reserve the special regions of memory |
d111e8f9 | 1220 | */ |
2778f620 | 1221 | void __init arm_mm_memblock_reserve(void) |
d111e8f9 | 1222 | { |
d111e8f9 RK |
1223 | /* |
1224 | * Reserve the page tables. These are already in use, | |
1225 | * and can only be in node 0. | |
1226 | */ | |
e73fc88e | 1227 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
d111e8f9 | 1228 | |
d111e8f9 RK |
1229 | #ifdef CONFIG_SA1111 |
1230 | /* | |
1231 | * Because of the SA1111 DMA bug, we want to preserve our | |
1232 | * precious DMA-able memory... | |
1233 | */ | |
2778f620 | 1234 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
d111e8f9 | 1235 | #endif |
d111e8f9 RK |
1236 | } |
1237 | ||
1238 | /* | |
0536bdf3 NP |
1239 | * Set up the device mappings. Since we clear out the page tables for all |
1240 | * mappings above VMALLOC_START, we will remove any debug device mappings. | |
d111e8f9 RK |
1241 | * This means you have to be careful how you debug this function, or any |
1242 | * called function. This means you can't use any function or debugging | |
1243 | * method which may touch any device, otherwise the kernel _will_ crash. | |
1244 | */ | |
ff69a4c8 | 1245 | static void __init devicemaps_init(const struct machine_desc *mdesc) |
d111e8f9 RK |
1246 | { |
1247 | struct map_desc map; | |
1248 | unsigned long addr; | |
94e5a85b | 1249 | void *vectors; |
d111e8f9 RK |
1250 | |
1251 | /* | |
1252 | * Allocate the vector page early. | |
1253 | */ | |
19accfd3 | 1254 | vectors = early_alloc(PAGE_SIZE * 2); |
94e5a85b RK |
1255 | |
1256 | early_trap_init(vectors); | |
d111e8f9 | 1257 | |
0536bdf3 | 1258 | for (addr = VMALLOC_START; addr; addr += PMD_SIZE) |
d111e8f9 RK |
1259 | pmd_clear(pmd_off_k(addr)); |
1260 | ||
1261 | /* | |
1262 | * Map the kernel if it is XIP. | |
1263 | * It is always first in the modulearea. | |
1264 | */ | |
1265 | #ifdef CONFIG_XIP_KERNEL | |
1266 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 1267 | map.virtual = MODULES_VADDR; |
37efe642 | 1268 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
1269 | map.type = MT_ROM; |
1270 | create_mapping(&map); | |
1271 | #endif | |
1272 | ||
1273 | /* | |
1274 | * Map the cache flushing regions. | |
1275 | */ | |
1276 | #ifdef FLUSH_BASE | |
1277 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
1278 | map.virtual = FLUSH_BASE; | |
1279 | map.length = SZ_1M; | |
1280 | map.type = MT_CACHECLEAN; | |
1281 | create_mapping(&map); | |
1282 | #endif | |
1283 | #ifdef FLUSH_BASE_MINICACHE | |
1284 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
1285 | map.virtual = FLUSH_BASE_MINICACHE; | |
1286 | map.length = SZ_1M; | |
1287 | map.type = MT_MINICLEAN; | |
1288 | create_mapping(&map); | |
1289 | #endif | |
1290 | ||
1291 | /* | |
1292 | * Create a mapping for the machine vectors at the high-vectors | |
1293 | * location (0xffff0000). If we aren't using high-vectors, also | |
1294 | * create a mapping at the low-vectors virtual address. | |
1295 | */ | |
94e5a85b | 1296 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
d111e8f9 RK |
1297 | map.virtual = 0xffff0000; |
1298 | map.length = PAGE_SIZE; | |
a5463cd3 | 1299 | #ifdef CONFIG_KUSER_HELPERS |
d111e8f9 | 1300 | map.type = MT_HIGH_VECTORS; |
a5463cd3 RK |
1301 | #else |
1302 | map.type = MT_LOW_VECTORS; | |
1303 | #endif | |
d111e8f9 RK |
1304 | create_mapping(&map); |
1305 | ||
1306 | if (!vectors_high()) { | |
1307 | map.virtual = 0; | |
19accfd3 | 1308 | map.length = PAGE_SIZE * 2; |
d111e8f9 RK |
1309 | map.type = MT_LOW_VECTORS; |
1310 | create_mapping(&map); | |
1311 | } | |
1312 | ||
19accfd3 RK |
1313 | /* Now create a kernel read-only mapping */ |
1314 | map.pfn += 1; | |
1315 | map.virtual = 0xffff0000 + PAGE_SIZE; | |
1316 | map.length = PAGE_SIZE; | |
1317 | map.type = MT_LOW_VECTORS; | |
1318 | create_mapping(&map); | |
1319 | ||
d111e8f9 RK |
1320 | /* |
1321 | * Ask the machine support to map in the statically mapped devices. | |
1322 | */ | |
1323 | if (mdesc->map_io) | |
1324 | mdesc->map_io(); | |
bc37324e MR |
1325 | else |
1326 | debug_ll_io_init(); | |
19b52abe | 1327 | fill_pmd_gaps(); |
d111e8f9 | 1328 | |
c2794437 RH |
1329 | /* Reserve fixed i/o space in VMALLOC region */ |
1330 | pci_reserve_io(); | |
1331 | ||
d111e8f9 RK |
1332 | /* |
1333 | * Finally flush the caches and tlb to ensure that we're in a | |
1334 | * consistent state wrt the writebuffer. This also ensures that | |
1335 | * any write-allocated cache lines in the vector page are written | |
1336 | * back. After this point, we can start to touch devices again. | |
1337 | */ | |
1338 | local_flush_tlb_all(); | |
1339 | flush_cache_all(); | |
1340 | } | |
1341 | ||
d73cd428 NP |
1342 | static void __init kmap_init(void) |
1343 | { | |
1344 | #ifdef CONFIG_HIGHMEM | |
4bb2e27d RK |
1345 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
1346 | PKMAP_BASE, _PAGE_KERNEL_TABLE); | |
d73cd428 NP |
1347 | #endif |
1348 | } | |
1349 | ||
a2227120 RK |
1350 | static void __init map_lowmem(void) |
1351 | { | |
8df65168 | 1352 | struct memblock_region *reg; |
ebd4922e RK |
1353 | unsigned long kernel_x_start = round_down(__pa(_stext), SECTION_SIZE); |
1354 | unsigned long kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE); | |
a2227120 RK |
1355 | |
1356 | /* Map all the lowmem memory banks. */ | |
8df65168 RK |
1357 | for_each_memblock(memory, reg) { |
1358 | phys_addr_t start = reg->base; | |
1359 | phys_addr_t end = start + reg->size; | |
1360 | struct map_desc map; | |
1361 | ||
c7909509 MS |
1362 | if (end > arm_lowmem_limit) |
1363 | end = arm_lowmem_limit; | |
8df65168 RK |
1364 | if (start >= end) |
1365 | break; | |
1366 | ||
ebd4922e RK |
1367 | if (end < kernel_x_start || start >= kernel_x_end) { |
1368 | map.pfn = __phys_to_pfn(start); | |
1369 | map.virtual = __phys_to_virt(start); | |
1370 | map.length = end - start; | |
1371 | map.type = MT_MEMORY_RWX; | |
a2227120 | 1372 | |
ebd4922e RK |
1373 | create_mapping(&map); |
1374 | } else { | |
1375 | /* This better cover the entire kernel */ | |
1376 | if (start < kernel_x_start) { | |
1377 | map.pfn = __phys_to_pfn(start); | |
1378 | map.virtual = __phys_to_virt(start); | |
1379 | map.length = kernel_x_start - start; | |
1380 | map.type = MT_MEMORY_RW; | |
1381 | ||
1382 | create_mapping(&map); | |
1383 | } | |
1384 | ||
1385 | map.pfn = __phys_to_pfn(kernel_x_start); | |
1386 | map.virtual = __phys_to_virt(kernel_x_start); | |
1387 | map.length = kernel_x_end - kernel_x_start; | |
1388 | map.type = MT_MEMORY_RWX; | |
1389 | ||
1390 | create_mapping(&map); | |
1391 | ||
1392 | if (kernel_x_end < end) { | |
1393 | map.pfn = __phys_to_pfn(kernel_x_end); | |
1394 | map.virtual = __phys_to_virt(kernel_x_end); | |
1395 | map.length = end - kernel_x_end; | |
1396 | map.type = MT_MEMORY_RW; | |
1397 | ||
1398 | create_mapping(&map); | |
1399 | } | |
1400 | } | |
a2227120 RK |
1401 | } |
1402 | } | |
1403 | ||
a77e0c7b SS |
1404 | #ifdef CONFIG_ARM_LPAE |
1405 | /* | |
1406 | * early_paging_init() recreates boot time page table setup, allowing machines | |
1407 | * to switch over to a high (>4G) address space on LPAE systems | |
1408 | */ | |
1409 | void __init early_paging_init(const struct machine_desc *mdesc, | |
1410 | struct proc_info_list *procinfo) | |
1411 | { | |
1412 | pmdval_t pmdprot = procinfo->__cpu_mm_mmu_flags; | |
1413 | unsigned long map_start, map_end; | |
1414 | pgd_t *pgd0, *pgdk; | |
1415 | pud_t *pud0, *pudk, *pud_start; | |
1416 | pmd_t *pmd0, *pmdk; | |
1417 | phys_addr_t phys; | |
1418 | int i; | |
1419 | ||
1420 | if (!(mdesc->init_meminfo)) | |
1421 | return; | |
1422 | ||
1423 | /* remap kernel code and data */ | |
1424 | map_start = init_mm.start_code; | |
1425 | map_end = init_mm.brk; | |
1426 | ||
1427 | /* get a handle on things... */ | |
1428 | pgd0 = pgd_offset_k(0); | |
1429 | pud_start = pud0 = pud_offset(pgd0, 0); | |
1430 | pmd0 = pmd_offset(pud0, 0); | |
1431 | ||
1432 | pgdk = pgd_offset_k(map_start); | |
1433 | pudk = pud_offset(pgdk, map_start); | |
1434 | pmdk = pmd_offset(pudk, map_start); | |
1435 | ||
1436 | mdesc->init_meminfo(); | |
1437 | ||
1438 | /* Run the patch stub to update the constants */ | |
1439 | fixup_pv_table(&__pv_table_begin, | |
1440 | (&__pv_table_end - &__pv_table_begin) << 2); | |
1441 | ||
1442 | /* | |
1443 | * Cache cleaning operations for self-modifying code | |
1444 | * We should clean the entries by MVA but running a | |
1445 | * for loop over every pv_table entry pointer would | |
1446 | * just complicate the code. | |
1447 | */ | |
1448 | flush_cache_louis(); | |
1449 | dsb(); | |
1450 | isb(); | |
1451 | ||
1452 | /* remap level 1 table */ | |
1453 | for (i = 0; i < PTRS_PER_PGD; pud0++, i++) { | |
1454 | set_pud(pud0, | |
1455 | __pud(__pa(pmd0) | PMD_TYPE_TABLE | L_PGD_SWAPPER)); | |
1456 | pmd0 += PTRS_PER_PMD; | |
1457 | } | |
1458 | ||
1459 | /* remap pmds for kernel mapping */ | |
1460 | phys = __pa(map_start) & PMD_MASK; | |
1461 | do { | |
1462 | *pmdk++ = __pmd(phys | pmdprot); | |
1463 | phys += PMD_SIZE; | |
1464 | } while (phys < map_end); | |
1465 | ||
1466 | flush_cache_all(); | |
1467 | cpu_switch_mm(pgd0, &init_mm); | |
1468 | cpu_set_ttbr(1, __pa(pgd0) + TTBR1_OFFSET); | |
1469 | local_flush_bp_all(); | |
1470 | local_flush_tlb_all(); | |
1471 | } | |
1472 | ||
1473 | #else | |
1474 | ||
1475 | void __init early_paging_init(const struct machine_desc *mdesc, | |
1476 | struct proc_info_list *procinfo) | |
1477 | { | |
1478 | if (mdesc->init_meminfo) | |
1479 | mdesc->init_meminfo(); | |
1480 | } | |
1481 | ||
1482 | #endif | |
1483 | ||
d111e8f9 RK |
1484 | /* |
1485 | * paging_init() sets up the page tables, initialises the zone memory | |
1486 | * maps, and sets up the zero page, bad page and bad page tables. | |
1487 | */ | |
ff69a4c8 | 1488 | void __init paging_init(const struct machine_desc *mdesc) |
d111e8f9 RK |
1489 | { |
1490 | void *zero_page; | |
1491 | ||
1492 | build_mem_type_table(); | |
4b5f32ce | 1493 | prepare_page_table(); |
a2227120 | 1494 | map_lowmem(); |
c7909509 | 1495 | dma_contiguous_remap(); |
d111e8f9 | 1496 | devicemaps_init(mdesc); |
d73cd428 | 1497 | kmap_init(); |
de40614e | 1498 | tcm_init(); |
d111e8f9 RK |
1499 | |
1500 | top_pmd = pmd_off_k(0xffff0000); | |
1501 | ||
3abe9d33 RK |
1502 | /* allocate the zero page. */ |
1503 | zero_page = early_alloc(PAGE_SIZE); | |
2778f620 | 1504 | |
8d717a52 | 1505 | bootmem_init(); |
2778f620 | 1506 | |
d111e8f9 | 1507 | empty_zero_page = virt_to_page(zero_page); |
421fe93c | 1508 | __flush_dcache_page(NULL, empty_zero_page); |
d111e8f9 | 1509 | } |