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d111e8f9 RK |
1 | /* |
2 | * linux/arch/arm/mm/mmu.c | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ae8f1541 | 10 | #include <linux/module.h> |
d111e8f9 RK |
11 | #include <linux/kernel.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/init.h> | |
d111e8f9 RK |
14 | #include <linux/mman.h> |
15 | #include <linux/nodemask.h> | |
2778f620 | 16 | #include <linux/memblock.h> |
d907387c | 17 | #include <linux/fs.h> |
0536bdf3 | 18 | #include <linux/vmalloc.h> |
d111e8f9 | 19 | |
0ba8b9b2 | 20 | #include <asm/cputype.h> |
37efe642 | 21 | #include <asm/sections.h> |
3f973e22 | 22 | #include <asm/cachetype.h> |
d111e8f9 RK |
23 | #include <asm/setup.h> |
24 | #include <asm/sizes.h> | |
e616c591 | 25 | #include <asm/smp_plat.h> |
d111e8f9 | 26 | #include <asm/tlb.h> |
d73cd428 | 27 | #include <asm/highmem.h> |
247055aa | 28 | #include <asm/traps.h> |
d111e8f9 RK |
29 | |
30 | #include <asm/mach/arch.h> | |
31 | #include <asm/mach/map.h> | |
32 | ||
33 | #include "mm.h" | |
34 | ||
d111e8f9 RK |
35 | /* |
36 | * empty_zero_page is a special page that is used for | |
37 | * zero-initialized data and COW. | |
38 | */ | |
39 | struct page *empty_zero_page; | |
3653f3ab | 40 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
41 | |
42 | /* | |
43 | * The pmd table for the upper-most set of pages. | |
44 | */ | |
45 | pmd_t *top_pmd; | |
46 | ||
ae8f1541 RK |
47 | #define CPOLICY_UNCACHED 0 |
48 | #define CPOLICY_BUFFERED 1 | |
49 | #define CPOLICY_WRITETHROUGH 2 | |
50 | #define CPOLICY_WRITEBACK 3 | |
51 | #define CPOLICY_WRITEALLOC 4 | |
52 | ||
53 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
54 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 55 | pgprot_t pgprot_user; |
ae8f1541 RK |
56 | pgprot_t pgprot_kernel; |
57 | ||
44b18693 | 58 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
59 | EXPORT_SYMBOL(pgprot_kernel); |
60 | ||
61 | struct cachepolicy { | |
62 | const char policy[16]; | |
63 | unsigned int cr_mask; | |
442e70c0 | 64 | pmdval_t pmd; |
f6e3354d | 65 | pteval_t pte; |
ae8f1541 RK |
66 | }; |
67 | ||
68 | static struct cachepolicy cache_policies[] __initdata = { | |
69 | { | |
70 | .policy = "uncached", | |
71 | .cr_mask = CR_W|CR_C, | |
72 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 73 | .pte = L_PTE_MT_UNCACHED, |
ae8f1541 RK |
74 | }, { |
75 | .policy = "buffered", | |
76 | .cr_mask = CR_C, | |
77 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 78 | .pte = L_PTE_MT_BUFFERABLE, |
ae8f1541 RK |
79 | }, { |
80 | .policy = "writethrough", | |
81 | .cr_mask = 0, | |
82 | .pmd = PMD_SECT_WT, | |
bb30f36f | 83 | .pte = L_PTE_MT_WRITETHROUGH, |
ae8f1541 RK |
84 | }, { |
85 | .policy = "writeback", | |
86 | .cr_mask = 0, | |
87 | .pmd = PMD_SECT_WB, | |
bb30f36f | 88 | .pte = L_PTE_MT_WRITEBACK, |
ae8f1541 RK |
89 | }, { |
90 | .policy = "writealloc", | |
91 | .cr_mask = 0, | |
92 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 93 | .pte = L_PTE_MT_WRITEALLOC, |
ae8f1541 RK |
94 | } |
95 | }; | |
96 | ||
97 | /* | |
6cbdc8c5 | 98 | * These are useful for identifying cache coherency |
ae8f1541 RK |
99 | * problems by allowing the cache or the cache and |
100 | * writebuffer to be turned off. (Note: the write | |
101 | * buffer should not be on and the cache off). | |
102 | */ | |
2b0d8c25 | 103 | static int __init early_cachepolicy(char *p) |
ae8f1541 RK |
104 | { |
105 | int i; | |
106 | ||
107 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { | |
108 | int len = strlen(cache_policies[i].policy); | |
109 | ||
2b0d8c25 | 110 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ae8f1541 RK |
111 | cachepolicy = i; |
112 | cr_alignment &= ~cache_policies[i].cr_mask; | |
113 | cr_no_alignment &= ~cache_policies[i].cr_mask; | |
ae8f1541 RK |
114 | break; |
115 | } | |
116 | } | |
117 | if (i == ARRAY_SIZE(cache_policies)) | |
118 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); | |
4b46d641 RK |
119 | /* |
120 | * This restriction is partly to do with the way we boot; it is | |
121 | * unpredictable to have memory mapped using two different sets of | |
122 | * memory attributes (shared, type, and cache attribs). We can not | |
123 | * change these attributes once the initial assembly has setup the | |
124 | * page tables. | |
125 | */ | |
11179d8c CM |
126 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
127 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); | |
128 | cachepolicy = CPOLICY_WRITEBACK; | |
129 | } | |
ae8f1541 RK |
130 | flush_cache_all(); |
131 | set_cr(cr_alignment); | |
2b0d8c25 | 132 | return 0; |
ae8f1541 | 133 | } |
2b0d8c25 | 134 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 135 | |
2b0d8c25 | 136 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
137 | { |
138 | char *p = "buffered"; | |
139 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
140 | early_cachepolicy(p); |
141 | return 0; | |
ae8f1541 | 142 | } |
2b0d8c25 | 143 | early_param("nocache", early_nocache); |
ae8f1541 | 144 | |
2b0d8c25 | 145 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
146 | { |
147 | char *p = "uncached"; | |
148 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
149 | early_cachepolicy(p); |
150 | return 0; | |
ae8f1541 | 151 | } |
2b0d8c25 | 152 | early_param("nowb", early_nowrite); |
ae8f1541 | 153 | |
2b0d8c25 | 154 | static int __init early_ecc(char *p) |
ae8f1541 | 155 | { |
2b0d8c25 | 156 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 157 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 158 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 159 | ecc_mask = 0; |
2b0d8c25 | 160 | return 0; |
ae8f1541 | 161 | } |
2b0d8c25 | 162 | early_param("ecc", early_ecc); |
ae8f1541 RK |
163 | |
164 | static int __init noalign_setup(char *__unused) | |
165 | { | |
166 | cr_alignment &= ~CR_A; | |
167 | cr_no_alignment &= ~CR_A; | |
168 | set_cr(cr_alignment); | |
169 | return 1; | |
170 | } | |
171 | __setup("noalign", noalign_setup); | |
172 | ||
255d1f86 RK |
173 | #ifndef CONFIG_SMP |
174 | void adjust_cr(unsigned long mask, unsigned long set) | |
175 | { | |
176 | unsigned long flags; | |
177 | ||
178 | mask &= ~CR_A; | |
179 | ||
180 | set &= mask; | |
181 | ||
182 | local_irq_save(flags); | |
183 | ||
184 | cr_no_alignment = (cr_no_alignment & ~mask) | set; | |
185 | cr_alignment = (cr_alignment & ~mask) | set; | |
186 | ||
187 | set_cr((get_cr() & ~mask) | set); | |
188 | ||
189 | local_irq_restore(flags); | |
190 | } | |
191 | #endif | |
192 | ||
36bb94ba | 193 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
b1cce6b1 | 194 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 195 | |
b29e9f5e | 196 | static struct mem_type mem_types[] = { |
0af92bef | 197 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
198 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
199 | L_PTE_SHARED, | |
0af92bef | 200 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 201 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
202 | .domain = DOMAIN_IO, |
203 | }, | |
204 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 205 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 206 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 207 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
208 | .domain = DOMAIN_IO, |
209 | }, | |
210 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 211 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
212 | .prot_l1 = PMD_TYPE_TABLE, |
213 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
214 | .domain = DOMAIN_IO, | |
215 | }, | |
1ad77a87 | 216 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 217 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 218 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 219 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 220 | .domain = DOMAIN_IO, |
ae8f1541 | 221 | }, |
ebb4c658 RK |
222 | [MT_UNCACHED] = { |
223 | .prot_pte = PROT_PTE_DEVICE, | |
224 | .prot_l1 = PMD_TYPE_TABLE, | |
225 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
226 | .domain = DOMAIN_IO, | |
227 | }, | |
ae8f1541 | 228 | [MT_CACHECLEAN] = { |
9ef79635 | 229 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
230 | .domain = DOMAIN_KERNEL, |
231 | }, | |
232 | [MT_MINICLEAN] = { | |
9ef79635 | 233 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
234 | .domain = DOMAIN_KERNEL, |
235 | }, | |
236 | [MT_LOW_VECTORS] = { | |
237 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 238 | L_PTE_RDONLY, |
ae8f1541 RK |
239 | .prot_l1 = PMD_TYPE_TABLE, |
240 | .domain = DOMAIN_USER, | |
241 | }, | |
242 | [MT_HIGH_VECTORS] = { | |
243 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 244 | L_PTE_USER | L_PTE_RDONLY, |
ae8f1541 RK |
245 | .prot_l1 = PMD_TYPE_TABLE, |
246 | .domain = DOMAIN_USER, | |
247 | }, | |
248 | [MT_MEMORY] = { | |
36bb94ba | 249 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
f1a2481c | 250 | .prot_l1 = PMD_TYPE_TABLE, |
9ef79635 | 251 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
252 | .domain = DOMAIN_KERNEL, |
253 | }, | |
254 | [MT_ROM] = { | |
9ef79635 | 255 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
256 | .domain = DOMAIN_KERNEL, |
257 | }, | |
e4707dd3 | 258 | [MT_MEMORY_NONCACHED] = { |
f1a2481c | 259 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 260 | L_PTE_MT_BUFFERABLE, |
f1a2481c | 261 | .prot_l1 = PMD_TYPE_TABLE, |
e4707dd3 PW |
262 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
263 | .domain = DOMAIN_KERNEL, | |
264 | }, | |
cb9d7707 | 265 | [MT_MEMORY_DTCM] = { |
f444fce3 | 266 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 267 | L_PTE_XN, |
f444fce3 LW |
268 | .prot_l1 = PMD_TYPE_TABLE, |
269 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
270 | .domain = DOMAIN_KERNEL, | |
cb9d7707 LW |
271 | }, |
272 | [MT_MEMORY_ITCM] = { | |
36bb94ba | 273 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
cb9d7707 | 274 | .prot_l1 = PMD_TYPE_TABLE, |
f444fce3 | 275 | .domain = DOMAIN_KERNEL, |
cb9d7707 | 276 | }, |
8fb54284 SS |
277 | [MT_MEMORY_SO] = { |
278 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
279 | L_PTE_MT_UNCACHED, | |
280 | .prot_l1 = PMD_TYPE_TABLE, | |
281 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | | |
282 | PMD_SECT_UNCACHED | PMD_SECT_XN, | |
283 | .domain = DOMAIN_KERNEL, | |
284 | }, | |
ae8f1541 RK |
285 | }; |
286 | ||
b29e9f5e RK |
287 | const struct mem_type *get_mem_type(unsigned int type) |
288 | { | |
289 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
290 | } | |
69d3a84a | 291 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 292 | |
ae8f1541 RK |
293 | /* |
294 | * Adjust the PMD section entries according to the CPU in use. | |
295 | */ | |
296 | static void __init build_mem_type_table(void) | |
297 | { | |
298 | struct cachepolicy *cp; | |
299 | unsigned int cr = get_cr(); | |
442e70c0 | 300 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
ae8f1541 RK |
301 | int cpu_arch = cpu_architecture(); |
302 | int i; | |
303 | ||
11179d8c | 304 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 305 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
306 | if (cachepolicy > CPOLICY_BUFFERED) |
307 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 308 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
309 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
310 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 311 | #endif |
11179d8c | 312 | } |
ae8f1541 RK |
313 | if (cpu_arch < CPU_ARCH_ARMv5) { |
314 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
315 | cachepolicy = CPOLICY_WRITEBACK; | |
316 | ecc_mask = 0; | |
317 | } | |
f00ec48f RK |
318 | if (is_smp()) |
319 | cachepolicy = CPOLICY_WRITEALLOC; | |
ae8f1541 | 320 | |
1ad77a87 | 321 | /* |
b1cce6b1 RK |
322 | * Strip out features not present on earlier architectures. |
323 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
324 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 325 | */ |
b1cce6b1 RK |
326 | if (cpu_arch < CPU_ARCH_ARMv5) |
327 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
328 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
329 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
330 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
331 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
332 | |
333 | /* | |
b1cce6b1 RK |
334 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
335 | * "update-able on write" bit on ARM610). However, Xscale and | |
336 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 337 | */ |
b1cce6b1 | 338 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
9ef79635 | 339 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 340 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
341 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
342 | } | |
343 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
344 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
345 | if (mem_types[i].prot_l1) |
346 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
347 | if (mem_types[i].prot_sect) |
348 | mem_types[i].prot_sect |= PMD_BIT4; | |
349 | } | |
350 | } | |
ae8f1541 | 351 | |
b1cce6b1 RK |
352 | /* |
353 | * Mark the device areas according to the CPU/architecture. | |
354 | */ | |
355 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
356 | if (!cpu_is_xsc3()) { | |
357 | /* | |
358 | * Mark device regions on ARMv6+ as execute-never | |
359 | * to prevent speculative instruction fetches. | |
360 | */ | |
361 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
362 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
363 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
364 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
365 | } | |
366 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
367 | /* | |
368 | * For ARMv7 with TEX remapping, | |
369 | * - shared device is SXCB=1100 | |
370 | * - nonshared device is SXCB=0100 | |
371 | * - write combine device mem is SXCB=0001 | |
372 | * (Uncached Normal memory) | |
373 | */ | |
374 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
375 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
376 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
377 | } else if (cpu_is_xsc3()) { | |
378 | /* | |
379 | * For Xscale3, | |
380 | * - shared device is TEXCB=00101 | |
381 | * - nonshared device is TEXCB=01000 | |
382 | * - write combine device mem is TEXCB=00100 | |
383 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
384 | */ | |
385 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
386 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
387 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
388 | } else { | |
389 | /* | |
390 | * For ARMv6 and ARMv7 without TEX remapping, | |
391 | * - shared device is TEXCB=00001 | |
392 | * - nonshared device is TEXCB=01000 | |
393 | * - write combine device mem is TEXCB=00100 | |
394 | * (Uncached Normal in ARMv6 parlance). | |
395 | */ | |
396 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
397 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
398 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
399 | } | |
400 | } else { | |
401 | /* | |
402 | * On others, write combining is "Uncached/Buffered" | |
403 | */ | |
404 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
405 | } | |
406 | ||
407 | /* | |
408 | * Now deal with the memory-type mappings | |
409 | */ | |
ae8f1541 | 410 | cp = &cache_policies[cachepolicy]; |
bb30f36f RK |
411 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
412 | ||
bb30f36f RK |
413 | /* |
414 | * Only use write-through for non-SMP systems | |
415 | */ | |
f00ec48f | 416 | if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) |
bb30f36f | 417 | vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; |
ae8f1541 RK |
418 | |
419 | /* | |
420 | * Enable CPU-specific coherency if supported. | |
421 | * (Only available on XSC3 at the moment.) | |
422 | */ | |
f1a2481c | 423 | if (arch_is_coherent() && cpu_is_xsc3()) { |
b1cce6b1 | 424 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
f1a2481c SS |
425 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; |
426 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; | |
427 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
428 | } | |
ae8f1541 RK |
429 | /* |
430 | * ARMv6 and above have extended page tables. | |
431 | */ | |
432 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
ae8f1541 RK |
433 | /* |
434 | * Mark cache clean areas and XIP ROM read only | |
435 | * from SVC mode and no access from userspace. | |
436 | */ | |
437 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
438 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
439 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
440 | ||
f00ec48f RK |
441 | if (is_smp()) { |
442 | /* | |
443 | * Mark memory with the "shared" attribute | |
444 | * for SMP systems | |
445 | */ | |
446 | user_pgprot |= L_PTE_SHARED; | |
447 | kern_pgprot |= L_PTE_SHARED; | |
448 | vecs_pgprot |= L_PTE_SHARED; | |
449 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; | |
450 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; | |
451 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; | |
452 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; | |
453 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; | |
454 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; | |
455 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; | |
456 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
457 | } | |
ae8f1541 RK |
458 | } |
459 | ||
e4707dd3 PW |
460 | /* |
461 | * Non-cacheable Normal - intended for memory areas that must | |
462 | * not cause dirty cache line writebacks when used | |
463 | */ | |
464 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
465 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
466 | /* Non-cacheable Normal is XCB = 001 */ | |
467 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
468 | PMD_SECT_BUFFERED; | |
469 | } else { | |
470 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
471 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
472 | PMD_SECT_TEX(1); | |
473 | } | |
474 | } else { | |
475 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; | |
476 | } | |
477 | ||
ae8f1541 RK |
478 | for (i = 0; i < 16; i++) { |
479 | unsigned long v = pgprot_val(protection_map[i]); | |
bb30f36f | 480 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
481 | } |
482 | ||
bb30f36f RK |
483 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
484 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 485 | |
44b18693 | 486 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 487 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
36bb94ba | 488 | L_PTE_DIRTY | kern_pgprot); |
ae8f1541 RK |
489 | |
490 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
491 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
492 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; | |
f1a2481c SS |
493 | mem_types[MT_MEMORY].prot_pte |= kern_pgprot; |
494 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; | |
ae8f1541 RK |
495 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
496 | ||
497 | switch (cp->pmd) { | |
498 | case PMD_SECT_WT: | |
499 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
500 | break; | |
501 | case PMD_SECT_WB: | |
502 | case PMD_SECT_WBWA: | |
503 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
504 | break; | |
505 | } | |
506 | printk("Memory policy: ECC %sabled, Data cache %s\n", | |
507 | ecc_mask ? "en" : "dis", cp->policy); | |
2497f0a8 RK |
508 | |
509 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
510 | struct mem_type *t = &mem_types[i]; | |
511 | if (t->prot_l1) | |
512 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
513 | if (t->prot_sect) | |
514 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
515 | } | |
ae8f1541 RK |
516 | } |
517 | ||
d907387c CM |
518 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
519 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
520 | unsigned long size, pgprot_t vma_prot) | |
521 | { | |
522 | if (!pfn_valid(pfn)) | |
523 | return pgprot_noncached(vma_prot); | |
524 | else if (file->f_flags & O_SYNC) | |
525 | return pgprot_writecombine(vma_prot); | |
526 | return vma_prot; | |
527 | } | |
528 | EXPORT_SYMBOL(phys_mem_access_prot); | |
529 | #endif | |
530 | ||
ae8f1541 RK |
531 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
532 | ||
0536bdf3 | 533 | static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) |
3abe9d33 | 534 | { |
0536bdf3 | 535 | void *ptr = __va(memblock_alloc(sz, align)); |
2778f620 RK |
536 | memset(ptr, 0, sz); |
537 | return ptr; | |
3abe9d33 RK |
538 | } |
539 | ||
0536bdf3 NP |
540 | static void __init *early_alloc(unsigned long sz) |
541 | { | |
542 | return early_alloc_aligned(sz, sz); | |
543 | } | |
544 | ||
4bb2e27d | 545 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) |
ae8f1541 | 546 | { |
24e6c699 | 547 | if (pmd_none(*pmd)) { |
410f1483 | 548 | pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
97092e0c | 549 | __pmd_populate(pmd, __pa(pte), prot); |
24e6c699 | 550 | } |
4bb2e27d RK |
551 | BUG_ON(pmd_bad(*pmd)); |
552 | return pte_offset_kernel(pmd, addr); | |
553 | } | |
ae8f1541 | 554 | |
4bb2e27d RK |
555 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
556 | unsigned long end, unsigned long pfn, | |
557 | const struct mem_type *type) | |
558 | { | |
559 | pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); | |
24e6c699 | 560 | do { |
40d192b6 | 561 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
24e6c699 RK |
562 | pfn++; |
563 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
564 | } |
565 | ||
516295e5 | 566 | static void __init alloc_init_section(pud_t *pud, unsigned long addr, |
97092e0c | 567 | unsigned long end, phys_addr_t phys, |
24e6c699 | 568 | const struct mem_type *type) |
ae8f1541 | 569 | { |
516295e5 | 570 | pmd_t *pmd = pmd_offset(pud, addr); |
ae8f1541 | 571 | |
24e6c699 RK |
572 | /* |
573 | * Try a section mapping - end, addr and phys must all be aligned | |
574 | * to a section boundary. Note that PMDs refer to the individual | |
575 | * L1 entries, whereas PGDs refer to a group of L1 entries making | |
576 | * up one logical pointer to an L2 table. | |
577 | */ | |
578 | if (((addr | end | phys) & ~SECTION_MASK) == 0) { | |
579 | pmd_t *p = pmd; | |
ae8f1541 | 580 | |
24e6c699 RK |
581 | if (addr & SECTION_SIZE) |
582 | pmd++; | |
583 | ||
584 | do { | |
585 | *pmd = __pmd(phys | type->prot_sect); | |
586 | phys += SECTION_SIZE; | |
587 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
ae8f1541 | 588 | |
24e6c699 RK |
589 | flush_pmd_entry(p); |
590 | } else { | |
591 | /* | |
592 | * No need to loop; pte's aren't interested in the | |
593 | * individual L1 entries. | |
594 | */ | |
595 | alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); | |
596 | } | |
ae8f1541 RK |
597 | } |
598 | ||
516295e5 RK |
599 | static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end, |
600 | unsigned long phys, const struct mem_type *type) | |
601 | { | |
602 | pud_t *pud = pud_offset(pgd, addr); | |
603 | unsigned long next; | |
604 | ||
605 | do { | |
606 | next = pud_addr_end(addr, end); | |
607 | alloc_init_section(pud, addr, next, phys, type); | |
608 | phys += next - addr; | |
609 | } while (pud++, addr = next, addr != end); | |
610 | } | |
611 | ||
4a56c1e4 RK |
612 | static void __init create_36bit_mapping(struct map_desc *md, |
613 | const struct mem_type *type) | |
614 | { | |
97092e0c RK |
615 | unsigned long addr, length, end; |
616 | phys_addr_t phys; | |
4a56c1e4 RK |
617 | pgd_t *pgd; |
618 | ||
619 | addr = md->virtual; | |
cae6292b | 620 | phys = __pfn_to_phys(md->pfn); |
4a56c1e4 RK |
621 | length = PAGE_ALIGN(md->length); |
622 | ||
623 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
624 | printk(KERN_ERR "MM: CPU does not support supersection " | |
625 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 626 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
627 | return; |
628 | } | |
629 | ||
630 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
631 | * Since domain assignments can in fact be arbitrary, the | |
632 | * 'domain == 0' check below is required to insure that ARMv6 | |
633 | * supersections are only allocated for domain 0 regardless | |
634 | * of the actual domain assignments in use. | |
635 | */ | |
636 | if (type->domain) { | |
637 | printk(KERN_ERR "MM: invalid domain in supersection " | |
638 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 639 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
640 | return; |
641 | } | |
642 | ||
643 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
29a38193 WD |
644 | printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" |
645 | " at 0x%08lx invalid alignment\n", | |
646 | (long long)__pfn_to_phys((u64)md->pfn), addr); | |
4a56c1e4 RK |
647 | return; |
648 | } | |
649 | ||
650 | /* | |
651 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
652 | * (See ARMv6 spec). | |
653 | */ | |
654 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
655 | ||
656 | pgd = pgd_offset_k(addr); | |
657 | end = addr + length; | |
658 | do { | |
516295e5 RK |
659 | pud_t *pud = pud_offset(pgd, addr); |
660 | pmd_t *pmd = pmd_offset(pud, addr); | |
4a56c1e4 RK |
661 | int i; |
662 | ||
663 | for (i = 0; i < 16; i++) | |
664 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); | |
665 | ||
666 | addr += SUPERSECTION_SIZE; | |
667 | phys += SUPERSECTION_SIZE; | |
668 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
669 | } while (addr != end); | |
670 | } | |
671 | ||
ae8f1541 RK |
672 | /* |
673 | * Create the page directory entries and any necessary | |
674 | * page tables for the mapping specified by `md'. We | |
675 | * are able to cope here with varying sizes and address | |
676 | * offsets, and we take full advantage of sections and | |
677 | * supersections. | |
678 | */ | |
a2227120 | 679 | static void __init create_mapping(struct map_desc *md) |
ae8f1541 | 680 | { |
cae6292b WD |
681 | unsigned long addr, length, end; |
682 | phys_addr_t phys; | |
d5c98176 | 683 | const struct mem_type *type; |
24e6c699 | 684 | pgd_t *pgd; |
ae8f1541 RK |
685 | |
686 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
29a38193 WD |
687 | printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" |
688 | " at 0x%08lx in user region\n", | |
689 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
ae8f1541 RK |
690 | return; |
691 | } | |
692 | ||
693 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
0536bdf3 NP |
694 | md->virtual >= PAGE_OFFSET && |
695 | (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { | |
29a38193 | 696 | printk(KERN_WARNING "BUG: mapping for 0x%08llx" |
0536bdf3 | 697 | " at 0x%08lx out of vmalloc space\n", |
29a38193 | 698 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); |
ae8f1541 RK |
699 | } |
700 | ||
d5c98176 | 701 | type = &mem_types[md->type]; |
ae8f1541 RK |
702 | |
703 | /* | |
704 | * Catch 36-bit addresses | |
705 | */ | |
4a56c1e4 RK |
706 | if (md->pfn >= 0x100000) { |
707 | create_36bit_mapping(md, type); | |
708 | return; | |
ae8f1541 RK |
709 | } |
710 | ||
7b9c7b4d | 711 | addr = md->virtual & PAGE_MASK; |
cae6292b | 712 | phys = __pfn_to_phys(md->pfn); |
7b9c7b4d | 713 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 714 | |
24e6c699 | 715 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
29a38193 | 716 | printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " |
ae8f1541 | 717 | "be mapped using pages, ignoring.\n", |
29a38193 | 718 | (long long)__pfn_to_phys(md->pfn), addr); |
ae8f1541 RK |
719 | return; |
720 | } | |
721 | ||
24e6c699 RK |
722 | pgd = pgd_offset_k(addr); |
723 | end = addr + length; | |
724 | do { | |
725 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 726 | |
516295e5 | 727 | alloc_init_pud(pgd, addr, next, phys, type); |
ae8f1541 | 728 | |
24e6c699 RK |
729 | phys += next - addr; |
730 | addr = next; | |
731 | } while (pgd++, addr != end); | |
ae8f1541 RK |
732 | } |
733 | ||
734 | /* | |
735 | * Create the architecture specific mappings | |
736 | */ | |
737 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
738 | { | |
0536bdf3 NP |
739 | struct map_desc *md; |
740 | struct vm_struct *vm; | |
741 | ||
742 | if (!nr) | |
743 | return; | |
ae8f1541 | 744 | |
0536bdf3 NP |
745 | vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm)); |
746 | ||
747 | for (md = io_desc; nr; md++, nr--) { | |
748 | create_mapping(md); | |
749 | vm->addr = (void *)(md->virtual & PAGE_MASK); | |
750 | vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); | |
751 | vm->phys_addr = __pfn_to_phys(md->pfn); | |
576d2f25 NP |
752 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; |
753 | vm->flags |= VM_ARM_MTYPE(md->type); | |
0536bdf3 NP |
754 | vm->caller = iotable_init; |
755 | vm_area_add_early(vm++); | |
756 | } | |
ae8f1541 RK |
757 | } |
758 | ||
0536bdf3 NP |
759 | static void * __initdata vmalloc_min = |
760 | (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); | |
6c5da7ac RK |
761 | |
762 | /* | |
763 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
764 | * bytes. This can be used to increase (or decrease) the vmalloc | |
0536bdf3 | 765 | * area - the default is 240m. |
6c5da7ac | 766 | */ |
2b0d8c25 | 767 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 768 | { |
79612395 | 769 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
6c5da7ac RK |
770 | |
771 | if (vmalloc_reserve < SZ_16M) { | |
772 | vmalloc_reserve = SZ_16M; | |
773 | printk(KERN_WARNING | |
774 | "vmalloc area too small, limiting to %luMB\n", | |
775 | vmalloc_reserve >> 20); | |
776 | } | |
9210807c NP |
777 | |
778 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { | |
779 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); | |
780 | printk(KERN_WARNING | |
781 | "vmalloc area is too big, limiting to %luMB\n", | |
782 | vmalloc_reserve >> 20); | |
783 | } | |
79612395 RK |
784 | |
785 | vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); | |
2b0d8c25 | 786 | return 0; |
6c5da7ac | 787 | } |
2b0d8c25 | 788 | early_param("vmalloc", early_vmalloc); |
6c5da7ac | 789 | |
8df65168 RK |
790 | static phys_addr_t lowmem_limit __initdata = 0; |
791 | ||
0371d3f7 | 792 | void __init sanity_check_meminfo(void) |
60296c71 | 793 | { |
dde5828f | 794 | int i, j, highmem = 0; |
60296c71 | 795 | |
4b5f32ce | 796 | for (i = 0, j = 0; i < meminfo.nr_banks; i++) { |
a1bbaec0 NP |
797 | struct membank *bank = &meminfo.bank[j]; |
798 | *bank = meminfo.bank[i]; | |
60296c71 | 799 | |
a1bbaec0 | 800 | #ifdef CONFIG_HIGHMEM |
40f7bfe4 | 801 | if (__va(bank->start) >= vmalloc_min || |
dde5828f RK |
802 | __va(bank->start) < (void *)PAGE_OFFSET) |
803 | highmem = 1; | |
804 | ||
805 | bank->highmem = highmem; | |
806 | ||
a1bbaec0 NP |
807 | /* |
808 | * Split those memory banks which are partially overlapping | |
809 | * the vmalloc area greatly simplifying things later. | |
810 | */ | |
79612395 RK |
811 | if (__va(bank->start) < vmalloc_min && |
812 | bank->size > vmalloc_min - __va(bank->start)) { | |
a1bbaec0 NP |
813 | if (meminfo.nr_banks >= NR_BANKS) { |
814 | printk(KERN_CRIT "NR_BANKS too low, " | |
815 | "ignoring high memory\n"); | |
816 | } else { | |
817 | memmove(bank + 1, bank, | |
818 | (meminfo.nr_banks - i) * sizeof(*bank)); | |
819 | meminfo.nr_banks++; | |
820 | i++; | |
79612395 RK |
821 | bank[1].size -= vmalloc_min - __va(bank->start); |
822 | bank[1].start = __pa(vmalloc_min - 1) + 1; | |
dde5828f | 823 | bank[1].highmem = highmem = 1; |
a1bbaec0 NP |
824 | j++; |
825 | } | |
79612395 | 826 | bank->size = vmalloc_min - __va(bank->start); |
a1bbaec0 NP |
827 | } |
828 | #else | |
041d785f RK |
829 | bank->highmem = highmem; |
830 | ||
a1bbaec0 NP |
831 | /* |
832 | * Check whether this memory bank would entirely overlap | |
833 | * the vmalloc area. | |
834 | */ | |
79612395 | 835 | if (__va(bank->start) >= vmalloc_min || |
f0bba9f9 | 836 | __va(bank->start) < (void *)PAGE_OFFSET) { |
e33b9d08 | 837 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " |
a1bbaec0 | 838 | "(vmalloc region overlap).\n", |
e33b9d08 RK |
839 | (unsigned long long)bank->start, |
840 | (unsigned long long)bank->start + bank->size - 1); | |
a1bbaec0 NP |
841 | continue; |
842 | } | |
60296c71 | 843 | |
a1bbaec0 NP |
844 | /* |
845 | * Check whether this memory bank would partially overlap | |
846 | * the vmalloc area. | |
847 | */ | |
79612395 | 848 | if (__va(bank->start + bank->size) > vmalloc_min || |
a1bbaec0 | 849 | __va(bank->start + bank->size) < __va(bank->start)) { |
79612395 | 850 | unsigned long newsize = vmalloc_min - __va(bank->start); |
e33b9d08 RK |
851 | printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " |
852 | "to -%.8llx (vmalloc region overlap).\n", | |
853 | (unsigned long long)bank->start, | |
854 | (unsigned long long)bank->start + bank->size - 1, | |
855 | (unsigned long long)bank->start + newsize - 1); | |
a1bbaec0 NP |
856 | bank->size = newsize; |
857 | } | |
858 | #endif | |
40f7bfe4 WD |
859 | if (!bank->highmem && bank->start + bank->size > lowmem_limit) |
860 | lowmem_limit = bank->start + bank->size; | |
861 | ||
a1bbaec0 | 862 | j++; |
60296c71 | 863 | } |
e616c591 RK |
864 | #ifdef CONFIG_HIGHMEM |
865 | if (highmem) { | |
866 | const char *reason = NULL; | |
867 | ||
868 | if (cache_is_vipt_aliasing()) { | |
869 | /* | |
870 | * Interactions between kmap and other mappings | |
871 | * make highmem support with aliasing VIPT caches | |
872 | * rather difficult. | |
873 | */ | |
874 | reason = "with VIPT aliasing cache"; | |
e616c591 RK |
875 | } |
876 | if (reason) { | |
877 | printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", | |
878 | reason); | |
879 | while (j > 0 && meminfo.bank[j - 1].highmem) | |
880 | j--; | |
881 | } | |
882 | } | |
883 | #endif | |
4b5f32ce | 884 | meminfo.nr_banks = j; |
55a8173c | 885 | high_memory = __va(lowmem_limit - 1) + 1; |
40f7bfe4 | 886 | memblock_set_current_limit(lowmem_limit); |
60296c71 LB |
887 | } |
888 | ||
4b5f32ce | 889 | static inline void prepare_page_table(void) |
d111e8f9 RK |
890 | { |
891 | unsigned long addr; | |
8df65168 | 892 | phys_addr_t end; |
d111e8f9 RK |
893 | |
894 | /* | |
895 | * Clear out all the mappings below the kernel image. | |
896 | */ | |
e73fc88e | 897 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
d111e8f9 RK |
898 | pmd_clear(pmd_off_k(addr)); |
899 | ||
900 | #ifdef CONFIG_XIP_KERNEL | |
901 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
e73fc88e | 902 | addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; |
d111e8f9 | 903 | #endif |
e73fc88e | 904 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
d111e8f9 RK |
905 | pmd_clear(pmd_off_k(addr)); |
906 | ||
8df65168 RK |
907 | /* |
908 | * Find the end of the first block of lowmem. | |
909 | */ | |
910 | end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; | |
911 | if (end >= lowmem_limit) | |
912 | end = lowmem_limit; | |
913 | ||
d111e8f9 RK |
914 | /* |
915 | * Clear out all the kernel space mappings, except for the first | |
0536bdf3 | 916 | * memory bank, up to the vmalloc region. |
d111e8f9 | 917 | */ |
8df65168 | 918 | for (addr = __phys_to_virt(end); |
0536bdf3 | 919 | addr < VMALLOC_START; addr += PMD_SIZE) |
d111e8f9 RK |
920 | pmd_clear(pmd_off_k(addr)); |
921 | } | |
922 | ||
e73fc88e CM |
923 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
924 | ||
d111e8f9 | 925 | /* |
2778f620 | 926 | * Reserve the special regions of memory |
d111e8f9 | 927 | */ |
2778f620 | 928 | void __init arm_mm_memblock_reserve(void) |
d111e8f9 | 929 | { |
d111e8f9 RK |
930 | /* |
931 | * Reserve the page tables. These are already in use, | |
932 | * and can only be in node 0. | |
933 | */ | |
e73fc88e | 934 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
d111e8f9 | 935 | |
d111e8f9 RK |
936 | #ifdef CONFIG_SA1111 |
937 | /* | |
938 | * Because of the SA1111 DMA bug, we want to preserve our | |
939 | * precious DMA-able memory... | |
940 | */ | |
2778f620 | 941 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
d111e8f9 | 942 | #endif |
d111e8f9 RK |
943 | } |
944 | ||
945 | /* | |
0536bdf3 NP |
946 | * Set up the device mappings. Since we clear out the page tables for all |
947 | * mappings above VMALLOC_START, we will remove any debug device mappings. | |
d111e8f9 RK |
948 | * This means you have to be careful how you debug this function, or any |
949 | * called function. This means you can't use any function or debugging | |
950 | * method which may touch any device, otherwise the kernel _will_ crash. | |
951 | */ | |
952 | static void __init devicemaps_init(struct machine_desc *mdesc) | |
953 | { | |
954 | struct map_desc map; | |
955 | unsigned long addr; | |
d111e8f9 RK |
956 | |
957 | /* | |
958 | * Allocate the vector page early. | |
959 | */ | |
247055aa | 960 | vectors_page = early_alloc(PAGE_SIZE); |
d111e8f9 | 961 | |
0536bdf3 | 962 | for (addr = VMALLOC_START; addr; addr += PMD_SIZE) |
d111e8f9 RK |
963 | pmd_clear(pmd_off_k(addr)); |
964 | ||
965 | /* | |
966 | * Map the kernel if it is XIP. | |
967 | * It is always first in the modulearea. | |
968 | */ | |
969 | #ifdef CONFIG_XIP_KERNEL | |
970 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 971 | map.virtual = MODULES_VADDR; |
37efe642 | 972 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
973 | map.type = MT_ROM; |
974 | create_mapping(&map); | |
975 | #endif | |
976 | ||
977 | /* | |
978 | * Map the cache flushing regions. | |
979 | */ | |
980 | #ifdef FLUSH_BASE | |
981 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
982 | map.virtual = FLUSH_BASE; | |
983 | map.length = SZ_1M; | |
984 | map.type = MT_CACHECLEAN; | |
985 | create_mapping(&map); | |
986 | #endif | |
987 | #ifdef FLUSH_BASE_MINICACHE | |
988 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
989 | map.virtual = FLUSH_BASE_MINICACHE; | |
990 | map.length = SZ_1M; | |
991 | map.type = MT_MINICLEAN; | |
992 | create_mapping(&map); | |
993 | #endif | |
994 | ||
995 | /* | |
996 | * Create a mapping for the machine vectors at the high-vectors | |
997 | * location (0xffff0000). If we aren't using high-vectors, also | |
998 | * create a mapping at the low-vectors virtual address. | |
999 | */ | |
247055aa | 1000 | map.pfn = __phys_to_pfn(virt_to_phys(vectors_page)); |
d111e8f9 RK |
1001 | map.virtual = 0xffff0000; |
1002 | map.length = PAGE_SIZE; | |
1003 | map.type = MT_HIGH_VECTORS; | |
1004 | create_mapping(&map); | |
1005 | ||
1006 | if (!vectors_high()) { | |
1007 | map.virtual = 0; | |
1008 | map.type = MT_LOW_VECTORS; | |
1009 | create_mapping(&map); | |
1010 | } | |
1011 | ||
1012 | /* | |
1013 | * Ask the machine support to map in the statically mapped devices. | |
1014 | */ | |
1015 | if (mdesc->map_io) | |
1016 | mdesc->map_io(); | |
1017 | ||
1018 | /* | |
1019 | * Finally flush the caches and tlb to ensure that we're in a | |
1020 | * consistent state wrt the writebuffer. This also ensures that | |
1021 | * any write-allocated cache lines in the vector page are written | |
1022 | * back. After this point, we can start to touch devices again. | |
1023 | */ | |
1024 | local_flush_tlb_all(); | |
1025 | flush_cache_all(); | |
1026 | } | |
1027 | ||
d73cd428 NP |
1028 | static void __init kmap_init(void) |
1029 | { | |
1030 | #ifdef CONFIG_HIGHMEM | |
4bb2e27d RK |
1031 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
1032 | PKMAP_BASE, _PAGE_KERNEL_TABLE); | |
d73cd428 NP |
1033 | #endif |
1034 | } | |
1035 | ||
a2227120 RK |
1036 | static void __init map_lowmem(void) |
1037 | { | |
8df65168 | 1038 | struct memblock_region *reg; |
a2227120 RK |
1039 | |
1040 | /* Map all the lowmem memory banks. */ | |
8df65168 RK |
1041 | for_each_memblock(memory, reg) { |
1042 | phys_addr_t start = reg->base; | |
1043 | phys_addr_t end = start + reg->size; | |
1044 | struct map_desc map; | |
1045 | ||
1046 | if (end > lowmem_limit) | |
1047 | end = lowmem_limit; | |
1048 | if (start >= end) | |
1049 | break; | |
1050 | ||
1051 | map.pfn = __phys_to_pfn(start); | |
1052 | map.virtual = __phys_to_virt(start); | |
1053 | map.length = end - start; | |
1054 | map.type = MT_MEMORY; | |
a2227120 | 1055 | |
8df65168 | 1056 | create_mapping(&map); |
a2227120 RK |
1057 | } |
1058 | } | |
1059 | ||
d111e8f9 RK |
1060 | /* |
1061 | * paging_init() sets up the page tables, initialises the zone memory | |
1062 | * maps, and sets up the zero page, bad page and bad page tables. | |
1063 | */ | |
4b5f32ce | 1064 | void __init paging_init(struct machine_desc *mdesc) |
d111e8f9 RK |
1065 | { |
1066 | void *zero_page; | |
1067 | ||
0371d3f7 RK |
1068 | memblock_set_current_limit(lowmem_limit); |
1069 | ||
d111e8f9 | 1070 | build_mem_type_table(); |
4b5f32ce | 1071 | prepare_page_table(); |
a2227120 | 1072 | map_lowmem(); |
d111e8f9 | 1073 | devicemaps_init(mdesc); |
d73cd428 | 1074 | kmap_init(); |
d111e8f9 RK |
1075 | |
1076 | top_pmd = pmd_off_k(0xffff0000); | |
1077 | ||
3abe9d33 RK |
1078 | /* allocate the zero page. */ |
1079 | zero_page = early_alloc(PAGE_SIZE); | |
2778f620 | 1080 | |
8d717a52 | 1081 | bootmem_init(); |
2778f620 | 1082 | |
d111e8f9 | 1083 | empty_zero_page = virt_to_page(zero_page); |
421fe93c | 1084 | __flush_dcache_page(NULL, empty_zero_page); |
d111e8f9 | 1085 | } |