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d111e8f9 RK |
1 | /* |
2 | * linux/arch/arm/mm/mmu.c | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ae8f1541 | 10 | #include <linux/module.h> |
d111e8f9 RK |
11 | #include <linux/kernel.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/init.h> | |
d111e8f9 RK |
14 | #include <linux/mman.h> |
15 | #include <linux/nodemask.h> | |
2778f620 | 16 | #include <linux/memblock.h> |
d907387c | 17 | #include <linux/fs.h> |
d111e8f9 | 18 | |
0ba8b9b2 | 19 | #include <asm/cputype.h> |
37efe642 | 20 | #include <asm/sections.h> |
3f973e22 | 21 | #include <asm/cachetype.h> |
d111e8f9 RK |
22 | #include <asm/setup.h> |
23 | #include <asm/sizes.h> | |
e616c591 | 24 | #include <asm/smp_plat.h> |
d111e8f9 | 25 | #include <asm/tlb.h> |
d73cd428 | 26 | #include <asm/highmem.h> |
247055aa | 27 | #include <asm/traps.h> |
d111e8f9 RK |
28 | |
29 | #include <asm/mach/arch.h> | |
30 | #include <asm/mach/map.h> | |
31 | ||
32 | #include "mm.h" | |
33 | ||
d111e8f9 RK |
34 | /* |
35 | * empty_zero_page is a special page that is used for | |
36 | * zero-initialized data and COW. | |
37 | */ | |
38 | struct page *empty_zero_page; | |
3653f3ab | 39 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
40 | |
41 | /* | |
42 | * The pmd table for the upper-most set of pages. | |
43 | */ | |
44 | pmd_t *top_pmd; | |
45 | ||
ae8f1541 RK |
46 | #define CPOLICY_UNCACHED 0 |
47 | #define CPOLICY_BUFFERED 1 | |
48 | #define CPOLICY_WRITETHROUGH 2 | |
49 | #define CPOLICY_WRITEBACK 3 | |
50 | #define CPOLICY_WRITEALLOC 4 | |
51 | ||
52 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
53 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 54 | pgprot_t pgprot_user; |
ae8f1541 RK |
55 | pgprot_t pgprot_kernel; |
56 | ||
44b18693 | 57 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
58 | EXPORT_SYMBOL(pgprot_kernel); |
59 | ||
60 | struct cachepolicy { | |
61 | const char policy[16]; | |
62 | unsigned int cr_mask; | |
442e70c0 | 63 | pmdval_t pmd; |
f6e3354d | 64 | pteval_t pte; |
ae8f1541 RK |
65 | }; |
66 | ||
67 | static struct cachepolicy cache_policies[] __initdata = { | |
68 | { | |
69 | .policy = "uncached", | |
70 | .cr_mask = CR_W|CR_C, | |
71 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 72 | .pte = L_PTE_MT_UNCACHED, |
ae8f1541 RK |
73 | }, { |
74 | .policy = "buffered", | |
75 | .cr_mask = CR_C, | |
76 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 77 | .pte = L_PTE_MT_BUFFERABLE, |
ae8f1541 RK |
78 | }, { |
79 | .policy = "writethrough", | |
80 | .cr_mask = 0, | |
81 | .pmd = PMD_SECT_WT, | |
bb30f36f | 82 | .pte = L_PTE_MT_WRITETHROUGH, |
ae8f1541 RK |
83 | }, { |
84 | .policy = "writeback", | |
85 | .cr_mask = 0, | |
86 | .pmd = PMD_SECT_WB, | |
bb30f36f | 87 | .pte = L_PTE_MT_WRITEBACK, |
ae8f1541 RK |
88 | }, { |
89 | .policy = "writealloc", | |
90 | .cr_mask = 0, | |
91 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 92 | .pte = L_PTE_MT_WRITEALLOC, |
ae8f1541 RK |
93 | } |
94 | }; | |
95 | ||
96 | /* | |
6cbdc8c5 | 97 | * These are useful for identifying cache coherency |
ae8f1541 RK |
98 | * problems by allowing the cache or the cache and |
99 | * writebuffer to be turned off. (Note: the write | |
100 | * buffer should not be on and the cache off). | |
101 | */ | |
2b0d8c25 | 102 | static int __init early_cachepolicy(char *p) |
ae8f1541 RK |
103 | { |
104 | int i; | |
105 | ||
106 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { | |
107 | int len = strlen(cache_policies[i].policy); | |
108 | ||
2b0d8c25 | 109 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ae8f1541 RK |
110 | cachepolicy = i; |
111 | cr_alignment &= ~cache_policies[i].cr_mask; | |
112 | cr_no_alignment &= ~cache_policies[i].cr_mask; | |
ae8f1541 RK |
113 | break; |
114 | } | |
115 | } | |
116 | if (i == ARRAY_SIZE(cache_policies)) | |
117 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); | |
4b46d641 RK |
118 | /* |
119 | * This restriction is partly to do with the way we boot; it is | |
120 | * unpredictable to have memory mapped using two different sets of | |
121 | * memory attributes (shared, type, and cache attribs). We can not | |
122 | * change these attributes once the initial assembly has setup the | |
123 | * page tables. | |
124 | */ | |
11179d8c CM |
125 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
126 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); | |
127 | cachepolicy = CPOLICY_WRITEBACK; | |
128 | } | |
ae8f1541 RK |
129 | flush_cache_all(); |
130 | set_cr(cr_alignment); | |
2b0d8c25 | 131 | return 0; |
ae8f1541 | 132 | } |
2b0d8c25 | 133 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 134 | |
2b0d8c25 | 135 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
136 | { |
137 | char *p = "buffered"; | |
138 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
139 | early_cachepolicy(p); |
140 | return 0; | |
ae8f1541 | 141 | } |
2b0d8c25 | 142 | early_param("nocache", early_nocache); |
ae8f1541 | 143 | |
2b0d8c25 | 144 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
145 | { |
146 | char *p = "uncached"; | |
147 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
148 | early_cachepolicy(p); |
149 | return 0; | |
ae8f1541 | 150 | } |
2b0d8c25 | 151 | early_param("nowb", early_nowrite); |
ae8f1541 | 152 | |
1b6ba46b | 153 | #ifndef CONFIG_ARM_LPAE |
2b0d8c25 | 154 | static int __init early_ecc(char *p) |
ae8f1541 | 155 | { |
2b0d8c25 | 156 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 157 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 158 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 159 | ecc_mask = 0; |
2b0d8c25 | 160 | return 0; |
ae8f1541 | 161 | } |
2b0d8c25 | 162 | early_param("ecc", early_ecc); |
1b6ba46b | 163 | #endif |
ae8f1541 RK |
164 | |
165 | static int __init noalign_setup(char *__unused) | |
166 | { | |
167 | cr_alignment &= ~CR_A; | |
168 | cr_no_alignment &= ~CR_A; | |
169 | set_cr(cr_alignment); | |
170 | return 1; | |
171 | } | |
172 | __setup("noalign", noalign_setup); | |
173 | ||
255d1f86 RK |
174 | #ifndef CONFIG_SMP |
175 | void adjust_cr(unsigned long mask, unsigned long set) | |
176 | { | |
177 | unsigned long flags; | |
178 | ||
179 | mask &= ~CR_A; | |
180 | ||
181 | set &= mask; | |
182 | ||
183 | local_irq_save(flags); | |
184 | ||
185 | cr_no_alignment = (cr_no_alignment & ~mask) | set; | |
186 | cr_alignment = (cr_alignment & ~mask) | set; | |
187 | ||
188 | set_cr((get_cr() & ~mask) | set); | |
189 | ||
190 | local_irq_restore(flags); | |
191 | } | |
192 | #endif | |
193 | ||
36bb94ba | 194 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
b1cce6b1 | 195 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 196 | |
b29e9f5e | 197 | static struct mem_type mem_types[] = { |
0af92bef | 198 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
199 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
200 | L_PTE_SHARED, | |
0af92bef | 201 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 202 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
203 | .domain = DOMAIN_IO, |
204 | }, | |
205 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 206 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 207 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 208 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
209 | .domain = DOMAIN_IO, |
210 | }, | |
211 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 212 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
213 | .prot_l1 = PMD_TYPE_TABLE, |
214 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
215 | .domain = DOMAIN_IO, | |
216 | }, | |
1ad77a87 | 217 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 218 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 219 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 220 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 221 | .domain = DOMAIN_IO, |
ae8f1541 | 222 | }, |
ebb4c658 RK |
223 | [MT_UNCACHED] = { |
224 | .prot_pte = PROT_PTE_DEVICE, | |
225 | .prot_l1 = PMD_TYPE_TABLE, | |
226 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
227 | .domain = DOMAIN_IO, | |
228 | }, | |
ae8f1541 | 229 | [MT_CACHECLEAN] = { |
9ef79635 | 230 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
231 | .domain = DOMAIN_KERNEL, |
232 | }, | |
1b6ba46b | 233 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 | 234 | [MT_MINICLEAN] = { |
9ef79635 | 235 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
236 | .domain = DOMAIN_KERNEL, |
237 | }, | |
1b6ba46b | 238 | #endif |
ae8f1541 RK |
239 | [MT_LOW_VECTORS] = { |
240 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 241 | L_PTE_RDONLY, |
ae8f1541 RK |
242 | .prot_l1 = PMD_TYPE_TABLE, |
243 | .domain = DOMAIN_USER, | |
244 | }, | |
245 | [MT_HIGH_VECTORS] = { | |
246 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 247 | L_PTE_USER | L_PTE_RDONLY, |
ae8f1541 RK |
248 | .prot_l1 = PMD_TYPE_TABLE, |
249 | .domain = DOMAIN_USER, | |
250 | }, | |
251 | [MT_MEMORY] = { | |
36bb94ba | 252 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
f1a2481c | 253 | .prot_l1 = PMD_TYPE_TABLE, |
9ef79635 | 254 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
255 | .domain = DOMAIN_KERNEL, |
256 | }, | |
257 | [MT_ROM] = { | |
9ef79635 | 258 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
259 | .domain = DOMAIN_KERNEL, |
260 | }, | |
e4707dd3 | 261 | [MT_MEMORY_NONCACHED] = { |
f1a2481c | 262 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 263 | L_PTE_MT_BUFFERABLE, |
f1a2481c | 264 | .prot_l1 = PMD_TYPE_TABLE, |
e4707dd3 PW |
265 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
266 | .domain = DOMAIN_KERNEL, | |
267 | }, | |
cb9d7707 | 268 | [MT_MEMORY_DTCM] = { |
f444fce3 | 269 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 270 | L_PTE_XN, |
f444fce3 LW |
271 | .prot_l1 = PMD_TYPE_TABLE, |
272 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
273 | .domain = DOMAIN_KERNEL, | |
cb9d7707 LW |
274 | }, |
275 | [MT_MEMORY_ITCM] = { | |
36bb94ba | 276 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
cb9d7707 | 277 | .prot_l1 = PMD_TYPE_TABLE, |
f444fce3 | 278 | .domain = DOMAIN_KERNEL, |
cb9d7707 | 279 | }, |
8fb54284 SS |
280 | [MT_MEMORY_SO] = { |
281 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
282 | L_PTE_MT_UNCACHED, | |
283 | .prot_l1 = PMD_TYPE_TABLE, | |
284 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | | |
285 | PMD_SECT_UNCACHED | PMD_SECT_XN, | |
286 | .domain = DOMAIN_KERNEL, | |
287 | }, | |
ae8f1541 RK |
288 | }; |
289 | ||
b29e9f5e RK |
290 | const struct mem_type *get_mem_type(unsigned int type) |
291 | { | |
292 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
293 | } | |
69d3a84a | 294 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 295 | |
ae8f1541 RK |
296 | /* |
297 | * Adjust the PMD section entries according to the CPU in use. | |
298 | */ | |
299 | static void __init build_mem_type_table(void) | |
300 | { | |
301 | struct cachepolicy *cp; | |
302 | unsigned int cr = get_cr(); | |
442e70c0 | 303 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
ae8f1541 RK |
304 | int cpu_arch = cpu_architecture(); |
305 | int i; | |
306 | ||
11179d8c | 307 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 308 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
309 | if (cachepolicy > CPOLICY_BUFFERED) |
310 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 311 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
312 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
313 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 314 | #endif |
11179d8c | 315 | } |
ae8f1541 RK |
316 | if (cpu_arch < CPU_ARCH_ARMv5) { |
317 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
318 | cachepolicy = CPOLICY_WRITEBACK; | |
319 | ecc_mask = 0; | |
320 | } | |
f00ec48f RK |
321 | if (is_smp()) |
322 | cachepolicy = CPOLICY_WRITEALLOC; | |
ae8f1541 | 323 | |
1ad77a87 | 324 | /* |
b1cce6b1 RK |
325 | * Strip out features not present on earlier architectures. |
326 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
327 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 328 | */ |
b1cce6b1 RK |
329 | if (cpu_arch < CPU_ARCH_ARMv5) |
330 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
331 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
332 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
333 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
334 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
335 | |
336 | /* | |
b1cce6b1 RK |
337 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
338 | * "update-able on write" bit on ARM610). However, Xscale and | |
339 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 340 | */ |
b1cce6b1 | 341 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
9ef79635 | 342 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 343 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
344 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
345 | } | |
346 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
347 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
348 | if (mem_types[i].prot_l1) |
349 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
350 | if (mem_types[i].prot_sect) |
351 | mem_types[i].prot_sect |= PMD_BIT4; | |
352 | } | |
353 | } | |
ae8f1541 | 354 | |
b1cce6b1 RK |
355 | /* |
356 | * Mark the device areas according to the CPU/architecture. | |
357 | */ | |
358 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
359 | if (!cpu_is_xsc3()) { | |
360 | /* | |
361 | * Mark device regions on ARMv6+ as execute-never | |
362 | * to prevent speculative instruction fetches. | |
363 | */ | |
364 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
365 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
366 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
367 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
368 | } | |
369 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
370 | /* | |
371 | * For ARMv7 with TEX remapping, | |
372 | * - shared device is SXCB=1100 | |
373 | * - nonshared device is SXCB=0100 | |
374 | * - write combine device mem is SXCB=0001 | |
375 | * (Uncached Normal memory) | |
376 | */ | |
377 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
378 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
379 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
380 | } else if (cpu_is_xsc3()) { | |
381 | /* | |
382 | * For Xscale3, | |
383 | * - shared device is TEXCB=00101 | |
384 | * - nonshared device is TEXCB=01000 | |
385 | * - write combine device mem is TEXCB=00100 | |
386 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
387 | */ | |
388 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
389 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
390 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
391 | } else { | |
392 | /* | |
393 | * For ARMv6 and ARMv7 without TEX remapping, | |
394 | * - shared device is TEXCB=00001 | |
395 | * - nonshared device is TEXCB=01000 | |
396 | * - write combine device mem is TEXCB=00100 | |
397 | * (Uncached Normal in ARMv6 parlance). | |
398 | */ | |
399 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
400 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
401 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
402 | } | |
403 | } else { | |
404 | /* | |
405 | * On others, write combining is "Uncached/Buffered" | |
406 | */ | |
407 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
408 | } | |
409 | ||
410 | /* | |
411 | * Now deal with the memory-type mappings | |
412 | */ | |
ae8f1541 | 413 | cp = &cache_policies[cachepolicy]; |
bb30f36f RK |
414 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
415 | ||
bb30f36f RK |
416 | /* |
417 | * Only use write-through for non-SMP systems | |
418 | */ | |
f00ec48f | 419 | if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) |
bb30f36f | 420 | vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; |
ae8f1541 RK |
421 | |
422 | /* | |
423 | * Enable CPU-specific coherency if supported. | |
424 | * (Only available on XSC3 at the moment.) | |
425 | */ | |
f1a2481c | 426 | if (arch_is_coherent() && cpu_is_xsc3()) { |
b1cce6b1 | 427 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
f1a2481c SS |
428 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; |
429 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; | |
430 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
431 | } | |
ae8f1541 RK |
432 | /* |
433 | * ARMv6 and above have extended page tables. | |
434 | */ | |
435 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
1b6ba46b | 436 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
437 | /* |
438 | * Mark cache clean areas and XIP ROM read only | |
439 | * from SVC mode and no access from userspace. | |
440 | */ | |
441 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
442 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
443 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
1b6ba46b | 444 | #endif |
ae8f1541 | 445 | |
f00ec48f RK |
446 | if (is_smp()) { |
447 | /* | |
448 | * Mark memory with the "shared" attribute | |
449 | * for SMP systems | |
450 | */ | |
451 | user_pgprot |= L_PTE_SHARED; | |
452 | kern_pgprot |= L_PTE_SHARED; | |
453 | vecs_pgprot |= L_PTE_SHARED; | |
454 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; | |
455 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; | |
456 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; | |
457 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; | |
458 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; | |
459 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; | |
460 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; | |
461 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
462 | } | |
ae8f1541 RK |
463 | } |
464 | ||
e4707dd3 PW |
465 | /* |
466 | * Non-cacheable Normal - intended for memory areas that must | |
467 | * not cause dirty cache line writebacks when used | |
468 | */ | |
469 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
470 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
471 | /* Non-cacheable Normal is XCB = 001 */ | |
472 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
473 | PMD_SECT_BUFFERED; | |
474 | } else { | |
475 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
476 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
477 | PMD_SECT_TEX(1); | |
478 | } | |
479 | } else { | |
480 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; | |
481 | } | |
482 | ||
1b6ba46b CM |
483 | #ifdef CONFIG_ARM_LPAE |
484 | /* | |
485 | * Do not generate access flag faults for the kernel mappings. | |
486 | */ | |
487 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
488 | mem_types[i].prot_pte |= PTE_EXT_AF; | |
489 | mem_types[i].prot_sect |= PMD_SECT_AF; | |
490 | } | |
491 | kern_pgprot |= PTE_EXT_AF; | |
492 | vecs_pgprot |= PTE_EXT_AF; | |
493 | #endif | |
494 | ||
ae8f1541 RK |
495 | for (i = 0; i < 16; i++) { |
496 | unsigned long v = pgprot_val(protection_map[i]); | |
bb30f36f | 497 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
498 | } |
499 | ||
bb30f36f RK |
500 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
501 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 502 | |
44b18693 | 503 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 504 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
36bb94ba | 505 | L_PTE_DIRTY | kern_pgprot); |
ae8f1541 RK |
506 | |
507 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
508 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
509 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; | |
f1a2481c SS |
510 | mem_types[MT_MEMORY].prot_pte |= kern_pgprot; |
511 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; | |
ae8f1541 RK |
512 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
513 | ||
514 | switch (cp->pmd) { | |
515 | case PMD_SECT_WT: | |
516 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
517 | break; | |
518 | case PMD_SECT_WB: | |
519 | case PMD_SECT_WBWA: | |
520 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
521 | break; | |
522 | } | |
523 | printk("Memory policy: ECC %sabled, Data cache %s\n", | |
524 | ecc_mask ? "en" : "dis", cp->policy); | |
2497f0a8 RK |
525 | |
526 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
527 | struct mem_type *t = &mem_types[i]; | |
528 | if (t->prot_l1) | |
529 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
530 | if (t->prot_sect) | |
531 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
532 | } | |
ae8f1541 RK |
533 | } |
534 | ||
d907387c CM |
535 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
536 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
537 | unsigned long size, pgprot_t vma_prot) | |
538 | { | |
539 | if (!pfn_valid(pfn)) | |
540 | return pgprot_noncached(vma_prot); | |
541 | else if (file->f_flags & O_SYNC) | |
542 | return pgprot_writecombine(vma_prot); | |
543 | return vma_prot; | |
544 | } | |
545 | EXPORT_SYMBOL(phys_mem_access_prot); | |
546 | #endif | |
547 | ||
ae8f1541 RK |
548 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
549 | ||
3abe9d33 RK |
550 | static void __init *early_alloc(unsigned long sz) |
551 | { | |
2778f620 RK |
552 | void *ptr = __va(memblock_alloc(sz, sz)); |
553 | memset(ptr, 0, sz); | |
554 | return ptr; | |
3abe9d33 RK |
555 | } |
556 | ||
4bb2e27d | 557 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) |
ae8f1541 | 558 | { |
24e6c699 | 559 | if (pmd_none(*pmd)) { |
410f1483 | 560 | pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
97092e0c | 561 | __pmd_populate(pmd, __pa(pte), prot); |
24e6c699 | 562 | } |
4bb2e27d RK |
563 | BUG_ON(pmd_bad(*pmd)); |
564 | return pte_offset_kernel(pmd, addr); | |
565 | } | |
ae8f1541 | 566 | |
4bb2e27d RK |
567 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
568 | unsigned long end, unsigned long pfn, | |
569 | const struct mem_type *type) | |
570 | { | |
571 | pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); | |
24e6c699 | 572 | do { |
40d192b6 | 573 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
24e6c699 RK |
574 | pfn++; |
575 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
576 | } |
577 | ||
516295e5 | 578 | static void __init alloc_init_section(pud_t *pud, unsigned long addr, |
97092e0c | 579 | unsigned long end, phys_addr_t phys, |
24e6c699 | 580 | const struct mem_type *type) |
ae8f1541 | 581 | { |
516295e5 | 582 | pmd_t *pmd = pmd_offset(pud, addr); |
ae8f1541 | 583 | |
24e6c699 RK |
584 | /* |
585 | * Try a section mapping - end, addr and phys must all be aligned | |
586 | * to a section boundary. Note that PMDs refer to the individual | |
587 | * L1 entries, whereas PGDs refer to a group of L1 entries making | |
588 | * up one logical pointer to an L2 table. | |
589 | */ | |
590 | if (((addr | end | phys) & ~SECTION_MASK) == 0) { | |
591 | pmd_t *p = pmd; | |
ae8f1541 | 592 | |
1b6ba46b | 593 | #ifndef CONFIG_ARM_LPAE |
24e6c699 RK |
594 | if (addr & SECTION_SIZE) |
595 | pmd++; | |
1b6ba46b | 596 | #endif |
24e6c699 RK |
597 | |
598 | do { | |
599 | *pmd = __pmd(phys | type->prot_sect); | |
600 | phys += SECTION_SIZE; | |
601 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
ae8f1541 | 602 | |
24e6c699 RK |
603 | flush_pmd_entry(p); |
604 | } else { | |
605 | /* | |
606 | * No need to loop; pte's aren't interested in the | |
607 | * individual L1 entries. | |
608 | */ | |
609 | alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); | |
610 | } | |
ae8f1541 RK |
611 | } |
612 | ||
516295e5 RK |
613 | static void alloc_init_pud(pgd_t *pgd, unsigned long addr, unsigned long end, |
614 | unsigned long phys, const struct mem_type *type) | |
615 | { | |
616 | pud_t *pud = pud_offset(pgd, addr); | |
617 | unsigned long next; | |
618 | ||
619 | do { | |
620 | next = pud_addr_end(addr, end); | |
621 | alloc_init_section(pud, addr, next, phys, type); | |
622 | phys += next - addr; | |
623 | } while (pud++, addr = next, addr != end); | |
624 | } | |
625 | ||
1b6ba46b | 626 | #ifndef CONFIG_ARM_LPAE |
4a56c1e4 RK |
627 | static void __init create_36bit_mapping(struct map_desc *md, |
628 | const struct mem_type *type) | |
629 | { | |
97092e0c RK |
630 | unsigned long addr, length, end; |
631 | phys_addr_t phys; | |
4a56c1e4 RK |
632 | pgd_t *pgd; |
633 | ||
634 | addr = md->virtual; | |
cae6292b | 635 | phys = __pfn_to_phys(md->pfn); |
4a56c1e4 RK |
636 | length = PAGE_ALIGN(md->length); |
637 | ||
638 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
639 | printk(KERN_ERR "MM: CPU does not support supersection " | |
640 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 641 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
642 | return; |
643 | } | |
644 | ||
645 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
646 | * Since domain assignments can in fact be arbitrary, the | |
647 | * 'domain == 0' check below is required to insure that ARMv6 | |
648 | * supersections are only allocated for domain 0 regardless | |
649 | * of the actual domain assignments in use. | |
650 | */ | |
651 | if (type->domain) { | |
652 | printk(KERN_ERR "MM: invalid domain in supersection " | |
653 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 654 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
655 | return; |
656 | } | |
657 | ||
658 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
29a38193 WD |
659 | printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" |
660 | " at 0x%08lx invalid alignment\n", | |
661 | (long long)__pfn_to_phys((u64)md->pfn), addr); | |
4a56c1e4 RK |
662 | return; |
663 | } | |
664 | ||
665 | /* | |
666 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
667 | * (See ARMv6 spec). | |
668 | */ | |
669 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
670 | ||
671 | pgd = pgd_offset_k(addr); | |
672 | end = addr + length; | |
673 | do { | |
516295e5 RK |
674 | pud_t *pud = pud_offset(pgd, addr); |
675 | pmd_t *pmd = pmd_offset(pud, addr); | |
4a56c1e4 RK |
676 | int i; |
677 | ||
678 | for (i = 0; i < 16; i++) | |
679 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); | |
680 | ||
681 | addr += SUPERSECTION_SIZE; | |
682 | phys += SUPERSECTION_SIZE; | |
683 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
684 | } while (addr != end); | |
685 | } | |
1b6ba46b | 686 | #endif /* !CONFIG_ARM_LPAE */ |
4a56c1e4 | 687 | |
ae8f1541 RK |
688 | /* |
689 | * Create the page directory entries and any necessary | |
690 | * page tables for the mapping specified by `md'. We | |
691 | * are able to cope here with varying sizes and address | |
692 | * offsets, and we take full advantage of sections and | |
693 | * supersections. | |
694 | */ | |
a2227120 | 695 | static void __init create_mapping(struct map_desc *md) |
ae8f1541 | 696 | { |
cae6292b WD |
697 | unsigned long addr, length, end; |
698 | phys_addr_t phys; | |
d5c98176 | 699 | const struct mem_type *type; |
24e6c699 | 700 | pgd_t *pgd; |
ae8f1541 RK |
701 | |
702 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
29a38193 WD |
703 | printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" |
704 | " at 0x%08lx in user region\n", | |
705 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
ae8f1541 RK |
706 | return; |
707 | } | |
708 | ||
709 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
710 | md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { | |
29a38193 WD |
711 | printk(KERN_WARNING "BUG: mapping for 0x%08llx" |
712 | " at 0x%08lx overlaps vmalloc space\n", | |
713 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
ae8f1541 RK |
714 | } |
715 | ||
d5c98176 | 716 | type = &mem_types[md->type]; |
ae8f1541 | 717 | |
1b6ba46b | 718 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
719 | /* |
720 | * Catch 36-bit addresses | |
721 | */ | |
4a56c1e4 RK |
722 | if (md->pfn >= 0x100000) { |
723 | create_36bit_mapping(md, type); | |
724 | return; | |
ae8f1541 | 725 | } |
1b6ba46b | 726 | #endif |
ae8f1541 | 727 | |
7b9c7b4d | 728 | addr = md->virtual & PAGE_MASK; |
cae6292b | 729 | phys = __pfn_to_phys(md->pfn); |
7b9c7b4d | 730 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 731 | |
24e6c699 | 732 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
29a38193 | 733 | printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " |
ae8f1541 | 734 | "be mapped using pages, ignoring.\n", |
29a38193 | 735 | (long long)__pfn_to_phys(md->pfn), addr); |
ae8f1541 RK |
736 | return; |
737 | } | |
738 | ||
24e6c699 RK |
739 | pgd = pgd_offset_k(addr); |
740 | end = addr + length; | |
741 | do { | |
742 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 743 | |
516295e5 | 744 | alloc_init_pud(pgd, addr, next, phys, type); |
ae8f1541 | 745 | |
24e6c699 RK |
746 | phys += next - addr; |
747 | addr = next; | |
748 | } while (pgd++, addr != end); | |
ae8f1541 RK |
749 | } |
750 | ||
751 | /* | |
752 | * Create the architecture specific mappings | |
753 | */ | |
754 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
755 | { | |
756 | int i; | |
757 | ||
758 | for (i = 0; i < nr; i++) | |
759 | create_mapping(io_desc + i); | |
760 | } | |
761 | ||
79612395 | 762 | static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M); |
6c5da7ac RK |
763 | |
764 | /* | |
765 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
766 | * bytes. This can be used to increase (or decrease) the vmalloc | |
767 | * area - the default is 128m. | |
768 | */ | |
2b0d8c25 | 769 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 770 | { |
79612395 | 771 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
6c5da7ac RK |
772 | |
773 | if (vmalloc_reserve < SZ_16M) { | |
774 | vmalloc_reserve = SZ_16M; | |
775 | printk(KERN_WARNING | |
776 | "vmalloc area too small, limiting to %luMB\n", | |
777 | vmalloc_reserve >> 20); | |
778 | } | |
9210807c NP |
779 | |
780 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { | |
781 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); | |
782 | printk(KERN_WARNING | |
783 | "vmalloc area is too big, limiting to %luMB\n", | |
784 | vmalloc_reserve >> 20); | |
785 | } | |
79612395 RK |
786 | |
787 | vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); | |
2b0d8c25 | 788 | return 0; |
6c5da7ac | 789 | } |
2b0d8c25 | 790 | early_param("vmalloc", early_vmalloc); |
6c5da7ac | 791 | |
8df65168 RK |
792 | static phys_addr_t lowmem_limit __initdata = 0; |
793 | ||
0371d3f7 | 794 | void __init sanity_check_meminfo(void) |
60296c71 | 795 | { |
dde5828f | 796 | int i, j, highmem = 0; |
60296c71 | 797 | |
4b5f32ce | 798 | for (i = 0, j = 0; i < meminfo.nr_banks; i++) { |
a1bbaec0 NP |
799 | struct membank *bank = &meminfo.bank[j]; |
800 | *bank = meminfo.bank[i]; | |
60296c71 | 801 | |
a1bbaec0 | 802 | #ifdef CONFIG_HIGHMEM |
40f7bfe4 | 803 | if (__va(bank->start) >= vmalloc_min || |
dde5828f RK |
804 | __va(bank->start) < (void *)PAGE_OFFSET) |
805 | highmem = 1; | |
806 | ||
807 | bank->highmem = highmem; | |
808 | ||
a1bbaec0 NP |
809 | /* |
810 | * Split those memory banks which are partially overlapping | |
811 | * the vmalloc area greatly simplifying things later. | |
812 | */ | |
79612395 RK |
813 | if (__va(bank->start) < vmalloc_min && |
814 | bank->size > vmalloc_min - __va(bank->start)) { | |
a1bbaec0 NP |
815 | if (meminfo.nr_banks >= NR_BANKS) { |
816 | printk(KERN_CRIT "NR_BANKS too low, " | |
817 | "ignoring high memory\n"); | |
818 | } else { | |
819 | memmove(bank + 1, bank, | |
820 | (meminfo.nr_banks - i) * sizeof(*bank)); | |
821 | meminfo.nr_banks++; | |
822 | i++; | |
79612395 RK |
823 | bank[1].size -= vmalloc_min - __va(bank->start); |
824 | bank[1].start = __pa(vmalloc_min - 1) + 1; | |
dde5828f | 825 | bank[1].highmem = highmem = 1; |
a1bbaec0 NP |
826 | j++; |
827 | } | |
79612395 | 828 | bank->size = vmalloc_min - __va(bank->start); |
a1bbaec0 NP |
829 | } |
830 | #else | |
041d785f RK |
831 | bank->highmem = highmem; |
832 | ||
a1bbaec0 NP |
833 | /* |
834 | * Check whether this memory bank would entirely overlap | |
835 | * the vmalloc area. | |
836 | */ | |
79612395 | 837 | if (__va(bank->start) >= vmalloc_min || |
f0bba9f9 | 838 | __va(bank->start) < (void *)PAGE_OFFSET) { |
e33b9d08 | 839 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " |
a1bbaec0 | 840 | "(vmalloc region overlap).\n", |
e33b9d08 RK |
841 | (unsigned long long)bank->start, |
842 | (unsigned long long)bank->start + bank->size - 1); | |
a1bbaec0 NP |
843 | continue; |
844 | } | |
60296c71 | 845 | |
a1bbaec0 NP |
846 | /* |
847 | * Check whether this memory bank would partially overlap | |
848 | * the vmalloc area. | |
849 | */ | |
79612395 | 850 | if (__va(bank->start + bank->size) > vmalloc_min || |
a1bbaec0 | 851 | __va(bank->start + bank->size) < __va(bank->start)) { |
79612395 | 852 | unsigned long newsize = vmalloc_min - __va(bank->start); |
e33b9d08 RK |
853 | printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " |
854 | "to -%.8llx (vmalloc region overlap).\n", | |
855 | (unsigned long long)bank->start, | |
856 | (unsigned long long)bank->start + bank->size - 1, | |
857 | (unsigned long long)bank->start + newsize - 1); | |
a1bbaec0 NP |
858 | bank->size = newsize; |
859 | } | |
860 | #endif | |
40f7bfe4 WD |
861 | if (!bank->highmem && bank->start + bank->size > lowmem_limit) |
862 | lowmem_limit = bank->start + bank->size; | |
863 | ||
a1bbaec0 | 864 | j++; |
60296c71 | 865 | } |
e616c591 RK |
866 | #ifdef CONFIG_HIGHMEM |
867 | if (highmem) { | |
868 | const char *reason = NULL; | |
869 | ||
870 | if (cache_is_vipt_aliasing()) { | |
871 | /* | |
872 | * Interactions between kmap and other mappings | |
873 | * make highmem support with aliasing VIPT caches | |
874 | * rather difficult. | |
875 | */ | |
876 | reason = "with VIPT aliasing cache"; | |
e616c591 RK |
877 | } |
878 | if (reason) { | |
879 | printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", | |
880 | reason); | |
881 | while (j > 0 && meminfo.bank[j - 1].highmem) | |
882 | j--; | |
883 | } | |
884 | } | |
885 | #endif | |
4b5f32ce | 886 | meminfo.nr_banks = j; |
40f7bfe4 | 887 | memblock_set_current_limit(lowmem_limit); |
60296c71 LB |
888 | } |
889 | ||
4b5f32ce | 890 | static inline void prepare_page_table(void) |
d111e8f9 RK |
891 | { |
892 | unsigned long addr; | |
8df65168 | 893 | phys_addr_t end; |
d111e8f9 RK |
894 | |
895 | /* | |
896 | * Clear out all the mappings below the kernel image. | |
897 | */ | |
e73fc88e | 898 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
d111e8f9 RK |
899 | pmd_clear(pmd_off_k(addr)); |
900 | ||
901 | #ifdef CONFIG_XIP_KERNEL | |
902 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
e73fc88e | 903 | addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; |
d111e8f9 | 904 | #endif |
e73fc88e | 905 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
d111e8f9 RK |
906 | pmd_clear(pmd_off_k(addr)); |
907 | ||
8df65168 RK |
908 | /* |
909 | * Find the end of the first block of lowmem. | |
910 | */ | |
911 | end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; | |
912 | if (end >= lowmem_limit) | |
913 | end = lowmem_limit; | |
914 | ||
d111e8f9 RK |
915 | /* |
916 | * Clear out all the kernel space mappings, except for the first | |
917 | * memory bank, up to the end of the vmalloc region. | |
918 | */ | |
8df65168 | 919 | for (addr = __phys_to_virt(end); |
e73fc88e | 920 | addr < VMALLOC_END; addr += PMD_SIZE) |
d111e8f9 RK |
921 | pmd_clear(pmd_off_k(addr)); |
922 | } | |
923 | ||
1b6ba46b CM |
924 | #ifdef CONFIG_ARM_LPAE |
925 | /* the first page is reserved for pgd */ | |
926 | #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ | |
927 | PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) | |
928 | #else | |
e73fc88e | 929 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
1b6ba46b | 930 | #endif |
e73fc88e | 931 | |
d111e8f9 | 932 | /* |
2778f620 | 933 | * Reserve the special regions of memory |
d111e8f9 | 934 | */ |
2778f620 | 935 | void __init arm_mm_memblock_reserve(void) |
d111e8f9 | 936 | { |
d111e8f9 RK |
937 | /* |
938 | * Reserve the page tables. These are already in use, | |
939 | * and can only be in node 0. | |
940 | */ | |
e73fc88e | 941 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
d111e8f9 | 942 | |
d111e8f9 RK |
943 | #ifdef CONFIG_SA1111 |
944 | /* | |
945 | * Because of the SA1111 DMA bug, we want to preserve our | |
946 | * precious DMA-able memory... | |
947 | */ | |
2778f620 | 948 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
d111e8f9 | 949 | #endif |
d111e8f9 RK |
950 | } |
951 | ||
952 | /* | |
953 | * Set up device the mappings. Since we clear out the page tables for all | |
954 | * mappings above VMALLOC_END, we will remove any debug device mappings. | |
955 | * This means you have to be careful how you debug this function, or any | |
956 | * called function. This means you can't use any function or debugging | |
957 | * method which may touch any device, otherwise the kernel _will_ crash. | |
958 | */ | |
959 | static void __init devicemaps_init(struct machine_desc *mdesc) | |
960 | { | |
961 | struct map_desc map; | |
962 | unsigned long addr; | |
d111e8f9 RK |
963 | |
964 | /* | |
965 | * Allocate the vector page early. | |
966 | */ | |
247055aa | 967 | vectors_page = early_alloc(PAGE_SIZE); |
d111e8f9 | 968 | |
e73fc88e | 969 | for (addr = VMALLOC_END; addr; addr += PMD_SIZE) |
d111e8f9 RK |
970 | pmd_clear(pmd_off_k(addr)); |
971 | ||
972 | /* | |
973 | * Map the kernel if it is XIP. | |
974 | * It is always first in the modulearea. | |
975 | */ | |
976 | #ifdef CONFIG_XIP_KERNEL | |
977 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 978 | map.virtual = MODULES_VADDR; |
37efe642 | 979 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
980 | map.type = MT_ROM; |
981 | create_mapping(&map); | |
982 | #endif | |
983 | ||
984 | /* | |
985 | * Map the cache flushing regions. | |
986 | */ | |
987 | #ifdef FLUSH_BASE | |
988 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
989 | map.virtual = FLUSH_BASE; | |
990 | map.length = SZ_1M; | |
991 | map.type = MT_CACHECLEAN; | |
992 | create_mapping(&map); | |
993 | #endif | |
994 | #ifdef FLUSH_BASE_MINICACHE | |
995 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
996 | map.virtual = FLUSH_BASE_MINICACHE; | |
997 | map.length = SZ_1M; | |
998 | map.type = MT_MINICLEAN; | |
999 | create_mapping(&map); | |
1000 | #endif | |
1001 | ||
1002 | /* | |
1003 | * Create a mapping for the machine vectors at the high-vectors | |
1004 | * location (0xffff0000). If we aren't using high-vectors, also | |
1005 | * create a mapping at the low-vectors virtual address. | |
1006 | */ | |
247055aa | 1007 | map.pfn = __phys_to_pfn(virt_to_phys(vectors_page)); |
d111e8f9 RK |
1008 | map.virtual = 0xffff0000; |
1009 | map.length = PAGE_SIZE; | |
1010 | map.type = MT_HIGH_VECTORS; | |
1011 | create_mapping(&map); | |
1012 | ||
1013 | if (!vectors_high()) { | |
1014 | map.virtual = 0; | |
1015 | map.type = MT_LOW_VECTORS; | |
1016 | create_mapping(&map); | |
1017 | } | |
1018 | ||
1019 | /* | |
1020 | * Ask the machine support to map in the statically mapped devices. | |
1021 | */ | |
1022 | if (mdesc->map_io) | |
1023 | mdesc->map_io(); | |
1024 | ||
1025 | /* | |
1026 | * Finally flush the caches and tlb to ensure that we're in a | |
1027 | * consistent state wrt the writebuffer. This also ensures that | |
1028 | * any write-allocated cache lines in the vector page are written | |
1029 | * back. After this point, we can start to touch devices again. | |
1030 | */ | |
1031 | local_flush_tlb_all(); | |
1032 | flush_cache_all(); | |
1033 | } | |
1034 | ||
d73cd428 NP |
1035 | static void __init kmap_init(void) |
1036 | { | |
1037 | #ifdef CONFIG_HIGHMEM | |
4bb2e27d RK |
1038 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
1039 | PKMAP_BASE, _PAGE_KERNEL_TABLE); | |
d73cd428 NP |
1040 | #endif |
1041 | } | |
1042 | ||
a2227120 RK |
1043 | static void __init map_lowmem(void) |
1044 | { | |
8df65168 | 1045 | struct memblock_region *reg; |
a2227120 RK |
1046 | |
1047 | /* Map all the lowmem memory banks. */ | |
8df65168 RK |
1048 | for_each_memblock(memory, reg) { |
1049 | phys_addr_t start = reg->base; | |
1050 | phys_addr_t end = start + reg->size; | |
1051 | struct map_desc map; | |
1052 | ||
1053 | if (end > lowmem_limit) | |
1054 | end = lowmem_limit; | |
1055 | if (start >= end) | |
1056 | break; | |
1057 | ||
1058 | map.pfn = __phys_to_pfn(start); | |
1059 | map.virtual = __phys_to_virt(start); | |
1060 | map.length = end - start; | |
1061 | map.type = MT_MEMORY; | |
a2227120 | 1062 | |
8df65168 | 1063 | create_mapping(&map); |
a2227120 RK |
1064 | } |
1065 | } | |
1066 | ||
d111e8f9 RK |
1067 | /* |
1068 | * paging_init() sets up the page tables, initialises the zone memory | |
1069 | * maps, and sets up the zero page, bad page and bad page tables. | |
1070 | */ | |
4b5f32ce | 1071 | void __init paging_init(struct machine_desc *mdesc) |
d111e8f9 RK |
1072 | { |
1073 | void *zero_page; | |
1074 | ||
0371d3f7 RK |
1075 | memblock_set_current_limit(lowmem_limit); |
1076 | ||
d111e8f9 | 1077 | build_mem_type_table(); |
4b5f32ce | 1078 | prepare_page_table(); |
a2227120 | 1079 | map_lowmem(); |
d111e8f9 | 1080 | devicemaps_init(mdesc); |
d73cd428 | 1081 | kmap_init(); |
d111e8f9 RK |
1082 | |
1083 | top_pmd = pmd_off_k(0xffff0000); | |
1084 | ||
3abe9d33 RK |
1085 | /* allocate the zero page. */ |
1086 | zero_page = early_alloc(PAGE_SIZE); | |
2778f620 | 1087 | |
8d717a52 | 1088 | bootmem_init(); |
2778f620 | 1089 | |
d111e8f9 | 1090 | empty_zero_page = virt_to_page(zero_page); |
421fe93c | 1091 | __flush_dcache_page(NULL, empty_zero_page); |
d111e8f9 | 1092 | } |