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d111e8f9 RK |
1 | /* |
2 | * linux/arch/arm/mm/mmu.c | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ae8f1541 | 10 | #include <linux/module.h> |
d111e8f9 RK |
11 | #include <linux/kernel.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/init.h> | |
d111e8f9 RK |
14 | #include <linux/mman.h> |
15 | #include <linux/nodemask.h> | |
2778f620 | 16 | #include <linux/memblock.h> |
d907387c | 17 | #include <linux/fs.h> |
d111e8f9 | 18 | |
0ba8b9b2 | 19 | #include <asm/cputype.h> |
37efe642 | 20 | #include <asm/sections.h> |
3f973e22 | 21 | #include <asm/cachetype.h> |
d111e8f9 RK |
22 | #include <asm/setup.h> |
23 | #include <asm/sizes.h> | |
e616c591 | 24 | #include <asm/smp_plat.h> |
d111e8f9 | 25 | #include <asm/tlb.h> |
d73cd428 | 26 | #include <asm/highmem.h> |
d111e8f9 RK |
27 | |
28 | #include <asm/mach/arch.h> | |
29 | #include <asm/mach/map.h> | |
30 | ||
31 | #include "mm.h" | |
32 | ||
33 | DEFINE_PER_CPU(struct mmu_gather, mmu_gathers); | |
34 | ||
d111e8f9 RK |
35 | /* |
36 | * empty_zero_page is a special page that is used for | |
37 | * zero-initialized data and COW. | |
38 | */ | |
39 | struct page *empty_zero_page; | |
3653f3ab | 40 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
41 | |
42 | /* | |
43 | * The pmd table for the upper-most set of pages. | |
44 | */ | |
45 | pmd_t *top_pmd; | |
46 | ||
ae8f1541 RK |
47 | #define CPOLICY_UNCACHED 0 |
48 | #define CPOLICY_BUFFERED 1 | |
49 | #define CPOLICY_WRITETHROUGH 2 | |
50 | #define CPOLICY_WRITEBACK 3 | |
51 | #define CPOLICY_WRITEALLOC 4 | |
52 | ||
53 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
54 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 55 | pgprot_t pgprot_user; |
ae8f1541 RK |
56 | pgprot_t pgprot_kernel; |
57 | ||
44b18693 | 58 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
59 | EXPORT_SYMBOL(pgprot_kernel); |
60 | ||
61 | struct cachepolicy { | |
62 | const char policy[16]; | |
63 | unsigned int cr_mask; | |
64 | unsigned int pmd; | |
65 | unsigned int pte; | |
66 | }; | |
67 | ||
68 | static struct cachepolicy cache_policies[] __initdata = { | |
69 | { | |
70 | .policy = "uncached", | |
71 | .cr_mask = CR_W|CR_C, | |
72 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 73 | .pte = L_PTE_MT_UNCACHED, |
ae8f1541 RK |
74 | }, { |
75 | .policy = "buffered", | |
76 | .cr_mask = CR_C, | |
77 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 78 | .pte = L_PTE_MT_BUFFERABLE, |
ae8f1541 RK |
79 | }, { |
80 | .policy = "writethrough", | |
81 | .cr_mask = 0, | |
82 | .pmd = PMD_SECT_WT, | |
bb30f36f | 83 | .pte = L_PTE_MT_WRITETHROUGH, |
ae8f1541 RK |
84 | }, { |
85 | .policy = "writeback", | |
86 | .cr_mask = 0, | |
87 | .pmd = PMD_SECT_WB, | |
bb30f36f | 88 | .pte = L_PTE_MT_WRITEBACK, |
ae8f1541 RK |
89 | }, { |
90 | .policy = "writealloc", | |
91 | .cr_mask = 0, | |
92 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 93 | .pte = L_PTE_MT_WRITEALLOC, |
ae8f1541 RK |
94 | } |
95 | }; | |
96 | ||
97 | /* | |
6cbdc8c5 | 98 | * These are useful for identifying cache coherency |
ae8f1541 RK |
99 | * problems by allowing the cache or the cache and |
100 | * writebuffer to be turned off. (Note: the write | |
101 | * buffer should not be on and the cache off). | |
102 | */ | |
2b0d8c25 | 103 | static int __init early_cachepolicy(char *p) |
ae8f1541 RK |
104 | { |
105 | int i; | |
106 | ||
107 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { | |
108 | int len = strlen(cache_policies[i].policy); | |
109 | ||
2b0d8c25 | 110 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ae8f1541 RK |
111 | cachepolicy = i; |
112 | cr_alignment &= ~cache_policies[i].cr_mask; | |
113 | cr_no_alignment &= ~cache_policies[i].cr_mask; | |
ae8f1541 RK |
114 | break; |
115 | } | |
116 | } | |
117 | if (i == ARRAY_SIZE(cache_policies)) | |
118 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); | |
4b46d641 RK |
119 | /* |
120 | * This restriction is partly to do with the way we boot; it is | |
121 | * unpredictable to have memory mapped using two different sets of | |
122 | * memory attributes (shared, type, and cache attribs). We can not | |
123 | * change these attributes once the initial assembly has setup the | |
124 | * page tables. | |
125 | */ | |
11179d8c CM |
126 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
127 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); | |
128 | cachepolicy = CPOLICY_WRITEBACK; | |
129 | } | |
ae8f1541 RK |
130 | flush_cache_all(); |
131 | set_cr(cr_alignment); | |
2b0d8c25 | 132 | return 0; |
ae8f1541 | 133 | } |
2b0d8c25 | 134 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 135 | |
2b0d8c25 | 136 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
137 | { |
138 | char *p = "buffered"; | |
139 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
140 | early_cachepolicy(p); |
141 | return 0; | |
ae8f1541 | 142 | } |
2b0d8c25 | 143 | early_param("nocache", early_nocache); |
ae8f1541 | 144 | |
2b0d8c25 | 145 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
146 | { |
147 | char *p = "uncached"; | |
148 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
149 | early_cachepolicy(p); |
150 | return 0; | |
ae8f1541 | 151 | } |
2b0d8c25 | 152 | early_param("nowb", early_nowrite); |
ae8f1541 | 153 | |
2b0d8c25 | 154 | static int __init early_ecc(char *p) |
ae8f1541 | 155 | { |
2b0d8c25 | 156 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 157 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 158 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 159 | ecc_mask = 0; |
2b0d8c25 | 160 | return 0; |
ae8f1541 | 161 | } |
2b0d8c25 | 162 | early_param("ecc", early_ecc); |
ae8f1541 RK |
163 | |
164 | static int __init noalign_setup(char *__unused) | |
165 | { | |
166 | cr_alignment &= ~CR_A; | |
167 | cr_no_alignment &= ~CR_A; | |
168 | set_cr(cr_alignment); | |
169 | return 1; | |
170 | } | |
171 | __setup("noalign", noalign_setup); | |
172 | ||
255d1f86 RK |
173 | #ifndef CONFIG_SMP |
174 | void adjust_cr(unsigned long mask, unsigned long set) | |
175 | { | |
176 | unsigned long flags; | |
177 | ||
178 | mask &= ~CR_A; | |
179 | ||
180 | set &= mask; | |
181 | ||
182 | local_irq_save(flags); | |
183 | ||
184 | cr_no_alignment = (cr_no_alignment & ~mask) | set; | |
185 | cr_alignment = (cr_alignment & ~mask) | set; | |
186 | ||
187 | set_cr((get_cr() & ~mask) | set); | |
188 | ||
189 | local_irq_restore(flags); | |
190 | } | |
191 | #endif | |
192 | ||
0af92bef | 193 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_WRITE |
b1cce6b1 | 194 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 195 | |
b29e9f5e | 196 | static struct mem_type mem_types[] = { |
0af92bef | 197 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
198 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
199 | L_PTE_SHARED, | |
0af92bef | 200 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 201 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
202 | .domain = DOMAIN_IO, |
203 | }, | |
204 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 205 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 206 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 207 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
208 | .domain = DOMAIN_IO, |
209 | }, | |
210 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 211 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
212 | .prot_l1 = PMD_TYPE_TABLE, |
213 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
214 | .domain = DOMAIN_IO, | |
215 | }, | |
1ad77a87 | 216 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 217 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 218 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 219 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 220 | .domain = DOMAIN_IO, |
ae8f1541 | 221 | }, |
ebb4c658 RK |
222 | [MT_UNCACHED] = { |
223 | .prot_pte = PROT_PTE_DEVICE, | |
224 | .prot_l1 = PMD_TYPE_TABLE, | |
225 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
226 | .domain = DOMAIN_IO, | |
227 | }, | |
ae8f1541 | 228 | [MT_CACHECLEAN] = { |
9ef79635 | 229 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
230 | .domain = DOMAIN_KERNEL, |
231 | }, | |
232 | [MT_MINICLEAN] = { | |
9ef79635 | 233 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
234 | .domain = DOMAIN_KERNEL, |
235 | }, | |
236 | [MT_LOW_VECTORS] = { | |
237 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
238 | L_PTE_EXEC, | |
239 | .prot_l1 = PMD_TYPE_TABLE, | |
240 | .domain = DOMAIN_USER, | |
241 | }, | |
242 | [MT_HIGH_VECTORS] = { | |
243 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
244 | L_PTE_USER | L_PTE_EXEC, | |
245 | .prot_l1 = PMD_TYPE_TABLE, | |
246 | .domain = DOMAIN_USER, | |
247 | }, | |
248 | [MT_MEMORY] = { | |
f1a2481c | 249 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
7f58217b | 250 | L_PTE_WRITE | L_PTE_EXEC, |
f1a2481c | 251 | .prot_l1 = PMD_TYPE_TABLE, |
9ef79635 | 252 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
253 | .domain = DOMAIN_KERNEL, |
254 | }, | |
255 | [MT_ROM] = { | |
9ef79635 | 256 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
257 | .domain = DOMAIN_KERNEL, |
258 | }, | |
e4707dd3 | 259 | [MT_MEMORY_NONCACHED] = { |
f1a2481c | 260 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
7f58217b | 261 | L_PTE_WRITE | L_PTE_EXEC | L_PTE_MT_BUFFERABLE, |
f1a2481c | 262 | .prot_l1 = PMD_TYPE_TABLE, |
e4707dd3 PW |
263 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
264 | .domain = DOMAIN_KERNEL, | |
265 | }, | |
cb9d7707 | 266 | [MT_MEMORY_DTCM] = { |
f444fce3 LW |
267 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
268 | L_PTE_WRITE, | |
269 | .prot_l1 = PMD_TYPE_TABLE, | |
270 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
271 | .domain = DOMAIN_KERNEL, | |
cb9d7707 LW |
272 | }, |
273 | [MT_MEMORY_ITCM] = { | |
274 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
f444fce3 | 275 | L_PTE_WRITE | L_PTE_EXEC, |
cb9d7707 | 276 | .prot_l1 = PMD_TYPE_TABLE, |
f444fce3 | 277 | .domain = DOMAIN_KERNEL, |
cb9d7707 | 278 | }, |
ae8f1541 RK |
279 | }; |
280 | ||
b29e9f5e RK |
281 | const struct mem_type *get_mem_type(unsigned int type) |
282 | { | |
283 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
284 | } | |
69d3a84a | 285 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 286 | |
ae8f1541 RK |
287 | /* |
288 | * Adjust the PMD section entries according to the CPU in use. | |
289 | */ | |
290 | static void __init build_mem_type_table(void) | |
291 | { | |
292 | struct cachepolicy *cp; | |
293 | unsigned int cr = get_cr(); | |
bb30f36f | 294 | unsigned int user_pgprot, kern_pgprot, vecs_pgprot; |
ae8f1541 RK |
295 | int cpu_arch = cpu_architecture(); |
296 | int i; | |
297 | ||
11179d8c | 298 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 299 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
300 | if (cachepolicy > CPOLICY_BUFFERED) |
301 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 302 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
303 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
304 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 305 | #endif |
11179d8c | 306 | } |
ae8f1541 RK |
307 | if (cpu_arch < CPU_ARCH_ARMv5) { |
308 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
309 | cachepolicy = CPOLICY_WRITEBACK; | |
310 | ecc_mask = 0; | |
311 | } | |
f00ec48f RK |
312 | if (is_smp()) |
313 | cachepolicy = CPOLICY_WRITEALLOC; | |
ae8f1541 | 314 | |
1ad77a87 | 315 | /* |
b1cce6b1 RK |
316 | * Strip out features not present on earlier architectures. |
317 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
318 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 319 | */ |
b1cce6b1 RK |
320 | if (cpu_arch < CPU_ARCH_ARMv5) |
321 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
322 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
323 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
324 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
325 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
326 | |
327 | /* | |
b1cce6b1 RK |
328 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
329 | * "update-able on write" bit on ARM610). However, Xscale and | |
330 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 331 | */ |
b1cce6b1 | 332 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
9ef79635 | 333 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 334 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
335 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
336 | } | |
337 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
338 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
339 | if (mem_types[i].prot_l1) |
340 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
341 | if (mem_types[i].prot_sect) |
342 | mem_types[i].prot_sect |= PMD_BIT4; | |
343 | } | |
344 | } | |
ae8f1541 | 345 | |
b1cce6b1 RK |
346 | /* |
347 | * Mark the device areas according to the CPU/architecture. | |
348 | */ | |
349 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
350 | if (!cpu_is_xsc3()) { | |
351 | /* | |
352 | * Mark device regions on ARMv6+ as execute-never | |
353 | * to prevent speculative instruction fetches. | |
354 | */ | |
355 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
356 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
357 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
358 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
359 | } | |
360 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
361 | /* | |
362 | * For ARMv7 with TEX remapping, | |
363 | * - shared device is SXCB=1100 | |
364 | * - nonshared device is SXCB=0100 | |
365 | * - write combine device mem is SXCB=0001 | |
366 | * (Uncached Normal memory) | |
367 | */ | |
368 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
369 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
370 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
371 | } else if (cpu_is_xsc3()) { | |
372 | /* | |
373 | * For Xscale3, | |
374 | * - shared device is TEXCB=00101 | |
375 | * - nonshared device is TEXCB=01000 | |
376 | * - write combine device mem is TEXCB=00100 | |
377 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
378 | */ | |
379 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
380 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
381 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
382 | } else { | |
383 | /* | |
384 | * For ARMv6 and ARMv7 without TEX remapping, | |
385 | * - shared device is TEXCB=00001 | |
386 | * - nonshared device is TEXCB=01000 | |
387 | * - write combine device mem is TEXCB=00100 | |
388 | * (Uncached Normal in ARMv6 parlance). | |
389 | */ | |
390 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
391 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
392 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
393 | } | |
394 | } else { | |
395 | /* | |
396 | * On others, write combining is "Uncached/Buffered" | |
397 | */ | |
398 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
399 | } | |
400 | ||
401 | /* | |
402 | * Now deal with the memory-type mappings | |
403 | */ | |
ae8f1541 | 404 | cp = &cache_policies[cachepolicy]; |
bb30f36f RK |
405 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
406 | ||
bb30f36f RK |
407 | /* |
408 | * Only use write-through for non-SMP systems | |
409 | */ | |
f00ec48f | 410 | if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) |
bb30f36f | 411 | vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; |
ae8f1541 RK |
412 | |
413 | /* | |
414 | * Enable CPU-specific coherency if supported. | |
415 | * (Only available on XSC3 at the moment.) | |
416 | */ | |
f1a2481c | 417 | if (arch_is_coherent() && cpu_is_xsc3()) { |
b1cce6b1 | 418 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
f1a2481c SS |
419 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; |
420 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; | |
421 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
422 | } | |
ae8f1541 RK |
423 | /* |
424 | * ARMv6 and above have extended page tables. | |
425 | */ | |
426 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
ae8f1541 RK |
427 | /* |
428 | * Mark cache clean areas and XIP ROM read only | |
429 | * from SVC mode and no access from userspace. | |
430 | */ | |
431 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
432 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
433 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
434 | ||
f00ec48f RK |
435 | if (is_smp()) { |
436 | /* | |
437 | * Mark memory with the "shared" attribute | |
438 | * for SMP systems | |
439 | */ | |
440 | user_pgprot |= L_PTE_SHARED; | |
441 | kern_pgprot |= L_PTE_SHARED; | |
442 | vecs_pgprot |= L_PTE_SHARED; | |
443 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; | |
444 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; | |
445 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; | |
446 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; | |
447 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; | |
448 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; | |
449 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; | |
450 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
451 | } | |
ae8f1541 RK |
452 | } |
453 | ||
e4707dd3 PW |
454 | /* |
455 | * Non-cacheable Normal - intended for memory areas that must | |
456 | * not cause dirty cache line writebacks when used | |
457 | */ | |
458 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
459 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
460 | /* Non-cacheable Normal is XCB = 001 */ | |
461 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
462 | PMD_SECT_BUFFERED; | |
463 | } else { | |
464 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
465 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
466 | PMD_SECT_TEX(1); | |
467 | } | |
468 | } else { | |
469 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; | |
470 | } | |
471 | ||
ae8f1541 RK |
472 | for (i = 0; i < 16; i++) { |
473 | unsigned long v = pgprot_val(protection_map[i]); | |
bb30f36f | 474 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
475 | } |
476 | ||
bb30f36f RK |
477 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
478 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 479 | |
44b18693 | 480 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 481 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
6dc995a3 | 482 | L_PTE_DIRTY | L_PTE_WRITE | kern_pgprot); |
ae8f1541 RK |
483 | |
484 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
485 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
486 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; | |
f1a2481c SS |
487 | mem_types[MT_MEMORY].prot_pte |= kern_pgprot; |
488 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; | |
ae8f1541 RK |
489 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
490 | ||
491 | switch (cp->pmd) { | |
492 | case PMD_SECT_WT: | |
493 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
494 | break; | |
495 | case PMD_SECT_WB: | |
496 | case PMD_SECT_WBWA: | |
497 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
498 | break; | |
499 | } | |
500 | printk("Memory policy: ECC %sabled, Data cache %s\n", | |
501 | ecc_mask ? "en" : "dis", cp->policy); | |
2497f0a8 RK |
502 | |
503 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
504 | struct mem_type *t = &mem_types[i]; | |
505 | if (t->prot_l1) | |
506 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
507 | if (t->prot_sect) | |
508 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
509 | } | |
ae8f1541 RK |
510 | } |
511 | ||
d907387c CM |
512 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
513 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
514 | unsigned long size, pgprot_t vma_prot) | |
515 | { | |
516 | if (!pfn_valid(pfn)) | |
517 | return pgprot_noncached(vma_prot); | |
518 | else if (file->f_flags & O_SYNC) | |
519 | return pgprot_writecombine(vma_prot); | |
520 | return vma_prot; | |
521 | } | |
522 | EXPORT_SYMBOL(phys_mem_access_prot); | |
523 | #endif | |
524 | ||
ae8f1541 RK |
525 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
526 | ||
3abe9d33 RK |
527 | static void __init *early_alloc(unsigned long sz) |
528 | { | |
2778f620 RK |
529 | void *ptr = __va(memblock_alloc(sz, sz)); |
530 | memset(ptr, 0, sz); | |
531 | return ptr; | |
3abe9d33 RK |
532 | } |
533 | ||
4bb2e27d | 534 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) |
ae8f1541 | 535 | { |
24e6c699 | 536 | if (pmd_none(*pmd)) { |
4bb2e27d RK |
537 | pte_t *pte = early_alloc(2 * PTRS_PER_PTE * sizeof(pte_t)); |
538 | __pmd_populate(pmd, __pa(pte) | prot); | |
24e6c699 | 539 | } |
4bb2e27d RK |
540 | BUG_ON(pmd_bad(*pmd)); |
541 | return pte_offset_kernel(pmd, addr); | |
542 | } | |
ae8f1541 | 543 | |
4bb2e27d RK |
544 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
545 | unsigned long end, unsigned long pfn, | |
546 | const struct mem_type *type) | |
547 | { | |
548 | pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); | |
24e6c699 | 549 | do { |
40d192b6 | 550 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
24e6c699 RK |
551 | pfn++; |
552 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
553 | } |
554 | ||
24e6c699 RK |
555 | static void __init alloc_init_section(pgd_t *pgd, unsigned long addr, |
556 | unsigned long end, unsigned long phys, | |
557 | const struct mem_type *type) | |
ae8f1541 | 558 | { |
24e6c699 | 559 | pmd_t *pmd = pmd_offset(pgd, addr); |
ae8f1541 | 560 | |
24e6c699 RK |
561 | /* |
562 | * Try a section mapping - end, addr and phys must all be aligned | |
563 | * to a section boundary. Note that PMDs refer to the individual | |
564 | * L1 entries, whereas PGDs refer to a group of L1 entries making | |
565 | * up one logical pointer to an L2 table. | |
566 | */ | |
567 | if (((addr | end | phys) & ~SECTION_MASK) == 0) { | |
568 | pmd_t *p = pmd; | |
ae8f1541 | 569 | |
24e6c699 RK |
570 | if (addr & SECTION_SIZE) |
571 | pmd++; | |
572 | ||
573 | do { | |
574 | *pmd = __pmd(phys | type->prot_sect); | |
575 | phys += SECTION_SIZE; | |
576 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
ae8f1541 | 577 | |
24e6c699 RK |
578 | flush_pmd_entry(p); |
579 | } else { | |
580 | /* | |
581 | * No need to loop; pte's aren't interested in the | |
582 | * individual L1 entries. | |
583 | */ | |
584 | alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); | |
585 | } | |
ae8f1541 RK |
586 | } |
587 | ||
4a56c1e4 RK |
588 | static void __init create_36bit_mapping(struct map_desc *md, |
589 | const struct mem_type *type) | |
590 | { | |
591 | unsigned long phys, addr, length, end; | |
592 | pgd_t *pgd; | |
593 | ||
594 | addr = md->virtual; | |
595 | phys = (unsigned long)__pfn_to_phys(md->pfn); | |
596 | length = PAGE_ALIGN(md->length); | |
597 | ||
598 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
599 | printk(KERN_ERR "MM: CPU does not support supersection " | |
600 | "mapping for 0x%08llx at 0x%08lx\n", | |
601 | __pfn_to_phys((u64)md->pfn), addr); | |
602 | return; | |
603 | } | |
604 | ||
605 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
606 | * Since domain assignments can in fact be arbitrary, the | |
607 | * 'domain == 0' check below is required to insure that ARMv6 | |
608 | * supersections are only allocated for domain 0 regardless | |
609 | * of the actual domain assignments in use. | |
610 | */ | |
611 | if (type->domain) { | |
612 | printk(KERN_ERR "MM: invalid domain in supersection " | |
613 | "mapping for 0x%08llx at 0x%08lx\n", | |
614 | __pfn_to_phys((u64)md->pfn), addr); | |
615 | return; | |
616 | } | |
617 | ||
618 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
619 | printk(KERN_ERR "MM: cannot create mapping for " | |
620 | "0x%08llx at 0x%08lx invalid alignment\n", | |
621 | __pfn_to_phys((u64)md->pfn), addr); | |
622 | return; | |
623 | } | |
624 | ||
625 | /* | |
626 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
627 | * (See ARMv6 spec). | |
628 | */ | |
629 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
630 | ||
631 | pgd = pgd_offset_k(addr); | |
632 | end = addr + length; | |
633 | do { | |
634 | pmd_t *pmd = pmd_offset(pgd, addr); | |
635 | int i; | |
636 | ||
637 | for (i = 0; i < 16; i++) | |
638 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); | |
639 | ||
640 | addr += SUPERSECTION_SIZE; | |
641 | phys += SUPERSECTION_SIZE; | |
642 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
643 | } while (addr != end); | |
644 | } | |
645 | ||
ae8f1541 RK |
646 | /* |
647 | * Create the page directory entries and any necessary | |
648 | * page tables for the mapping specified by `md'. We | |
649 | * are able to cope here with varying sizes and address | |
650 | * offsets, and we take full advantage of sections and | |
651 | * supersections. | |
652 | */ | |
a2227120 | 653 | static void __init create_mapping(struct map_desc *md) |
ae8f1541 | 654 | { |
24e6c699 | 655 | unsigned long phys, addr, length, end; |
d5c98176 | 656 | const struct mem_type *type; |
24e6c699 | 657 | pgd_t *pgd; |
ae8f1541 RK |
658 | |
659 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
660 | printk(KERN_WARNING "BUG: not creating mapping for " | |
661 | "0x%08llx at 0x%08lx in user region\n", | |
662 | __pfn_to_phys((u64)md->pfn), md->virtual); | |
663 | return; | |
664 | } | |
665 | ||
666 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
667 | md->virtual >= PAGE_OFFSET && md->virtual < VMALLOC_END) { | |
668 | printk(KERN_WARNING "BUG: mapping for 0x%08llx at 0x%08lx " | |
669 | "overlaps vmalloc space\n", | |
670 | __pfn_to_phys((u64)md->pfn), md->virtual); | |
671 | } | |
672 | ||
d5c98176 | 673 | type = &mem_types[md->type]; |
ae8f1541 RK |
674 | |
675 | /* | |
676 | * Catch 36-bit addresses | |
677 | */ | |
4a56c1e4 RK |
678 | if (md->pfn >= 0x100000) { |
679 | create_36bit_mapping(md, type); | |
680 | return; | |
ae8f1541 RK |
681 | } |
682 | ||
7b9c7b4d | 683 | addr = md->virtual & PAGE_MASK; |
24e6c699 | 684 | phys = (unsigned long)__pfn_to_phys(md->pfn); |
7b9c7b4d | 685 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 686 | |
24e6c699 | 687 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
ae8f1541 RK |
688 | printk(KERN_WARNING "BUG: map for 0x%08lx at 0x%08lx can not " |
689 | "be mapped using pages, ignoring.\n", | |
24e6c699 | 690 | __pfn_to_phys(md->pfn), addr); |
ae8f1541 RK |
691 | return; |
692 | } | |
693 | ||
24e6c699 RK |
694 | pgd = pgd_offset_k(addr); |
695 | end = addr + length; | |
696 | do { | |
697 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 698 | |
24e6c699 | 699 | alloc_init_section(pgd, addr, next, phys, type); |
ae8f1541 | 700 | |
24e6c699 RK |
701 | phys += next - addr; |
702 | addr = next; | |
703 | } while (pgd++, addr != end); | |
ae8f1541 RK |
704 | } |
705 | ||
706 | /* | |
707 | * Create the architecture specific mappings | |
708 | */ | |
709 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
710 | { | |
711 | int i; | |
712 | ||
713 | for (i = 0; i < nr; i++) | |
714 | create_mapping(io_desc + i); | |
715 | } | |
716 | ||
79612395 | 717 | static void * __initdata vmalloc_min = (void *)(VMALLOC_END - SZ_128M); |
6c5da7ac RK |
718 | |
719 | /* | |
720 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
721 | * bytes. This can be used to increase (or decrease) the vmalloc | |
722 | * area - the default is 128m. | |
723 | */ | |
2b0d8c25 | 724 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 725 | { |
79612395 | 726 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
6c5da7ac RK |
727 | |
728 | if (vmalloc_reserve < SZ_16M) { | |
729 | vmalloc_reserve = SZ_16M; | |
730 | printk(KERN_WARNING | |
731 | "vmalloc area too small, limiting to %luMB\n", | |
732 | vmalloc_reserve >> 20); | |
733 | } | |
9210807c NP |
734 | |
735 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { | |
736 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); | |
737 | printk(KERN_WARNING | |
738 | "vmalloc area is too big, limiting to %luMB\n", | |
739 | vmalloc_reserve >> 20); | |
740 | } | |
79612395 RK |
741 | |
742 | vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); | |
2b0d8c25 | 743 | return 0; |
6c5da7ac | 744 | } |
2b0d8c25 | 745 | early_param("vmalloc", early_vmalloc); |
6c5da7ac | 746 | |
4b5f32ce | 747 | static void __init sanity_check_meminfo(void) |
60296c71 | 748 | { |
dde5828f | 749 | int i, j, highmem = 0; |
60296c71 | 750 | |
4e929d2b | 751 | memblock_set_current_limit(__pa(vmalloc_min - 1) + 1); |
2778f620 | 752 | |
4b5f32ce | 753 | for (i = 0, j = 0; i < meminfo.nr_banks; i++) { |
a1bbaec0 NP |
754 | struct membank *bank = &meminfo.bank[j]; |
755 | *bank = meminfo.bank[i]; | |
60296c71 | 756 | |
a1bbaec0 | 757 | #ifdef CONFIG_HIGHMEM |
79612395 | 758 | if (__va(bank->start) > vmalloc_min || |
dde5828f RK |
759 | __va(bank->start) < (void *)PAGE_OFFSET) |
760 | highmem = 1; | |
761 | ||
762 | bank->highmem = highmem; | |
763 | ||
a1bbaec0 NP |
764 | /* |
765 | * Split those memory banks which are partially overlapping | |
766 | * the vmalloc area greatly simplifying things later. | |
767 | */ | |
79612395 RK |
768 | if (__va(bank->start) < vmalloc_min && |
769 | bank->size > vmalloc_min - __va(bank->start)) { | |
a1bbaec0 NP |
770 | if (meminfo.nr_banks >= NR_BANKS) { |
771 | printk(KERN_CRIT "NR_BANKS too low, " | |
772 | "ignoring high memory\n"); | |
773 | } else { | |
774 | memmove(bank + 1, bank, | |
775 | (meminfo.nr_banks - i) * sizeof(*bank)); | |
776 | meminfo.nr_banks++; | |
777 | i++; | |
79612395 RK |
778 | bank[1].size -= vmalloc_min - __va(bank->start); |
779 | bank[1].start = __pa(vmalloc_min - 1) + 1; | |
dde5828f | 780 | bank[1].highmem = highmem = 1; |
a1bbaec0 NP |
781 | j++; |
782 | } | |
79612395 | 783 | bank->size = vmalloc_min - __va(bank->start); |
a1bbaec0 NP |
784 | } |
785 | #else | |
041d785f RK |
786 | bank->highmem = highmem; |
787 | ||
a1bbaec0 NP |
788 | /* |
789 | * Check whether this memory bank would entirely overlap | |
790 | * the vmalloc area. | |
791 | */ | |
79612395 | 792 | if (__va(bank->start) >= vmalloc_min || |
f0bba9f9 | 793 | __va(bank->start) < (void *)PAGE_OFFSET) { |
a1bbaec0 NP |
794 | printk(KERN_NOTICE "Ignoring RAM at %.8lx-%.8lx " |
795 | "(vmalloc region overlap).\n", | |
796 | bank->start, bank->start + bank->size - 1); | |
797 | continue; | |
798 | } | |
60296c71 | 799 | |
a1bbaec0 NP |
800 | /* |
801 | * Check whether this memory bank would partially overlap | |
802 | * the vmalloc area. | |
803 | */ | |
79612395 | 804 | if (__va(bank->start + bank->size) > vmalloc_min || |
a1bbaec0 | 805 | __va(bank->start + bank->size) < __va(bank->start)) { |
79612395 | 806 | unsigned long newsize = vmalloc_min - __va(bank->start); |
a1bbaec0 NP |
807 | printk(KERN_NOTICE "Truncating RAM at %.8lx-%.8lx " |
808 | "to -%.8lx (vmalloc region overlap).\n", | |
809 | bank->start, bank->start + bank->size - 1, | |
810 | bank->start + newsize - 1); | |
811 | bank->size = newsize; | |
812 | } | |
813 | #endif | |
814 | j++; | |
60296c71 | 815 | } |
e616c591 RK |
816 | #ifdef CONFIG_HIGHMEM |
817 | if (highmem) { | |
818 | const char *reason = NULL; | |
819 | ||
820 | if (cache_is_vipt_aliasing()) { | |
821 | /* | |
822 | * Interactions between kmap and other mappings | |
823 | * make highmem support with aliasing VIPT caches | |
824 | * rather difficult. | |
825 | */ | |
826 | reason = "with VIPT aliasing cache"; | |
f00ec48f | 827 | } else if (is_smp() && tlb_ops_need_broadcast()) { |
e616c591 RK |
828 | /* |
829 | * kmap_high needs to occasionally flush TLB entries, | |
830 | * however, if the TLB entries need to be broadcast | |
831 | * we may deadlock: | |
832 | * kmap_high(irqs off)->flush_all_zero_pkmaps-> | |
833 | * flush_tlb_kernel_range->smp_call_function_many | |
834 | * (must not be called with irqs off) | |
835 | */ | |
836 | reason = "without hardware TLB ops broadcasting"; | |
e616c591 RK |
837 | } |
838 | if (reason) { | |
839 | printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", | |
840 | reason); | |
841 | while (j > 0 && meminfo.bank[j - 1].highmem) | |
842 | j--; | |
843 | } | |
844 | } | |
845 | #endif | |
4b5f32ce | 846 | meminfo.nr_banks = j; |
60296c71 LB |
847 | } |
848 | ||
4b5f32ce | 849 | static inline void prepare_page_table(void) |
d111e8f9 RK |
850 | { |
851 | unsigned long addr; | |
852 | ||
853 | /* | |
854 | * Clear out all the mappings below the kernel image. | |
855 | */ | |
ab4f2ee1 | 856 | for (addr = 0; addr < MODULES_VADDR; addr += PGDIR_SIZE) |
d111e8f9 RK |
857 | pmd_clear(pmd_off_k(addr)); |
858 | ||
859 | #ifdef CONFIG_XIP_KERNEL | |
860 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
37efe642 | 861 | addr = ((unsigned long)_etext + PGDIR_SIZE - 1) & PGDIR_MASK; |
d111e8f9 RK |
862 | #endif |
863 | for ( ; addr < PAGE_OFFSET; addr += PGDIR_SIZE) | |
864 | pmd_clear(pmd_off_k(addr)); | |
865 | ||
866 | /* | |
867 | * Clear out all the kernel space mappings, except for the first | |
868 | * memory bank, up to the end of the vmalloc region. | |
869 | */ | |
4b5f32ce | 870 | for (addr = __phys_to_virt(bank_phys_end(&meminfo.bank[0])); |
d111e8f9 RK |
871 | addr < VMALLOC_END; addr += PGDIR_SIZE) |
872 | pmd_clear(pmd_off_k(addr)); | |
873 | } | |
874 | ||
875 | /* | |
2778f620 | 876 | * Reserve the special regions of memory |
d111e8f9 | 877 | */ |
2778f620 | 878 | void __init arm_mm_memblock_reserve(void) |
d111e8f9 | 879 | { |
d111e8f9 RK |
880 | /* |
881 | * Reserve the page tables. These are already in use, | |
882 | * and can only be in node 0. | |
883 | */ | |
2778f620 | 884 | memblock_reserve(__pa(swapper_pg_dir), PTRS_PER_PGD * sizeof(pgd_t)); |
d111e8f9 | 885 | |
d111e8f9 RK |
886 | #ifdef CONFIG_SA1111 |
887 | /* | |
888 | * Because of the SA1111 DMA bug, we want to preserve our | |
889 | * precious DMA-able memory... | |
890 | */ | |
2778f620 | 891 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
d111e8f9 | 892 | #endif |
d111e8f9 RK |
893 | } |
894 | ||
895 | /* | |
896 | * Set up device the mappings. Since we clear out the page tables for all | |
897 | * mappings above VMALLOC_END, we will remove any debug device mappings. | |
898 | * This means you have to be careful how you debug this function, or any | |
899 | * called function. This means you can't use any function or debugging | |
900 | * method which may touch any device, otherwise the kernel _will_ crash. | |
901 | */ | |
902 | static void __init devicemaps_init(struct machine_desc *mdesc) | |
903 | { | |
904 | struct map_desc map; | |
905 | unsigned long addr; | |
906 | void *vectors; | |
907 | ||
908 | /* | |
909 | * Allocate the vector page early. | |
910 | */ | |
3abe9d33 | 911 | vectors = early_alloc(PAGE_SIZE); |
d111e8f9 RK |
912 | |
913 | for (addr = VMALLOC_END; addr; addr += PGDIR_SIZE) | |
914 | pmd_clear(pmd_off_k(addr)); | |
915 | ||
916 | /* | |
917 | * Map the kernel if it is XIP. | |
918 | * It is always first in the modulearea. | |
919 | */ | |
920 | #ifdef CONFIG_XIP_KERNEL | |
921 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 922 | map.virtual = MODULES_VADDR; |
37efe642 | 923 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
924 | map.type = MT_ROM; |
925 | create_mapping(&map); | |
926 | #endif | |
927 | ||
928 | /* | |
929 | * Map the cache flushing regions. | |
930 | */ | |
931 | #ifdef FLUSH_BASE | |
932 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
933 | map.virtual = FLUSH_BASE; | |
934 | map.length = SZ_1M; | |
935 | map.type = MT_CACHECLEAN; | |
936 | create_mapping(&map); | |
937 | #endif | |
938 | #ifdef FLUSH_BASE_MINICACHE | |
939 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
940 | map.virtual = FLUSH_BASE_MINICACHE; | |
941 | map.length = SZ_1M; | |
942 | map.type = MT_MINICLEAN; | |
943 | create_mapping(&map); | |
944 | #endif | |
945 | ||
946 | /* | |
947 | * Create a mapping for the machine vectors at the high-vectors | |
948 | * location (0xffff0000). If we aren't using high-vectors, also | |
949 | * create a mapping at the low-vectors virtual address. | |
950 | */ | |
951 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); | |
952 | map.virtual = 0xffff0000; | |
953 | map.length = PAGE_SIZE; | |
954 | map.type = MT_HIGH_VECTORS; | |
955 | create_mapping(&map); | |
956 | ||
957 | if (!vectors_high()) { | |
958 | map.virtual = 0; | |
959 | map.type = MT_LOW_VECTORS; | |
960 | create_mapping(&map); | |
961 | } | |
962 | ||
963 | /* | |
964 | * Ask the machine support to map in the statically mapped devices. | |
965 | */ | |
966 | if (mdesc->map_io) | |
967 | mdesc->map_io(); | |
968 | ||
969 | /* | |
970 | * Finally flush the caches and tlb to ensure that we're in a | |
971 | * consistent state wrt the writebuffer. This also ensures that | |
972 | * any write-allocated cache lines in the vector page are written | |
973 | * back. After this point, we can start to touch devices again. | |
974 | */ | |
975 | local_flush_tlb_all(); | |
976 | flush_cache_all(); | |
977 | } | |
978 | ||
d73cd428 NP |
979 | static void __init kmap_init(void) |
980 | { | |
981 | #ifdef CONFIG_HIGHMEM | |
4bb2e27d RK |
982 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
983 | PKMAP_BASE, _PAGE_KERNEL_TABLE); | |
d73cd428 NP |
984 | #endif |
985 | } | |
986 | ||
a2227120 RK |
987 | static inline void map_memory_bank(struct membank *bank) |
988 | { | |
989 | struct map_desc map; | |
990 | ||
991 | map.pfn = bank_pfn_start(bank); | |
992 | map.virtual = __phys_to_virt(bank_phys_start(bank)); | |
993 | map.length = bank_phys_size(bank); | |
994 | map.type = MT_MEMORY; | |
995 | ||
996 | create_mapping(&map); | |
997 | } | |
998 | ||
999 | static void __init map_lowmem(void) | |
1000 | { | |
1001 | struct meminfo *mi = &meminfo; | |
1002 | int i; | |
1003 | ||
1004 | /* Map all the lowmem memory banks. */ | |
1005 | for (i = 0; i < mi->nr_banks; i++) { | |
1006 | struct membank *bank = &mi->bank[i]; | |
1007 | ||
1008 | if (!bank->highmem) | |
1009 | map_memory_bank(bank); | |
1010 | } | |
1011 | } | |
1012 | ||
d111e8f9 RK |
1013 | /* |
1014 | * paging_init() sets up the page tables, initialises the zone memory | |
1015 | * maps, and sets up the zero page, bad page and bad page tables. | |
1016 | */ | |
4b5f32ce | 1017 | void __init paging_init(struct machine_desc *mdesc) |
d111e8f9 RK |
1018 | { |
1019 | void *zero_page; | |
1020 | ||
1021 | build_mem_type_table(); | |
4b5f32ce NP |
1022 | sanity_check_meminfo(); |
1023 | prepare_page_table(); | |
a2227120 | 1024 | map_lowmem(); |
d111e8f9 | 1025 | devicemaps_init(mdesc); |
d73cd428 | 1026 | kmap_init(); |
d111e8f9 RK |
1027 | |
1028 | top_pmd = pmd_off_k(0xffff0000); | |
1029 | ||
3abe9d33 RK |
1030 | /* allocate the zero page. */ |
1031 | zero_page = early_alloc(PAGE_SIZE); | |
2778f620 | 1032 | |
8d717a52 | 1033 | bootmem_init(); |
2778f620 | 1034 | |
d111e8f9 | 1035 | empty_zero_page = virt_to_page(zero_page); |
421fe93c | 1036 | __flush_dcache_page(NULL, empty_zero_page); |
d111e8f9 | 1037 | } |
ae8f1541 RK |
1038 | |
1039 | /* | |
1040 | * In order to soft-boot, we need to insert a 1:1 mapping in place of | |
1041 | * the user-mode pages. This will then ensure that we have predictable | |
1042 | * results when turning the mmu off | |
1043 | */ | |
1044 | void setup_mm_for_reboot(char mode) | |
1045 | { | |
1046 | unsigned long base_pmdval; | |
1047 | pgd_t *pgd; | |
1048 | int i; | |
1049 | ||
3f2d4f56 MW |
1050 | /* |
1051 | * We need to access to user-mode page tables here. For kernel threads | |
1052 | * we don't have any user-mode mappings so we use the context that we | |
1053 | * "borrowed". | |
1054 | */ | |
1055 | pgd = current->active_mm->pgd; | |
ae8f1541 RK |
1056 | |
1057 | base_pmdval = PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | PMD_TYPE_SECT; | |
1058 | if (cpu_architecture() <= CPU_ARCH_ARMv5TEJ && !cpu_is_xscale()) | |
1059 | base_pmdval |= PMD_BIT4; | |
1060 | ||
1061 | for (i = 0; i < FIRST_USER_PGD_NR + USER_PTRS_PER_PGD; i++, pgd++) { | |
1062 | unsigned long pmdval = (i << PGDIR_SHIFT) | base_pmdval; | |
1063 | pmd_t *pmd; | |
1064 | ||
1065 | pmd = pmd_off(pgd, i << PGDIR_SHIFT); | |
1066 | pmd[0] = __pmd(pmdval); | |
1067 | pmd[1] = __pmd(pmdval + (1 << (PGDIR_SHIFT - 1))); | |
1068 | flush_pmd_entry(pmd); | |
1069 | } | |
ad3e6c0b TL |
1070 | |
1071 | local_flush_tlb_all(); | |
ae8f1541 | 1072 | } |