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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020 | |
3 | * | |
4 | * Copyright (C) 2000 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
d090ddda | 6 | * hacked for non-paged-MM by Hyok S. Choi, 2003. |
1da177e4 LT |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2 of the License, or | |
11 | * (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | * | |
22 | * | |
23 | * These are the low level assembler for performing cache and TLB | |
24 | * functions on the arm1020. | |
25 | * | |
26 | * CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt | |
27 | */ | |
28 | #include <linux/linkage.h> | |
1da177e4 LT |
29 | #include <linux/init.h> |
30 | #include <asm/assembler.h> | |
e6ae744d | 31 | #include <asm/asm-offsets.h> |
5ec9407d | 32 | #include <asm/hwcap.h> |
74945c86 | 33 | #include <asm/pgtable-hwdef.h> |
1da177e4 | 34 | #include <asm/pgtable.h> |
1da177e4 | 35 | #include <asm/ptrace.h> |
1da177e4 | 36 | |
00eb0f6b RK |
37 | #include "proc-macros.S" |
38 | ||
1da177e4 LT |
39 | /* |
40 | * This is the maximum size of an area which will be invalidated | |
41 | * using the single invalidate entry instructions. Anything larger | |
42 | * than this, and we go for the whole cache. | |
43 | * | |
44 | * This value should be chosen such that we choose the cheapest | |
45 | * alternative. | |
46 | */ | |
47 | #define MAX_AREA_SIZE 32768 | |
48 | ||
49 | /* | |
50 | * The size of one data cache line. | |
51 | */ | |
52 | #define CACHE_DLINESIZE 32 | |
53 | ||
54 | /* | |
55 | * The number of data cache segments. | |
56 | */ | |
57 | #define CACHE_DSEGMENTS 16 | |
58 | ||
59 | /* | |
60 | * The number of lines in a cache segment. | |
61 | */ | |
62 | #define CACHE_DENTRIES 64 | |
63 | ||
64 | /* | |
65 | * This is the size at which it becomes more efficient to | |
66 | * clean the whole cache, rather than using the individual | |
67 | * cache line maintainence instructions. | |
68 | */ | |
69 | #define CACHE_DLIMIT 32768 | |
70 | ||
71 | .text | |
72 | /* | |
73 | * cpu_arm1020_proc_init() | |
74 | */ | |
75 | ENTRY(cpu_arm1020_proc_init) | |
76 | mov pc, lr | |
77 | ||
78 | /* | |
79 | * cpu_arm1020_proc_fin() | |
80 | */ | |
81 | ENTRY(cpu_arm1020_proc_fin) | |
1da177e4 LT |
82 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
83 | bic r0, r0, #0x1000 @ ...i............ | |
84 | bic r0, r0, #0x000e @ ............wca. | |
85 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
9ca03a21 | 86 | mov pc, lr |
1da177e4 LT |
87 | |
88 | /* | |
89 | * cpu_arm1020_reset(loc) | |
90 | * | |
91 | * Perform a soft reset of the system. Put the CPU into the | |
92 | * same state as it would be if it had been reset, and branch | |
93 | * to what would be the reset vector. | |
94 | * | |
95 | * loc: location to jump to for soft reset | |
96 | */ | |
97 | .align 5 | |
98 | ENTRY(cpu_arm1020_reset) | |
99 | mov ip, #0 | |
100 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | |
101 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
d090ddda | 102 | #ifdef CONFIG_MMU |
1da177e4 | 103 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
d090ddda | 104 | #endif |
1da177e4 LT |
105 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register |
106 | bic ip, ip, #0x000f @ ............wcam | |
107 | bic ip, ip, #0x1100 @ ...i...s........ | |
108 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
109 | mov pc, r0 | |
110 | ||
111 | /* | |
112 | * cpu_arm1020_do_idle() | |
113 | */ | |
114 | .align 5 | |
115 | ENTRY(cpu_arm1020_do_idle) | |
116 | mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt | |
117 | mov pc, lr | |
118 | ||
119 | /* ================================= CACHE ================================ */ | |
120 | ||
121 | .align 5 | |
c8c90860 MW |
122 | |
123 | /* | |
124 | * flush_icache_all() | |
125 | * | |
126 | * Unconditionally clean and invalidate the entire icache. | |
127 | */ | |
128 | ENTRY(arm1020_flush_icache_all) | |
129 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
130 | mov r0, #0 | |
131 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
132 | #endif | |
133 | mov pc, lr | |
134 | ENDPROC(arm1020_flush_icache_all) | |
135 | ||
1da177e4 LT |
136 | /* |
137 | * flush_user_cache_all() | |
138 | * | |
139 | * Invalidate all cache entries in a particular address | |
140 | * space. | |
141 | */ | |
142 | ENTRY(arm1020_flush_user_cache_all) | |
143 | /* FALLTHROUGH */ | |
144 | /* | |
145 | * flush_kern_cache_all() | |
146 | * | |
147 | * Clean and invalidate the entire cache. | |
148 | */ | |
149 | ENTRY(arm1020_flush_kern_cache_all) | |
150 | mov r2, #VM_EXEC | |
151 | mov ip, #0 | |
152 | __flush_whole_cache: | |
153 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
154 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
155 | mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments | |
156 | 1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries | |
157 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index | |
158 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
159 | subs r3, r3, #1 << 26 | |
160 | bcs 2b @ entries 63 to 0 | |
161 | subs r1, r1, #1 << 5 | |
162 | bcs 1b @ segments 15 to 0 | |
163 | #endif | |
164 | tst r2, #VM_EXEC | |
165 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
166 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
167 | #endif | |
168 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
169 | mov pc, lr | |
170 | ||
171 | /* | |
172 | * flush_user_cache_range(start, end, flags) | |
173 | * | |
174 | * Invalidate a range of cache entries in the specified | |
175 | * address space. | |
176 | * | |
177 | * - start - start address (inclusive) | |
178 | * - end - end address (exclusive) | |
179 | * - flags - vm_flags for this space | |
180 | */ | |
181 | ENTRY(arm1020_flush_user_cache_range) | |
182 | mov ip, #0 | |
183 | sub r3, r1, r0 @ calculate total size | |
184 | cmp r3, #CACHE_DLIMIT | |
185 | bhs __flush_whole_cache | |
186 | ||
187 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
188 | mcr p15, 0, ip, c7, c10, 4 | |
189 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | |
190 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
191 | add r0, r0, #CACHE_DLINESIZE | |
192 | cmp r0, r1 | |
193 | blo 1b | |
194 | #endif | |
195 | tst r2, #VM_EXEC | |
196 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
197 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
198 | #endif | |
199 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
200 | mov pc, lr | |
201 | ||
202 | /* | |
203 | * coherent_kern_range(start, end) | |
204 | * | |
205 | * Ensure coherency between the Icache and the Dcache in the | |
206 | * region described by start. If you have non-snooping | |
207 | * Harvard caches, you need to implement this function. | |
208 | * | |
209 | * - start - virtual start address | |
210 | * - end - virtual end address | |
211 | */ | |
212 | ENTRY(arm1020_coherent_kern_range) | |
213 | /* FALLTRHOUGH */ | |
214 | ||
215 | /* | |
216 | * coherent_user_range(start, end) | |
217 | * | |
218 | * Ensure coherency between the Icache and the Dcache in the | |
219 | * region described by start. If you have non-snooping | |
220 | * Harvard caches, you need to implement this function. | |
221 | * | |
222 | * - start - virtual start address | |
223 | * - end - virtual end address | |
224 | */ | |
225 | ENTRY(arm1020_coherent_user_range) | |
226 | mov ip, #0 | |
227 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
228 | mcr p15, 0, ip, c7, c10, 4 | |
229 | 1: | |
230 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
231 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
232 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
233 | #endif | |
234 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
235 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
236 | #endif | |
237 | add r0, r0, #CACHE_DLINESIZE | |
238 | cmp r0, r1 | |
239 | blo 1b | |
240 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
241 | mov pc, lr | |
242 | ||
243 | /* | |
2c9b9c84 | 244 | * flush_kern_dcache_area(void *addr, size_t size) |
1da177e4 LT |
245 | * |
246 | * Ensure no D cache aliasing occurs, either with itself or | |
247 | * the I cache | |
248 | * | |
2c9b9c84 RK |
249 | * - addr - kernel address |
250 | * - size - region size | |
1da177e4 | 251 | */ |
2c9b9c84 | 252 | ENTRY(arm1020_flush_kern_dcache_area) |
1da177e4 LT |
253 | mov ip, #0 |
254 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
2c9b9c84 | 255 | add r1, r0, r1 |
1da177e4 LT |
256 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry |
257 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
258 | add r0, r0, #CACHE_DLINESIZE | |
259 | cmp r0, r1 | |
260 | blo 1b | |
261 | #endif | |
262 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
263 | mov pc, lr | |
264 | ||
265 | /* | |
266 | * dma_inv_range(start, end) | |
267 | * | |
268 | * Invalidate (discard) the specified virtual address range. | |
269 | * May not write back any entries. If 'start' or 'end' | |
270 | * are not cache line aligned, those lines must be written | |
271 | * back. | |
272 | * | |
273 | * - start - virtual start address | |
274 | * - end - virtual end address | |
275 | * | |
276 | * (same as v4wb) | |
277 | */ | |
702b94bf | 278 | arm1020_dma_inv_range: |
1da177e4 LT |
279 | mov ip, #0 |
280 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
281 | tst r0, #CACHE_DLINESIZE - 1 | |
282 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
283 | mcrne p15, 0, ip, c7, c10, 4 | |
284 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | |
285 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
286 | tst r1, #CACHE_DLINESIZE - 1 | |
287 | mcrne p15, 0, ip, c7, c10, 4 | |
288 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry | |
289 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
290 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
291 | add r0, r0, #CACHE_DLINESIZE | |
292 | cmp r0, r1 | |
293 | blo 1b | |
294 | #endif | |
295 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
296 | mov pc, lr | |
297 | ||
298 | /* | |
299 | * dma_clean_range(start, end) | |
300 | * | |
301 | * Clean the specified virtual address range. | |
302 | * | |
303 | * - start - virtual start address | |
304 | * - end - virtual end address | |
305 | * | |
306 | * (same as v4wb) | |
307 | */ | |
702b94bf | 308 | arm1020_dma_clean_range: |
1da177e4 LT |
309 | mov ip, #0 |
310 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
311 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
312 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
313 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
314 | add r0, r0, #CACHE_DLINESIZE | |
315 | cmp r0, r1 | |
316 | blo 1b | |
317 | #endif | |
318 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
319 | mov pc, lr | |
320 | ||
321 | /* | |
322 | * dma_flush_range(start, end) | |
323 | * | |
324 | * Clean and invalidate the specified virtual address range. | |
325 | * | |
326 | * - start - virtual start address | |
327 | * - end - virtual end address | |
328 | */ | |
329 | ENTRY(arm1020_dma_flush_range) | |
330 | mov ip, #0 | |
331 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
332 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
333 | mcr p15, 0, ip, c7, c10, 4 | |
334 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | |
335 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
336 | add r0, r0, #CACHE_DLINESIZE | |
337 | cmp r0, r1 | |
338 | blo 1b | |
339 | #endif | |
340 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
341 | mov pc, lr | |
342 | ||
a9c9147e RK |
343 | /* |
344 | * dma_map_area(start, size, dir) | |
345 | * - start - kernel virtual start address | |
346 | * - size - size of region | |
347 | * - dir - DMA direction | |
348 | */ | |
349 | ENTRY(arm1020_dma_map_area) | |
350 | add r1, r1, r0 | |
351 | cmp r2, #DMA_TO_DEVICE | |
352 | beq arm1020_dma_clean_range | |
353 | bcs arm1020_dma_inv_range | |
354 | b arm1020_dma_flush_range | |
355 | ENDPROC(arm1020_dma_map_area) | |
356 | ||
357 | /* | |
358 | * dma_unmap_area(start, size, dir) | |
359 | * - start - kernel virtual start address | |
360 | * - size - size of region | |
361 | * - dir - DMA direction | |
362 | */ | |
363 | ENTRY(arm1020_dma_unmap_area) | |
364 | mov pc, lr | |
365 | ENDPROC(arm1020_dma_unmap_area) | |
366 | ||
1da177e4 | 367 | ENTRY(arm1020_cache_fns) |
c8c90860 | 368 | .long arm1020_flush_icache_all |
1da177e4 LT |
369 | .long arm1020_flush_kern_cache_all |
370 | .long arm1020_flush_user_cache_all | |
371 | .long arm1020_flush_user_cache_range | |
372 | .long arm1020_coherent_kern_range | |
373 | .long arm1020_coherent_user_range | |
2c9b9c84 | 374 | .long arm1020_flush_kern_dcache_area |
a9c9147e RK |
375 | .long arm1020_dma_map_area |
376 | .long arm1020_dma_unmap_area | |
1da177e4 LT |
377 | .long arm1020_dma_flush_range |
378 | ||
379 | .align 5 | |
380 | ENTRY(cpu_arm1020_dcache_clean_area) | |
381 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
382 | mov ip, #0 | |
383 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
384 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
385 | add r0, r0, #CACHE_DLINESIZE | |
386 | subs r1, r1, #CACHE_DLINESIZE | |
387 | bhi 1b | |
388 | #endif | |
389 | mov pc, lr | |
390 | ||
391 | /* =============================== PageTable ============================== */ | |
392 | ||
393 | /* | |
394 | * cpu_arm1020_switch_mm(pgd) | |
395 | * | |
396 | * Set the translation base pointer to be as described by pgd. | |
397 | * | |
398 | * pgd: new page tables | |
399 | */ | |
400 | .align 5 | |
401 | ENTRY(cpu_arm1020_switch_mm) | |
d090ddda | 402 | #ifdef CONFIG_MMU |
1da177e4 LT |
403 | #ifndef CONFIG_CPU_DCACHE_DISABLE |
404 | mcr p15, 0, r3, c7, c10, 4 | |
405 | mov r1, #0xF @ 16 segments | |
406 | 1: mov r3, #0x3F @ 64 entries | |
407 | 2: mov ip, r3, LSL #26 @ shift up entry | |
408 | orr ip, ip, r1, LSL #5 @ shift in/up index | |
409 | mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry | |
410 | mov ip, #0 | |
411 | mcr p15, 0, ip, c7, c10, 4 | |
412 | subs r3, r3, #1 | |
413 | cmp r3, #0 | |
414 | bge 2b @ entries 3F to 0 | |
415 | subs r1, r1, #1 | |
416 | cmp r1, #0 | |
417 | bge 1b @ segments 15 to 0 | |
418 | ||
419 | #endif | |
420 | mov r1, #0 | |
421 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
422 | mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache | |
423 | #endif | |
424 | mcr p15, 0, r1, c7, c10, 4 @ drain WB | |
425 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | |
426 | mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs | |
d090ddda | 427 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
428 | mov pc, lr |
429 | ||
430 | /* | |
431 | * cpu_arm1020_set_pte(ptep, pte) | |
432 | * | |
433 | * Set a PTE and flush it out | |
434 | */ | |
435 | .align 5 | |
ad1ae2fe | 436 | ENTRY(cpu_arm1020_set_pte_ext) |
d090ddda | 437 | #ifdef CONFIG_MMU |
da091653 | 438 | armv3_set_pte_ext |
1da177e4 LT |
439 | mov r0, r0 |
440 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
441 | mcr p15, 0, r0, c7, c10, 4 | |
442 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
443 | #endif | |
444 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
d090ddda | 445 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
446 | mov pc, lr |
447 | ||
5085f3ff | 448 | __CPUINIT |
1da177e4 LT |
449 | |
450 | .type __arm1020_setup, #function | |
451 | __arm1020_setup: | |
452 | mov r0, #0 | |
453 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 | |
454 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 | |
d090ddda | 455 | #ifdef CONFIG_MMU |
1da177e4 | 456 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 |
d090ddda | 457 | #endif |
22b19086 RK |
458 | |
459 | adr r5, arm1020_crval | |
460 | ldmia r5, {r5, r6} | |
1da177e4 | 461 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
1da177e4 | 462 | bic r0, r0, r5 |
22b19086 | 463 | orr r0, r0, r6 |
1da177e4 LT |
464 | #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN |
465 | orr r0, r0, #0x4000 @ .R.. .... .... .... | |
466 | #endif | |
467 | mov pc, lr | |
468 | .size __arm1020_setup, . - __arm1020_setup | |
469 | ||
470 | /* | |
471 | * R | |
472 | * .RVI ZFRS BLDP WCAM | |
abaf48a0 | 473 | * .011 1001 ..11 0101 |
1da177e4 | 474 | */ |
22b19086 RK |
475 | .type arm1020_crval, #object |
476 | arm1020_crval: | |
477 | crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930 | |
1da177e4 LT |
478 | |
479 | __INITDATA | |
480 | ||
481 | /* | |
482 | * Purpose : Function pointers used to access above functions - all calls | |
483 | * come through these | |
484 | */ | |
485 | .type arm1020_processor_functions, #object | |
486 | arm1020_processor_functions: | |
487 | .word v4t_early_abort | |
4fb28474 | 488 | .word legacy_pabort |
1da177e4 LT |
489 | .word cpu_arm1020_proc_init |
490 | .word cpu_arm1020_proc_fin | |
491 | .word cpu_arm1020_reset | |
492 | .word cpu_arm1020_do_idle | |
493 | .word cpu_arm1020_dcache_clean_area | |
494 | .word cpu_arm1020_switch_mm | |
ad1ae2fe | 495 | .word cpu_arm1020_set_pte_ext |
1da177e4 LT |
496 | .size arm1020_processor_functions, . - arm1020_processor_functions |
497 | ||
498 | .section ".rodata" | |
499 | ||
500 | .type cpu_arch_name, #object | |
501 | cpu_arch_name: | |
502 | .asciz "armv5t" | |
503 | .size cpu_arch_name, . - cpu_arch_name | |
504 | ||
505 | .type cpu_elf_name, #object | |
506 | cpu_elf_name: | |
507 | .asciz "v5" | |
508 | .size cpu_elf_name, . - cpu_elf_name | |
509 | ||
510 | .type cpu_arm1020_name, #object | |
511 | cpu_arm1020_name: | |
512 | .ascii "ARM1020" | |
513 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
514 | .ascii "i" | |
515 | #endif | |
516 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
517 | .ascii "d" | |
518 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
519 | .ascii "(wt)" | |
520 | #else | |
521 | .ascii "(wb)" | |
522 | #endif | |
523 | #endif | |
524 | #ifndef CONFIG_CPU_BPREDICT_DISABLE | |
525 | .ascii "B" | |
526 | #endif | |
527 | #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN | |
528 | .ascii "RR" | |
529 | #endif | |
530 | .ascii "\0" | |
531 | .size cpu_arm1020_name, . - cpu_arm1020_name | |
532 | ||
533 | .align | |
534 | ||
02b7dd12 | 535 | .section ".proc.info.init", #alloc, #execinstr |
1da177e4 LT |
536 | |
537 | .type __arm1020_proc_info,#object | |
538 | __arm1020_proc_info: | |
539 | .long 0x4104a200 @ ARM 1020T (Architecture v5T) | |
540 | .long 0xff0ffff0 | |
8799ee9f RK |
541 | .long PMD_TYPE_SECT | \ |
542 | PMD_SECT_AP_WRITE | \ | |
543 | PMD_SECT_AP_READ | |
1da177e4 LT |
544 | .long PMD_TYPE_SECT | \ |
545 | PMD_SECT_AP_WRITE | \ | |
546 | PMD_SECT_AP_READ | |
547 | b __arm1020_setup | |
548 | .long cpu_arch_name | |
549 | .long cpu_elf_name | |
550 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | |
551 | .long cpu_arm1020_name | |
552 | .long arm1020_processor_functions | |
553 | .long v4wbi_tlb_fns | |
554 | .long v4wb_user_fns | |
555 | .long arm1020_cache_fns | |
556 | .size __arm1020_proc_info, . - __arm1020_proc_info |