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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-arm720.S: MMU functions for ARM720 | |
3 | * | |
4 | * Copyright (C) 2000 Steve Hill (sjhill@cotw.com) | |
5 | * Rob Scott (rscott@mtrob.fdns.net) | |
6 | * Copyright (C) 2000 ARM Limited, Deep Blue Solutions Ltd. | |
d090ddda | 7 | * hacked for non-paged-MM by Hyok S. Choi, 2004. |
1da177e4 LT |
8 | * |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * | |
24 | * These are the low level assembler for performing cache and TLB | |
25 | * functions on the ARM720T. The ARM720T has a writethrough IDC | |
26 | * cache, so we don't need to clean it. | |
27 | * | |
28 | * Changelog: | |
29 | * 05-09-2000 SJH Created by moving 720 specific functions | |
30 | * out of 'proc-arm6,7.S' per RMK discussion | |
31 | * 07-25-2000 SJH Added idle function. | |
32 | * 08-25-2000 DBS Updated for integration of ARM Ltd version. | |
d090ddda | 33 | * 04-20-2004 HSC modified for non-paged memory management mode. |
1da177e4 LT |
34 | */ |
35 | #include <linux/linkage.h> | |
36 | #include <linux/init.h> | |
37 | #include <asm/assembler.h> | |
e6ae744d | 38 | #include <asm/asm-offsets.h> |
5ec9407d | 39 | #include <asm/hwcap.h> |
74945c86 | 40 | #include <asm/pgtable-hwdef.h> |
1da177e4 | 41 | #include <asm/pgtable.h> |
1da177e4 | 42 | #include <asm/ptrace.h> |
1da177e4 | 43 | |
bb8d5a55 TG |
44 | #include "proc-macros.S" |
45 | ||
1da177e4 LT |
46 | /* |
47 | * Function: arm720_proc_init (void) | |
48 | * : arm720_proc_fin (void) | |
49 | * | |
50 | * Notes : This processor does not require these | |
51 | */ | |
52 | ENTRY(cpu_arm720_dcache_clean_area) | |
53 | ENTRY(cpu_arm720_proc_init) | |
54 | mov pc, lr | |
55 | ||
56 | ENTRY(cpu_arm720_proc_fin) | |
1da177e4 LT |
57 | mrc p15, 0, r0, c1, c0, 0 |
58 | bic r0, r0, #0x1000 @ ...i............ | |
59 | bic r0, r0, #0x000e @ ............wca. | |
60 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
9ca03a21 | 61 | mov pc, lr |
1da177e4 LT |
62 | |
63 | /* | |
64 | * Function: arm720_proc_do_idle(void) | |
65 | * Params : r0 = unused | |
25985edc | 66 | * Purpose : put the processor in proper idle mode |
1da177e4 LT |
67 | */ |
68 | ENTRY(cpu_arm720_do_idle) | |
69 | mov pc, lr | |
70 | ||
71 | /* | |
72 | * Function: arm720_switch_mm(unsigned long pgd_phys) | |
73 | * Params : pgd_phys Physical address of page table | |
74 | * Purpose : Perform a task switch, saving the old process' state and restoring | |
75 | * the new. | |
76 | */ | |
77 | ENTRY(cpu_arm720_switch_mm) | |
d090ddda | 78 | #ifdef CONFIG_MMU |
1da177e4 LT |
79 | mov r1, #0 |
80 | mcr p15, 0, r1, c7, c7, 0 @ invalidate cache | |
81 | mcr p15, 0, r0, c2, c0, 0 @ update page table ptr | |
82 | mcr p15, 0, r1, c8, c7, 0 @ flush TLB (v4) | |
d090ddda | 83 | #endif |
1da177e4 LT |
84 | mov pc, lr |
85 | ||
86 | /* | |
ad1ae2fe | 87 | * Function: arm720_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext) |
1da177e4 LT |
88 | * Params : r0 = Address to set |
89 | * : r1 = value to set | |
90 | * Purpose : Set a PTE and flush it out of any WB cache | |
91 | */ | |
da091653 | 92 | .align 5 |
ad1ae2fe | 93 | ENTRY(cpu_arm720_set_pte_ext) |
d090ddda | 94 | #ifdef CONFIG_MMU |
da091653 | 95 | armv3_set_pte_ext wc_disable=0 |
d090ddda | 96 | #endif |
da091653 | 97 | mov pc, lr |
1da177e4 LT |
98 | |
99 | /* | |
100 | * Function: arm720_reset | |
101 | * Params : r0 = address to jump to | |
102 | * Notes : This sets up everything for a reset | |
103 | */ | |
104 | ENTRY(cpu_arm720_reset) | |
105 | mov ip, #0 | |
106 | mcr p15, 0, ip, c7, c7, 0 @ invalidate cache | |
d090ddda | 107 | #ifdef CONFIG_MMU |
1da177e4 | 108 | mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4) |
d090ddda | 109 | #endif |
1da177e4 LT |
110 | mrc p15, 0, ip, c1, c0, 0 @ get ctrl register |
111 | bic ip, ip, #0x000f @ ............wcam | |
112 | bic ip, ip, #0x2100 @ ..v....s........ | |
113 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
114 | mov pc, r0 | |
115 | ||
5085f3ff | 116 | __CPUINIT |
1da177e4 LT |
117 | |
118 | .type __arm710_setup, #function | |
119 | __arm710_setup: | |
120 | mov r0, #0 | |
121 | mcr p15, 0, r0, c7, c7, 0 @ invalidate caches | |
d090ddda | 122 | #ifdef CONFIG_MMU |
1da177e4 | 123 | mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) |
d090ddda | 124 | #endif |
1da177e4 LT |
125 | mrc p15, 0, r0, c1, c0 @ get control register |
126 | ldr r5, arm710_cr1_clear | |
127 | bic r0, r0, r5 | |
128 | ldr r5, arm710_cr1_set | |
129 | orr r0, r0, r5 | |
130 | mov pc, lr @ __ret (head.S) | |
131 | .size __arm710_setup, . - __arm710_setup | |
132 | ||
133 | /* | |
134 | * R | |
135 | * .RVI ZFRS BLDP WCAM | |
136 | * .... 0001 ..11 1101 | |
137 | * | |
138 | */ | |
139 | .type arm710_cr1_clear, #object | |
140 | .type arm710_cr1_set, #object | |
141 | arm710_cr1_clear: | |
142 | .word 0x0f3f | |
143 | arm710_cr1_set: | |
144 | .word 0x013d | |
145 | ||
146 | .type __arm720_setup, #function | |
147 | __arm720_setup: | |
148 | mov r0, #0 | |
149 | mcr p15, 0, r0, c7, c7, 0 @ invalidate caches | |
d090ddda | 150 | #ifdef CONFIG_MMU |
1da177e4 | 151 | mcr p15, 0, r0, c8, c7, 0 @ flush TLB (v4) |
d090ddda | 152 | #endif |
22b19086 RK |
153 | adr r5, arm720_crval |
154 | ldmia r5, {r5, r6} | |
1da177e4 | 155 | mrc p15, 0, r0, c1, c0 @ get control register |
1da177e4 | 156 | bic r0, r0, r5 |
22b19086 | 157 | orr r0, r0, r6 |
1da177e4 LT |
158 | mov pc, lr @ __ret (head.S) |
159 | .size __arm720_setup, . - __arm720_setup | |
160 | ||
161 | /* | |
162 | * R | |
163 | * .RVI ZFRS BLDP WCAM | |
164 | * ..1. 1001 ..11 1101 | |
165 | * | |
166 | */ | |
22b19086 RK |
167 | .type arm720_crval, #object |
168 | arm720_crval: | |
169 | crval clear=0x00002f3f, mmuset=0x0000213d, ucset=0x00000130 | |
1da177e4 LT |
170 | |
171 | __INITDATA | |
172 | ||
173 | /* | |
174 | * Purpose : Function pointers used to access above functions - all calls | |
175 | * come through these | |
176 | */ | |
177 | .type arm720_processor_functions, #object | |
178 | ENTRY(arm720_processor_functions) | |
179 | .word v4t_late_abort | |
4fb28474 | 180 | .word legacy_pabort |
1da177e4 LT |
181 | .word cpu_arm720_proc_init |
182 | .word cpu_arm720_proc_fin | |
183 | .word cpu_arm720_reset | |
184 | .word cpu_arm720_do_idle | |
185 | .word cpu_arm720_dcache_clean_area | |
186 | .word cpu_arm720_switch_mm | |
ad1ae2fe | 187 | .word cpu_arm720_set_pte_ext |
f6b0fa02 RK |
188 | .word 0 |
189 | .word 0 | |
190 | .word 0 | |
1da177e4 LT |
191 | .size arm720_processor_functions, . - arm720_processor_functions |
192 | ||
193 | .section ".rodata" | |
194 | ||
195 | .type cpu_arch_name, #object | |
196 | cpu_arch_name: .asciz "armv4t" | |
197 | .size cpu_arch_name, . - cpu_arch_name | |
198 | ||
199 | .type cpu_elf_name, #object | |
200 | cpu_elf_name: .asciz "v4" | |
201 | .size cpu_elf_name, . - cpu_elf_name | |
202 | ||
203 | .type cpu_arm710_name, #object | |
204 | cpu_arm710_name: | |
205 | .asciz "ARM710T" | |
206 | .size cpu_arm710_name, . - cpu_arm710_name | |
207 | ||
208 | .type cpu_arm720_name, #object | |
209 | cpu_arm720_name: | |
210 | .asciz "ARM720T" | |
211 | .size cpu_arm720_name, . - cpu_arm720_name | |
212 | ||
213 | .align | |
214 | ||
215 | /* | |
4baa9922 | 216 | * See <asm/procinfo.h> for a definition of this structure. |
1da177e4 LT |
217 | */ |
218 | ||
02b7dd12 | 219 | .section ".proc.info.init", #alloc, #execinstr |
1da177e4 LT |
220 | |
221 | .type __arm710_proc_info, #object | |
222 | __arm710_proc_info: | |
223 | .long 0x41807100 @ cpu_val | |
224 | .long 0xffffff00 @ cpu_mask | |
225 | .long PMD_TYPE_SECT | \ | |
226 | PMD_SECT_BUFFERABLE | \ | |
227 | PMD_SECT_CACHEABLE | \ | |
228 | PMD_BIT4 | \ | |
229 | PMD_SECT_AP_WRITE | \ | |
230 | PMD_SECT_AP_READ | |
8799ee9f RK |
231 | .long PMD_TYPE_SECT | \ |
232 | PMD_BIT4 | \ | |
233 | PMD_SECT_AP_WRITE | \ | |
234 | PMD_SECT_AP_READ | |
1da177e4 LT |
235 | b __arm710_setup @ cpu_flush |
236 | .long cpu_arch_name @ arch_name | |
237 | .long cpu_elf_name @ elf_name | |
238 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB @ elf_hwcap | |
239 | .long cpu_arm710_name @ name | |
240 | .long arm720_processor_functions | |
241 | .long v4_tlb_fns | |
242 | .long v4wt_user_fns | |
243 | .long v4_cache_fns | |
244 | .size __arm710_proc_info, . - __arm710_proc_info | |
245 | ||
246 | .type __arm720_proc_info, #object | |
247 | __arm720_proc_info: | |
248 | .long 0x41807200 @ cpu_val | |
249 | .long 0xffffff00 @ cpu_mask | |
250 | .long PMD_TYPE_SECT | \ | |
251 | PMD_SECT_BUFFERABLE | \ | |
252 | PMD_SECT_CACHEABLE | \ | |
253 | PMD_BIT4 | \ | |
254 | PMD_SECT_AP_WRITE | \ | |
255 | PMD_SECT_AP_READ | |
8799ee9f RK |
256 | .long PMD_TYPE_SECT | \ |
257 | PMD_BIT4 | \ | |
258 | PMD_SECT_AP_WRITE | \ | |
259 | PMD_SECT_AP_READ | |
1da177e4 LT |
260 | b __arm720_setup @ cpu_flush |
261 | .long cpu_arch_name @ arch_name | |
262 | .long cpu_elf_name @ elf_name | |
263 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB @ elf_hwcap | |
264 | .long cpu_arm720_name @ name | |
265 | .long arm720_processor_functions | |
266 | .long v4_tlb_fns | |
267 | .long v4wt_user_fns | |
268 | .long v4_cache_fns | |
269 | .size __arm720_proc_info, . - __arm720_proc_info |