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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/arm925.S: MMU functions for ARM925 | |
3 | * | |
4 | * Copyright (C) 1999,2000 ARM Limited | |
5 | * Copyright (C) 2000 Deep Blue Solutions Ltd. | |
6 | * Copyright (C) 2002 RidgeRun, Inc. | |
7 | * Copyright (C) 2002-2003 MontaVista Software, Inc. | |
8 | * | |
9 | * Update for Linux-2.6 and cache flush improvements | |
10 | * Copyright (C) 2004 Nokia Corporation by Tony Lindgren <tony@atomide.com> | |
11 | * | |
12 | * This program is free software; you can redistribute it and/or modify | |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2 of the License, or | |
15 | * (at your option) any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; if not, write to the Free Software | |
24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
25 | * | |
26 | * | |
27 | * These are the low level assembler for performing cache and TLB | |
28 | * functions on the arm925. | |
29 | * | |
30 | * CONFIG_CPU_ARM925_CPU_IDLE -> nohlt | |
31 | * | |
32 | * Some additional notes based on deciphering the TI TRM on OMAP-5910: | |
33 | * | |
34 | * NOTE1: The TI925T Configuration Register bit "D-cache clean and flush | |
35 | * entry mode" must be 0 to flush the entries in both segments | |
36 | * at once. This is the default value. See TRM 2-20 and 2-24 for | |
37 | * more information. | |
38 | * | |
39 | * NOTE2: Default is the "D-cache clean and flush entry mode". It looks | |
40 | * like the "Transparent mode" must be on for partial cache flushes | |
41 | * to work in this mode. This mode only works with 16-bit external | |
42 | * memory. See TRM 2-24 for more information. | |
43 | * | |
44 | * NOTE3: Write-back cache flushing seems to be flakey with devices using | |
45 | * direct memory access, such as USB OHCI. The workaround is to use | |
46 | * write-through cache with CONFIG_CPU_DCACHE_WRITETHROUGH (this is | |
47 | * the default for OMAP-1510). | |
48 | */ | |
49 | ||
50 | #include <linux/linkage.h> | |
51 | #include <linux/config.h> | |
52 | #include <linux/init.h> | |
53 | #include <asm/assembler.h> | |
54 | #include <asm/pgtable.h> | |
55 | #include <asm/procinfo.h> | |
56 | #include <asm/hardware.h> | |
57 | #include <asm/page.h> | |
58 | #include <asm/ptrace.h> | |
59 | #include "proc-macros.S" | |
60 | ||
61 | /* | |
62 | * The size of one data cache line. | |
63 | */ | |
64 | #define CACHE_DLINESIZE 16 | |
65 | ||
66 | /* | |
67 | * The number of data cache segments. | |
68 | */ | |
69 | #define CACHE_DSEGMENTS 2 | |
70 | ||
71 | /* | |
72 | * The number of lines in a cache segment. | |
73 | */ | |
74 | #define CACHE_DENTRIES 256 | |
75 | ||
76 | /* | |
77 | * This is the size at which it becomes more efficient to | |
78 | * clean the whole cache, rather than using the individual | |
79 | * cache line maintainence instructions. | |
80 | */ | |
81 | #define CACHE_DLIMIT 8192 | |
82 | ||
83 | .text | |
84 | /* | |
85 | * cpu_arm925_proc_init() | |
86 | */ | |
87 | ENTRY(cpu_arm925_proc_init) | |
88 | mov pc, lr | |
89 | ||
90 | /* | |
91 | * cpu_arm925_proc_fin() | |
92 | */ | |
93 | ENTRY(cpu_arm925_proc_fin) | |
94 | stmfd sp!, {lr} | |
95 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE | |
96 | msr cpsr_c, ip | |
97 | bl arm925_flush_kern_cache_all | |
98 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | |
99 | bic r0, r0, #0x1000 @ ...i............ | |
100 | bic r0, r0, #0x000e @ ............wca. | |
101 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
102 | ldmfd sp!, {pc} | |
103 | ||
104 | /* | |
105 | * cpu_arm925_reset(loc) | |
106 | * | |
107 | * Perform a soft reset of the system. Put the CPU into the | |
108 | * same state as it would be if it had been reset, and branch | |
109 | * to what would be the reset vector. | |
110 | * | |
111 | * loc: location to jump to for soft reset | |
112 | */ | |
113 | .align 5 | |
114 | ENTRY(cpu_arm925_reset) | |
115 | /* Send software reset to MPU and DSP */ | |
116 | mov ip, #0xff000000 | |
117 | orr ip, ip, #0x00fe0000 | |
118 | orr ip, ip, #0x0000ce00 | |
119 | mov r4, #1 | |
120 | strh r4, [ip, #0x10] | |
121 | ||
122 | mov ip, #0 | |
123 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | |
124 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
125 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | |
126 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register | |
127 | bic ip, ip, #0x000f @ ............wcam | |
128 | bic ip, ip, #0x1100 @ ...i...s........ | |
129 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
130 | mov pc, r0 | |
131 | ||
132 | /* | |
133 | * cpu_arm925_do_idle() | |
134 | * | |
135 | * Called with IRQs disabled | |
136 | */ | |
137 | .align 10 | |
138 | ENTRY(cpu_arm925_do_idle) | |
139 | mov r0, #0 | |
140 | mrc p15, 0, r1, c1, c0, 0 @ Read control register | |
141 | mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer | |
142 | bic r2, r1, #1 << 12 | |
143 | mcr p15, 0, r2, c1, c0, 0 @ Disable I cache | |
144 | mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt | |
145 | mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable | |
146 | mov pc, lr | |
147 | ||
148 | /* | |
149 | * flush_user_cache_all() | |
150 | * | |
151 | * Clean and invalidate all cache entries in a particular | |
152 | * address space. | |
153 | */ | |
154 | ENTRY(arm925_flush_user_cache_all) | |
155 | /* FALLTHROUGH */ | |
156 | ||
157 | /* | |
158 | * flush_kern_cache_all() | |
159 | * | |
160 | * Clean and invalidate the entire cache. | |
161 | */ | |
162 | ENTRY(arm925_flush_kern_cache_all) | |
163 | mov r2, #VM_EXEC | |
164 | mov ip, #0 | |
165 | __flush_whole_cache: | |
166 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
167 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
168 | #else | |
169 | /* Flush entries in both segments at once, see NOTE1 above */ | |
170 | mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment | |
171 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index | |
172 | subs r3, r3, #1 << 4 | |
173 | bcs 2b @ entries 255 to 0 | |
174 | #endif | |
175 | tst r2, #VM_EXEC | |
176 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
177 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
178 | mov pc, lr | |
179 | ||
180 | /* | |
181 | * flush_user_cache_range(start, end, flags) | |
182 | * | |
183 | * Clean and invalidate a range of cache entries in the | |
184 | * specified address range. | |
185 | * | |
186 | * - start - start address (inclusive) | |
187 | * - end - end address (exclusive) | |
188 | * - flags - vm_flags describing address space | |
189 | */ | |
190 | ENTRY(arm925_flush_user_cache_range) | |
191 | mov ip, #0 | |
192 | sub r3, r1, r0 @ calculate total size | |
193 | cmp r3, #CACHE_DLIMIT | |
194 | bgt __flush_whole_cache | |
195 | 1: tst r2, #VM_EXEC | |
196 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
197 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
198 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
199 | add r0, r0, #CACHE_DLINESIZE | |
200 | mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
201 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
202 | add r0, r0, #CACHE_DLINESIZE | |
203 | #else | |
204 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | |
205 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
206 | add r0, r0, #CACHE_DLINESIZE | |
207 | mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry | |
208 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
209 | add r0, r0, #CACHE_DLINESIZE | |
210 | #endif | |
211 | cmp r0, r1 | |
212 | blo 1b | |
213 | tst r2, #VM_EXEC | |
214 | mcrne p15, 0, ip, c7, c10, 4 @ drain WB | |
215 | mov pc, lr | |
216 | ||
217 | /* | |
218 | * coherent_kern_range(start, end) | |
219 | * | |
220 | * Ensure coherency between the Icache and the Dcache in the | |
221 | * region described by start, end. If you have non-snooping | |
222 | * Harvard caches, you need to implement this function. | |
223 | * | |
224 | * - start - virtual start address | |
225 | * - end - virtual end address | |
226 | */ | |
227 | ENTRY(arm925_coherent_kern_range) | |
228 | /* FALLTHROUGH */ | |
229 | ||
230 | /* | |
231 | * coherent_user_range(start, end) | |
232 | * | |
233 | * Ensure coherency between the Icache and the Dcache in the | |
234 | * region described by start, end. If you have non-snooping | |
235 | * Harvard caches, you need to implement this function. | |
236 | * | |
237 | * - start - virtual start address | |
238 | * - end - virtual end address | |
239 | */ | |
240 | ENTRY(arm925_coherent_user_range) | |
241 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
242 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
243 | mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry | |
244 | add r0, r0, #CACHE_DLINESIZE | |
245 | cmp r0, r1 | |
246 | blo 1b | |
247 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
248 | mov pc, lr | |
249 | ||
250 | /* | |
251 | * flush_kern_dcache_page(void *page) | |
252 | * | |
253 | * Ensure no D cache aliasing occurs, either with itself or | |
254 | * the I cache | |
255 | * | |
256 | * - addr - page aligned address | |
257 | */ | |
258 | ENTRY(arm925_flush_kern_dcache_page) | |
259 | add r1, r0, #PAGE_SZ | |
260 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | |
261 | add r0, r0, #CACHE_DLINESIZE | |
262 | cmp r0, r1 | |
263 | blo 1b | |
264 | mov r0, #0 | |
265 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
266 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
267 | mov pc, lr | |
268 | ||
269 | /* | |
270 | * dma_inv_range(start, end) | |
271 | * | |
272 | * Invalidate (discard) the specified virtual address range. | |
273 | * May not write back any entries. If 'start' or 'end' | |
274 | * are not cache line aligned, those lines must be written | |
275 | * back. | |
276 | * | |
277 | * - start - virtual start address | |
278 | * - end - virtual end address | |
279 | * | |
280 | * (same as v4wb) | |
281 | */ | |
282 | ENTRY(arm925_dma_inv_range) | |
283 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
284 | tst r0, #CACHE_DLINESIZE - 1 | |
285 | mcrne p15, 0, r0, c7, c10, 1 @ clean D entry | |
286 | tst r1, #CACHE_DLINESIZE - 1 | |
287 | mcrne p15, 0, r1, c7, c10, 1 @ clean D entry | |
288 | #endif | |
289 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
290 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry | |
291 | add r0, r0, #CACHE_DLINESIZE | |
292 | cmp r0, r1 | |
293 | blo 1b | |
294 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
295 | mov pc, lr | |
296 | ||
297 | /* | |
298 | * dma_clean_range(start, end) | |
299 | * | |
300 | * Clean the specified virtual address range. | |
301 | * | |
302 | * - start - virtual start address | |
303 | * - end - virtual end address | |
304 | * | |
305 | * (same as v4wb) | |
306 | */ | |
307 | ENTRY(arm925_dma_clean_range) | |
308 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
309 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
310 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
311 | add r0, r0, #CACHE_DLINESIZE | |
312 | cmp r0, r1 | |
313 | blo 1b | |
314 | #endif | |
315 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
316 | mov pc, lr | |
317 | ||
318 | /* | |
319 | * dma_flush_range(start, end) | |
320 | * | |
321 | * Clean and invalidate the specified virtual address range. | |
322 | * | |
323 | * - start - virtual start address | |
324 | * - end - virtual end address | |
325 | */ | |
326 | ENTRY(arm925_dma_flush_range) | |
327 | bic r0, r0, #CACHE_DLINESIZE - 1 | |
328 | 1: | |
329 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
330 | mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry | |
331 | #else | |
332 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
333 | #endif | |
334 | add r0, r0, #CACHE_DLINESIZE | |
335 | cmp r0, r1 | |
336 | blo 1b | |
337 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
338 | mov pc, lr | |
339 | ||
340 | ENTRY(arm925_cache_fns) | |
341 | .long arm925_flush_kern_cache_all | |
342 | .long arm925_flush_user_cache_all | |
343 | .long arm925_flush_user_cache_range | |
344 | .long arm925_coherent_kern_range | |
345 | .long arm925_coherent_user_range | |
346 | .long arm925_flush_kern_dcache_page | |
347 | .long arm925_dma_inv_range | |
348 | .long arm925_dma_clean_range | |
349 | .long arm925_dma_flush_range | |
350 | ||
351 | ENTRY(cpu_arm925_dcache_clean_area) | |
352 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
353 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
354 | add r0, r0, #CACHE_DLINESIZE | |
355 | subs r1, r1, #CACHE_DLINESIZE | |
356 | bhi 1b | |
357 | #endif | |
358 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
359 | mov pc, lr | |
360 | ||
361 | /* =============================== PageTable ============================== */ | |
362 | ||
363 | /* | |
364 | * cpu_arm925_switch_mm(pgd) | |
365 | * | |
366 | * Set the translation base pointer to be as described by pgd. | |
367 | * | |
368 | * pgd: new page tables | |
369 | */ | |
370 | .align 5 | |
371 | ENTRY(cpu_arm925_switch_mm) | |
372 | mov ip, #0 | |
373 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
374 | mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache | |
375 | #else | |
376 | /* Flush entries in bothe segments at once, see NOTE1 above */ | |
377 | mov r3, #(CACHE_DENTRIES - 1) << 4 @ 256 entries in segment | |
378 | 2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index | |
379 | subs r3, r3, #1 << 4 | |
380 | bcs 2b @ entries 255 to 0 | |
381 | #endif | |
382 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
383 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
384 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer | |
385 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | |
386 | mov pc, lr | |
387 | ||
388 | /* | |
389 | * cpu_arm925_set_pte(ptep, pte) | |
390 | * | |
391 | * Set a PTE and flush it out | |
392 | */ | |
393 | .align 5 | |
394 | ENTRY(cpu_arm925_set_pte) | |
395 | str r1, [r0], #-2048 @ linux version | |
396 | ||
397 | eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY | |
398 | ||
399 | bic r2, r1, #PTE_SMALL_AP_MASK | |
400 | bic r2, r2, #PTE_TYPE_MASK | |
401 | orr r2, r2, #PTE_TYPE_SMALL | |
402 | ||
403 | tst r1, #L_PTE_USER @ User? | |
404 | orrne r2, r2, #PTE_SMALL_AP_URO_SRW | |
405 | ||
406 | tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? | |
407 | orreq r2, r2, #PTE_SMALL_AP_UNO_SRW | |
408 | ||
409 | tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? | |
410 | movne r2, #0 | |
411 | ||
412 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
413 | eor r3, r2, #0x0a @ C & small page? | |
414 | tst r3, #0x0b | |
415 | biceq r2, r2, #4 | |
416 | #endif | |
417 | str r2, [r0] @ hardware version | |
418 | mov r0, r0 | |
419 | #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH | |
420 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
421 | #endif | |
422 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
423 | mov pc, lr | |
424 | ||
425 | __INIT | |
426 | ||
427 | .type __arm925_setup, #function | |
428 | __arm925_setup: | |
429 | mov r0, #0 | |
430 | #if defined(CONFIG_CPU_ICACHE_STREAMING_DISABLE) | |
431 | orr r0,r0,#1 << 7 | |
432 | #endif | |
433 | ||
434 | /* Transparent on, D-cache clean & flush mode. See NOTE2 above */ | |
435 | orr r0,r0,#1 << 1 @ transparent mode on | |
436 | mcr p15, 0, r0, c15, c1, 0 @ write TI config register | |
437 | ||
438 | mov r0, #0 | |
439 | mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4 | |
440 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4 | |
441 | mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4 | |
442 | ||
443 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
444 | mov r0, #4 @ disable write-back on caches explicitly | |
445 | mcr p15, 7, r0, c15, c0, 0 | |
446 | #endif | |
447 | ||
448 | mrc p15, 0, r0, c1, c0 @ get control register v4 | |
449 | ldr r5, arm925_cr1_clear | |
450 | bic r0, r0, r5 | |
451 | ldr r5, arm925_cr1_set | |
452 | orr r0, r0, r5 | |
453 | #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN | |
454 | orr r0, r0, #0x4000 @ .1.. .... .... .... | |
455 | #endif | |
456 | mov pc, lr | |
457 | .size __arm925_setup, . - __arm925_setup | |
458 | ||
459 | /* | |
460 | * R | |
461 | * .RVI ZFRS BLDP WCAM | |
462 | * .011 0001 ..11 1101 | |
463 | * | |
464 | */ | |
465 | .type arm925_cr1_clear, #object | |
466 | .type arm925_cr1_set, #object | |
467 | arm925_cr1_clear: | |
468 | .word 0x7f3f | |
469 | arm925_cr1_set: | |
470 | .word 0x313d | |
471 | ||
472 | __INITDATA | |
473 | ||
474 | /* | |
475 | * Purpose : Function pointers used to access above functions - all calls | |
476 | * come through these | |
477 | */ | |
478 | .type arm925_processor_functions, #object | |
479 | arm925_processor_functions: | |
480 | .word v4t_early_abort | |
481 | .word cpu_arm925_proc_init | |
482 | .word cpu_arm925_proc_fin | |
483 | .word cpu_arm925_reset | |
484 | .word cpu_arm925_do_idle | |
485 | .word cpu_arm925_dcache_clean_area | |
486 | .word cpu_arm925_switch_mm | |
487 | .word cpu_arm925_set_pte | |
488 | .size arm925_processor_functions, . - arm925_processor_functions | |
489 | ||
490 | .section ".rodata" | |
491 | ||
492 | .type cpu_arch_name, #object | |
493 | cpu_arch_name: | |
494 | .asciz "armv4t" | |
495 | .size cpu_arch_name, . - cpu_arch_name | |
496 | ||
497 | .type cpu_elf_name, #object | |
498 | cpu_elf_name: | |
499 | .asciz "v4" | |
500 | .size cpu_elf_name, . - cpu_elf_name | |
501 | ||
502 | .type cpu_arm925_name, #object | |
503 | cpu_arm925_name: | |
504 | .ascii "ARM925T" | |
505 | #ifndef CONFIG_CPU_ICACHE_DISABLE | |
506 | .ascii "i" | |
507 | #endif | |
508 | #ifndef CONFIG_CPU_DCACHE_DISABLE | |
509 | .ascii "d" | |
510 | #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH | |
511 | .ascii "(wt)" | |
512 | #else | |
513 | .ascii "(wb)" | |
514 | #endif | |
515 | #ifdef CONFIG_CPU_CACHE_ROUND_ROBIN | |
516 | .ascii "RR" | |
517 | #endif | |
518 | #endif | |
519 | .ascii "\0" | |
520 | .size cpu_arm925_name, . - cpu_arm925_name | |
521 | ||
522 | .align | |
523 | ||
02b7dd12 | 524 | .section ".proc.info.init", #alloc, #execinstr |
1da177e4 LT |
525 | |
526 | .type __arm925_proc_info,#object | |
527 | __arm925_proc_info: | |
528 | .long 0x54029250 | |
529 | .long 0xfffffff0 | |
530 | .long PMD_TYPE_SECT | \ | |
531 | PMD_BIT4 | \ | |
532 | PMD_SECT_AP_WRITE | \ | |
533 | PMD_SECT_AP_READ | |
534 | b __arm925_setup | |
535 | .long cpu_arch_name | |
536 | .long cpu_elf_name | |
537 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | |
538 | .long cpu_arm925_name | |
539 | .long arm925_processor_functions | |
540 | .long v4wbi_tlb_fns | |
541 | .long v4wb_user_fns | |
542 | .long arm925_cache_fns | |
543 | .size __arm925_proc_info, . - __arm925_proc_info | |
544 | ||
545 | .type __arm915_proc_info,#object | |
546 | __arm915_proc_info: | |
547 | .long 0x54029150 | |
548 | .long 0xfffffff0 | |
549 | .long PMD_TYPE_SECT | \ | |
550 | PMD_BIT4 | \ | |
551 | PMD_SECT_AP_WRITE | \ | |
552 | PMD_SECT_AP_READ | |
553 | b __arm925_setup | |
554 | .long cpu_arch_name | |
555 | .long cpu_elf_name | |
556 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | |
557 | .long cpu_arm925_name | |
558 | .long arm925_processor_functions | |
559 | .long v4wbi_tlb_fns | |
560 | .long v4wb_user_fns | |
561 | .long arm925_cache_fns | |
562 | .size __arm925_proc_info, . - __arm925_proc_info |