[mirror_ubuntu-zesty-kernel.git] / arch / arm / mm / proc-arm946.S

/*
 *  linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
 *
 *  Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
 *
 *  (Many of cache codes are from proc-arm926.S)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
 * comprising 256 lines of 32 bytes (8 words).
 */
#define CACHE_DSIZE	(CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */
#define CACHE_DLINESIZE	32			/* fixed */
#define CACHE_DSEGMENTS	4			/* fixed */
#define CACHE_DENTRIES	(CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE)
#define CACHE_DLIMIT	(CACHE_DSIZE * 4)	/* benchmark needed */

	.text
/*
 * cpu_arm946_proc_init()
 * cpu_arm946_switch_mm()
 *
 * These are not required.
 */
ENTRY(cpu_arm946_proc_init)
ENTRY(cpu_arm946_switch_mm)
	mov	pc, lr

/*
 * cpu_arm946_proc_fin()
 */
ENTRY(cpu_arm946_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x00001000		@ i-cache
	bic	r0, r0, #0x00000004		@ d-cache
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 * cpu_arm946_reset(loc)
 * Params  : r0 = address to jump to
 * Notes   : This sets up everything for a reset
 */
ENTRY(cpu_arm946_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c5, 0		@ flush I cache
	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x00000005		@ .............c.p
	bic	ip, ip, #0x00001000		@ i-cache
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm946_do_idle()
 */
	.align	5
ENTRY(cpu_arm946_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mov	pc, lr

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(arm946_flush_icache_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mov	pc, lr
ENDPROC(arm946_flush_icache_all)

/*
 *	flush_user_cache_all()
 */
ENTRY(arm946_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm946_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ flush D cache
#else
	mov	r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean/flush D index
	subs	r3, r3, #1 << 4
	bcs	2b				@ entries n to 0
	subs	r1, r1, #1 << 29
	bcs	1b				@ segments 3 to 0
#endif
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ flush I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 * (same as arm926)
 */
ENTRY(arm946_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

1:	tst	r2, #VM_EXEC
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#else
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#endif
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm946_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 * (same as arm926)
 */
ENTRY(arm946_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 * (same as arm926)
 */
ENTRY(arm946_flush_kern_dcache_area)
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 * (same as arm926)
 */
arm946_dma_inv_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	tst	r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
#endif
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as arm926)
 */
arm946_dma_clean_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as arm926)
 */
ENTRY(arm946_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
#else
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm946_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm946_dma_clean_range
	bcs	arm946_dma_inv_range
	b	arm946_dma_flush_range
ENDPROC(arm946_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm946_dma_unmap_area)
	mov	pc, lr
ENDPROC(arm946_dma_unmap_area)

	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
	define_cache_functions arm946

ENTRY(cpu_arm946_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

	__CPUINIT

	.type	__arm946_setup, #function
__arm946_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c6, 0		@ invalidate D cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB

	mcr	p15, 0, r0, c6, c3, 0		@ disable memory region 3~7
	mcr	p15, 0, r0, c6, c4, 0
	mcr	p15, 0, r0, c6, c5, 0
	mcr	p15, 0, r0, c6, c6, 0
	mcr	p15, 0, r0, c6, c7, 0

	mov	r0, #0x0000003F			@ base = 0, size = 4GB
	mcr	p15, 0, r0, c6,	c0, 0		@ set region 0, default

	ldr	r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
	ldr	r1, =(CONFIG_DRAM_SIZE >> 12)	@ size of RAM (must be >= 4KB)
	mov	r2, #10				@ 11 is the minimum (4KB)
1:	add	r2, r2, #1			@ area size *= 2
	mov	r1, r1, lsr #1
	bne	1b				@ count not zero r-shift
	orr	r0, r0, r2, lsl #1		@ the region register value
	orr	r0, r0, #1			@ set enable bit
	mcr	p15, 0, r0, c6,	c1, 0		@ set region 1, RAM

	ldr	r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
	ldr	r1, =(CONFIG_FLASH_SIZE >> 12)	@ size of FLASH (must be >= 4KB)
	mov	r2, #10				@ 11 is the minimum (4KB)
1:	add	r2, r2, #1			@ area size *= 2
	mov	r1, r1, lsr #1
	bne	1b				@ count not zero r-shift
	orr	r0, r0, r2, lsl #1		@ the region register value
	orr	r0, r0, #1			@ set enable bit
	mcr	p15, 0, r0, c6,	c2, 0		@ set region 2, ROM/FLASH

	mov	r0, #0x06
	mcr	p15, 0, r0, c2, c0, 0		@ region 1,2 d-cacheable
	mcr	p15, 0, r0, c2, c0, 1		@ region 1,2 i-cacheable
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #0x00			@ disable whole write buffer
#else
	mov	r0, #0x02			@ region 1 write bufferred
#endif
	mcr	p15, 0, r0, c3, c0, 0

/*
 *  Access Permission Settings for future permission control by PU.
 *
 *				priv.	user
 * 	region 0 (whole)	rw	--	: b0001
 * 	region 1 (RAM)		rw	rw	: b0011
 * 	region 2 (FLASH)	rw	r-	: b0010
 *	region 3~7 (none)	--	--	: b0000
 */
	mov	r0, #0x00000031
	orr	r0, r0, #0x00000200
	mcr	p15, 0, r0, c5, c0, 2		@ set data access permission
	mcr	p15, 0, r0, c5, c0, 3		@ set inst. access permission

	mrc	p15, 0, r0, c1, c0		@ get control register
	orr	r0, r0, #0x00001000		@ I-cache
	orr	r0, r0, #0x00000005		@ MPU/D-cache
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x00004000		@ .1.. .... .... ....
#endif
	mov	pc, lr

	.size	__arm946_setup, . - __arm946_setup

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm946, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1

	.section ".rodata"

	string	cpu_arch_name, "armv5te"
	string	cpu_elf_name, "v5t"
	string	cpu_arm946_name, "ARM946E-S"

	.align

	.section ".proc.info.init", #alloc, #execinstr
	.type	__arm946_proc_info,#object
__arm946_proc_info:
	.long	0x41009460
	.long	0xff00fff0
	.long	0
	.long	0
	b	__arm946_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm946_name
	.long	arm946_processor_functions
	.long	0
	.long	0
	.long	arm946_cache_fns
	.size	__arm946_proc_info, . - __arm946_proc_info
Commit	Line	Data
f37f46eb HC	1	/*
	2	* linux/arch/arm/mm/arm946.S: utility functions for ARM946E-S
	3	*
	4	* Copyright (C) 2004-2006 Hyok S. Choi (hyok.choi@samsung.com)
	5	*
	6	* (Many of cache codes are from proc-arm926.S)
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2 as
	10	* published by the Free Software Foundation.
	11	*
	12	*/
	13	#include <linux/linkage.h>
	14	#include <linux/init.h>
	15	#include <asm/assembler.h>
5ec9407d	16	#include <asm/hwcap.h>
f37f46eb HC	17	#include <asm/pgtable-hwdef.h>
f37f46eb HC	18	#include <asm/pgtable.h>
f37f46eb	19	#include <asm/ptrace.h>
8a5544c8	20	#include "proc-macros.S"
f37f46eb HC	21
	22	/*
	23	* ARM946E-S is synthesizable to have 0KB to 1MB sized D-Cache,
	24	* comprising 256 lines of 32 bytes (8 words).
	25	*/
	26	#define CACHE_DSIZE (CONFIG_CPU_DCACHE_SIZE) /* typically 8KB. */
	27	#define CACHE_DLINESIZE 32 /* fixed */
	28	#define CACHE_DSEGMENTS 4 /* fixed */
	29	#define CACHE_DENTRIES (CACHE_DSIZE / CACHE_DSEGMENTS / CACHE_DLINESIZE)
	30	#define CACHE_DLIMIT (CACHE_DSIZE * 4) /* benchmark needed */
	31
	32	.text
	33	/*
	34	* cpu_arm946_proc_init()
	35	* cpu_arm946_switch_mm()
	36	*
	37	* These are not required.
	38	*/
	39	ENTRY(cpu_arm946_proc_init)
	40	ENTRY(cpu_arm946_switch_mm)
	41	mov pc, lr
	42
	43	/*
	44	* cpu_arm946_proc_fin()
	45	*/
	46	ENTRY(cpu_arm946_proc_fin)
f37f46eb HC	47	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	48	bic r0, r0, #0x00001000 @ i-cache
	49	bic r0, r0, #0x00000004 @ d-cache
	50	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	51	mov pc, lr
f37f46eb HC	52
	53	/*
	54	* cpu_arm946_reset(loc)
	55	* Params : r0 = address to jump to
	56	* Notes : This sets up everything for a reset
	57	*/
	58	ENTRY(cpu_arm946_reset)
	59	mov ip, #0
	60	mcr p15, 0, ip, c7, c5, 0 @ flush I cache
	61	mcr p15, 0, ip, c7, c6, 0 @ flush D cache
	62	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	63	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	64	bic ip, ip, #0x00000005 @ .............c.p
	65	bic ip, ip, #0x00001000 @ i-cache
	66	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	67	mov pc, r0
	68
	69	/*
	70	* cpu_arm946_do_idle()
	71	*/
	72	.align 5
	73	ENTRY(cpu_arm946_do_idle)
	74	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	75	mov pc, lr
	76
c8c90860 MW	77	/*
	78	* flush_icache_all()
	79	*
	80	* Unconditionally clean and invalidate the entire icache.
	81	*/
	82	ENTRY(arm946_flush_icache_all)
	83	mov r0, #0
	84	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	85	mov pc, lr
	86	ENDPROC(arm946_flush_icache_all)
	87
f37f46eb HC	88	/*
	89	* flush_user_cache_all()
	90	*/
	91	ENTRY(arm946_flush_user_cache_all)
	92	/* FALLTHROUGH */
	93
	94	/*
	95	* flush_kern_cache_all()
	96	*
	97	* Clean and invalidate the entire cache.
	98	*/
	99	ENTRY(arm946_flush_kern_cache_all)
	100	mov r2, #VM_EXEC
	101	mov ip, #0
	102	__flush_whole_cache:
	103	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	104	mcr p15, 0, ip, c7, c6, 0 @ flush D cache
	105	#else
	106	mov r1, #(CACHE_DSEGMENTS - 1) << 29 @ 4 segments
	107	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 4 @ n entries
	108	2: mcr p15, 0, r3, c7, c14, 2 @ clean/flush D index
	109	subs r3, r3, #1 << 4
	110	bcs 2b @ entries n to 0
	111	subs r1, r1, #1 << 29
	112	bcs 1b @ segments 3 to 0
	113	#endif
	114	tst r2, #VM_EXEC
	115	mcrne p15, 0, ip, c7, c5, 0 @ flush I cache
	116	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	117	mov pc, lr
	118
	119	/*
	120	* flush_user_cache_range(start, end, flags)
	121	*
	122	* Clean and invalidate a range of cache entries in the
	123	* specified address range.
	124	*
	125	* - start - start address (inclusive)
	126	* - end - end address (exclusive)
	127	* - flags - vm_flags describing address space
	128	* (same as arm926)
	129	*/
	130	ENTRY(arm946_flush_user_cache_range)
	131	mov ip, #0
	132	sub r3, r1, r0 @ calculate total size
	133	cmp r3, #CACHE_DLIMIT
	134	bhs __flush_whole_cache
	135
	136	1: tst r2, #VM_EXEC
	137	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	138	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	139	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	140	add r0, r0, #CACHE_DLINESIZE
	141	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	142	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	143	add r0, r0, #CACHE_DLINESIZE
	144	#else
	145	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	146	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	147	add r0, r0, #CACHE_DLINESIZE
	148	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	149	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	150	add r0, r0, #CACHE_DLINESIZE
	151	#endif
152	cmp r0, r1
153	blo 1b
154	tst r2, #VM_EXEC
155	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
156	mov pc, lr
157
158	/*
159	* coherent_kern_range(start, end)
160	*
161	* Ensure coherency between the Icache and the Dcache in the
162	* region described by start, end. If you have non-snooping
163	* Harvard caches, you need to implement this function.
164	*
165	* - start - virtual start address
166	* - end - virtual end address
167	*/
168	ENTRY(arm946_coherent_kern_range)
169	/* FALLTHROUGH */
170
171	/*
172	* coherent_user_range(start, end)
173	*
174	* Ensure coherency between the Icache and the Dcache in the
175	* region described by start, end. If you have non-snooping
176	* Harvard caches, you need to implement this function.
177	*
178	* - start - virtual start address
179	* - end - virtual end address
180	* (same as arm926)
181	*/
182	ENTRY(arm946_coherent_user_range)
183	bic r0, r0, #CACHE_DLINESIZE - 1
184	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
185	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
186	add r0, r0, #CACHE_DLINESIZE
187	cmp r0, r1
188	blo 1b
189	mcr p15, 0, r0, c7, c10, 4 @ drain WB
190	mov pc, lr
191
192	/*
2c9b9c84	193	* flush_kern_dcache_area(void *addr, size_t size)
f37f46eb HC	194	*
	195	* Ensure no D cache aliasing occurs, either with itself or
	196	* the I cache
	197	*
2c9b9c84 RK	198	* - addr - kernel address
2c9b9c84 RK	199	* - size - region size
f37f46eb HC	200	* (same as arm926)
f37f46eb HC	201	*/
2c9b9c84 RK	202	ENTRY(arm946_flush_kern_dcache_area)
2c9b9c84 RK	203	add r1, r0, r1
f37f46eb HC	204	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	205	add r0, r0, #CACHE_DLINESIZE
	206	cmp r0, r1
	207	blo 1b
	208	mov r0, #0
	209	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	210	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	211	mov pc, lr
	212
	213	/*
	214	* dma_inv_range(start, end)
	215	*
	216	* Invalidate (discard) the specified virtual address range.
	217	* May not write back any entries. If 'start' or 'end'
	218	* are not cache line aligned, those lines must be written
	219	* back.
	220	*
	221	* - start - virtual start address
	222	* - end - virtual end address
	223	* (same as arm926)
	224	*/
702b94bf	225	arm946_dma_inv_range:
f37f46eb HC	226	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	227	tst r0, #CACHE_DLINESIZE - 1
	228	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	229	tst r1, #CACHE_DLINESIZE - 1
	230	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	231	#endif
	232	bic r0, r0, #CACHE_DLINESIZE - 1
	233	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	234	add r0, r0, #CACHE_DLINESIZE
	235	cmp r0, r1
	236	blo 1b
	237	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	238	mov pc, lr
	239
	240	/*
	241	* dma_clean_range(start, end)
	242	*
	243	* Clean the specified virtual address range.
	244	*
	245	* - start - virtual start address
	246	* - end - virtual end address
	247	*
	248	* (same as arm926)
	249	*/
702b94bf	250	arm946_dma_clean_range:
f37f46eb HC	251	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	252	bic r0, r0, #CACHE_DLINESIZE - 1
	253	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	254	add r0, r0, #CACHE_DLINESIZE
	255	cmp r0, r1
	256	blo 1b
	257	#endif
	258	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	259	mov pc, lr
	260
	261	/*
	262	* dma_flush_range(start, end)
	263	*
	264	* Clean and invalidate the specified virtual address range.
	265	*
	266	* - start - virtual start address
	267	* - end - virtual end address
	268	*
	269	* (same as arm926)
	270	*/
	271	ENTRY(arm946_dma_flush_range)
	272	bic r0, r0, #CACHE_DLINESIZE - 1
	273	1:
	274	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	275	mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	276	#else
b3a8b751	277	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
f37f46eb HC	278	#endif
	279	add r0, r0, #CACHE_DLINESIZE
	280	cmp r0, r1
	281	blo 1b
	282	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	283	mov pc, lr
	284
a9c9147e RK	285	/*
	286	* dma_map_area(start, size, dir)
	287	* - start - kernel virtual start address
	288	* - size - size of region
	289	* - dir - DMA direction
	290	*/
	291	ENTRY(arm946_dma_map_area)
	292	add r1, r1, r0
	293	cmp r2, #DMA_TO_DEVICE
	294	beq arm946_dma_clean_range
	295	bcs arm946_dma_inv_range
	296	b arm946_dma_flush_range
	297	ENDPROC(arm946_dma_map_area)
	298
	299	/*
	300	* dma_unmap_area(start, size, dir)
	301	* - start - kernel virtual start address
	302	* - size - size of region
	303	* - dir - DMA direction
	304	*/
	305	ENTRY(arm946_dma_unmap_area)
	306	mov pc, lr
	307	ENDPROC(arm946_dma_unmap_area)
	308
b1b9892b DM	309	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
b1b9892b DM	310	define_cache_functions arm946
f37f46eb HC	311
	312	ENTRY(cpu_arm946_dcache_clean_area)
	313	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	314	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	315	add r0, r0, #CACHE_DLINESIZE
	316	subs r1, r1, #CACHE_DLINESIZE
	317	bhi 1b
	318	#endif
	319	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	320	mov pc, lr
	321
5085f3ff	322	__CPUINIT
f37f46eb HC	323
	324	.type __arm946_setup, #function
	325	__arm946_setup:
	326	mov r0, #0
	327	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	328	mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
	329	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	330
	331	mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
	332	mcr p15, 0, r0, c6, c4, 0
	333	mcr p15, 0, r0, c6, c5, 0
	334	mcr p15, 0, r0, c6, c6, 0
	335	mcr p15, 0, r0, c6, c7, 0
	336
	337	mov r0, #0x0000003F @ base = 0, size = 4GB
	338	mcr p15, 0, r0, c6, c0, 0 @ set region 0, default
	339
	340	ldr r0, =(CONFIG_DRAM_BASE & 0xFFFFF000) @ base[31:12] of RAM
	341	ldr r1, =(CONFIG_DRAM_SIZE >> 12) @ size of RAM (must be >= 4KB)
	342	mov r2, #10 @ 11 is the minimum (4KB)
	343	1: add r2, r2, #1 @ area size *= 2
	344	mov r1, r1, lsr #1
	345	bne 1b @ count not zero r-shift
	346	orr r0, r0, r2, lsl #1 @ the region register value
	347	orr r0, r0, #1 @ set enable bit
	348	mcr p15, 0, r0, c6, c1, 0 @ set region 1, RAM
	349
	350	ldr r0, =(CONFIG_FLASH_MEM_BASE & 0xFFFFF000) @ base[31:12] of FLASH
	351	ldr r1, =(CONFIG_FLASH_SIZE >> 12) @ size of FLASH (must be >= 4KB)
	352	mov r2, #10 @ 11 is the minimum (4KB)
	353	1: add r2, r2, #1 @ area size *= 2
	354	mov r1, r1, lsr #1
	355	bne 1b @ count not zero r-shift
	356	orr r0, r0, r2, lsl #1 @ the region register value
	357	orr r0, r0, #1 @ set enable bit
	358	mcr p15, 0, r0, c6, c2, 0 @ set region 2, ROM/FLASH
	359
	360	mov r0, #0x06
	361	mcr p15, 0, r0, c2, c0, 0 @ region 1,2 d-cacheable
	362	mcr p15, 0, r0, c2, c0, 1 @ region 1,2 i-cacheable
	363	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	364	mov r0, #0x00 @ disable whole write buffer
	365	#else
	366	mov r0, #0x02 @ region 1 write bufferred
	367	#endif
	368	mcr p15, 0, r0, c3, c0, 0
	369
	370	/*
	371	* Access Permission Settings for future permission control by PU.
	372	*
	373	* priv. user
	374	* region 0 (whole) rw -- : b0001
	375	* region 1 (RAM) rw rw : b0011
	376	* region 2 (FLASH) rw r- : b0010
	377	* region 3~7 (none) -- -- : b0000
	378	*/
	379	mov r0, #0x00000031
	380	orr r0, r0, #0x00000200
	381	mcr p15, 0, r0, c5, c0, 2 @ set data access permission
	382	mcr p15, 0, r0, c5, c0, 3 @ set inst. access permission
	383
	384	mrc p15, 0, r0, c1, c0 @ get control register
	385	orr r0, r0, #0x00001000 @ I-cache
	386	orr r0, r0, #0x00000005 @ MPU/D-cache
387	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
388	orr r0, r0, #0x00004000 @ .1.. .... .... ....
389	#endif
390	mov pc, lr
391
392	.size __arm946_setup, . - __arm946_setup
393
394	__INITDATA
395
b1b9892b DM	396	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
b1b9892b DM	397	define_processor_functions arm946, dabort=nommu_early_abort, pabort=legacy_pabort, nommu=1
f37f46eb HC	398
	399	.section ".rodata"
	400
b1b9892b DM	401	string cpu_arch_name, "armv5te"
	402	string cpu_elf_name, "v5t"
	403	string cpu_arm946_name, "ARM946E-S"
f37f46eb HC	404
	405	.align
	406
	407	.section ".proc.info.init", #alloc, #execinstr
	408	.type __arm946_proc_info,#object
	409	__arm946_proc_info:
	410	.long 0x41009460
	411	.long 0xff00fff0
	412	.long 0
7760d546	413	.long 0
f37f46eb HC	414	b __arm946_setup
	415	.long cpu_arch_name
	416	.long cpu_elf_name
	417	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	418	.long cpu_arm946_name
	419	.long arm946_processor_functions
	420	.long 0
	421	.long 0
7760d546	422	.long arm946_cache_fns
f37f46eb HC	423	.size __arm946_proc_info, . - __arm946_proc_info
f37f46eb HC	424