[mirror_ubuntu-bionic-kernel.git] / arch / arm / mm / proc-feroceon.S

/*
 *  linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
 *
 *  Heavily based on proc-arm926.S
 *  Maintainer: Assaf Hoffman <hoffman@marvell.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define CACHE_DLIMIT	16384

/*
 * the cache line size of the I and D cache
 */
#define CACHE_DLINESIZE	32

	.bss
	.align 3
__cache_params_loc:
	.space	8

	.text
__cache_params:
	.word	__cache_params_loc

/*
 * cpu_feroceon_proc_init()
 */
ENTRY(cpu_feroceon_proc_init)
	mrc	p15, 0, r0, c0, c0, 1		@ read cache type register
	ldr	r1, __cache_params
	mov	r2, #(16 << 5)
	tst	r0, #(1 << 16)			@ get way
	mov	r0, r0, lsr #18			@ get cache size order
	movne	r3, #((4 - 1) << 30)		@ 4-way
	and	r0, r0, #0xf
	moveq	r3, #0				@ 1-way
	mov	r2, r2, lsl r0			@ actual cache size
	movne	r2, r2, lsr #2			@ turned into # of sets
	sub	r2, r2, #(1 << 5)
	stmia	r1, {r2, r3}
	mov	pc, lr

/*
 * cpu_feroceon_proc_fin()
 */
ENTRY(cpu_feroceon_proc_fin)
#if defined(CONFIG_CACHE_FEROCEON_L2) && \
	!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
	mov	r0, #0
	mcr	p15, 1, r0, c15, c9, 0		@ clean L2
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif

	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 * cpu_feroceon_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_feroceon_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_feroceon_do_idle()
 *
 * Called with IRQs disabled
 */
	.align	5
ENTRY(cpu_feroceon_do_idle)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mov	pc, lr

/*
 *	flush_user_cache_all()
 *
 *	Clean and invalidate all cache entries in a particular
 *	address space.
 */
	.align	5
ENTRY(feroceon_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(feroceon_flush_kern_cache_all)
	mov	r2, #VM_EXEC

__flush_whole_cache:
	ldr	r1, __cache_params
	ldmia	r1, {r1, r3}
1:	orr	ip, r1, r3
2:	mcr	p15, 0, ip, c7, c14, 2		@ clean + invalidate D set/way
	subs	ip, ip, #(1 << 30)		@ next way
	bcs	2b
	subs	r1, r1, #(1 << 5)		@ next set
	bcs	1b

	tst	r2, #VM_EXEC
	mov	ip, #0
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 */
	.align	5
ENTRY(feroceon_flush_user_cache_range)
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bgt	__flush_whole_cache
1:	tst	r2, #VM_EXEC
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mov	ip, #0
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
	.align	5
ENTRY(feroceon_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(feroceon_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
	.align	5
ENTRY(feroceon_flush_kern_dcache_area)
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

	.align	5
ENTRY(feroceon_range_flush_kern_dcache_area)
	mrs	r2, cpsr
	add	r1, r0, #PAGE_SZ - CACHE_DLINESIZE	@ top addr is inclusive
	orr	r3, r2, #PSR_I_BIT
	msr	cpsr_c, r3			@ disable interrupts
	mcr	p15, 5, r0, c15, c15, 0		@ D clean/inv range start
	mcr	p15, 5, r1, c15, c15, 1		@ D clean/inv range top
	msr	cpsr_c, r2			@ restore interrupts
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
	.align	5
feroceon_dma_inv_range:
	tst	r0, #CACHE_DLINESIZE - 1
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

	.align	5
feroceon_range_dma_inv_range:
	mrs	r2, cpsr
	tst	r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
	cmp	r1, r0
	subne	r1, r1, #1			@ top address is inclusive
	orr	r3, r2, #PSR_I_BIT
	msr	cpsr_c, r3			@ disable interrupts
	mcr	p15, 5, r0, c15, c14, 0		@ D inv range start
	mcr	p15, 5, r1, c15, c14, 1		@ D inv range top
	msr	cpsr_c, r2			@ restore interrupts
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
	.align	5
feroceon_dma_clean_range:
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

	.align	5
feroceon_range_dma_clean_range:
	mrs	r2, cpsr
	cmp	r1, r0
	subne	r1, r1, #1			@ top address is inclusive
	orr	r3, r2, #PSR_I_BIT
	msr	cpsr_c, r3			@ disable interrupts
	mcr	p15, 5, r0, c15, c13, 0		@ D clean range start
	mcr	p15, 5, r1, c15, c13, 1		@ D clean range top
	msr	cpsr_c, r2			@ restore interrupts
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
	.align	5
ENTRY(feroceon_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

	.align	5
ENTRY(feroceon_range_dma_flush_range)
	mrs	r2, cpsr
	cmp	r1, r0
	subne	r1, r1, #1			@ top address is inclusive
	orr	r3, r2, #PSR_I_BIT
	msr	cpsr_c, r3			@ disable interrupts
	mcr	p15, 5, r0, c15, c15, 0		@ D clean/inv range start
	mcr	p15, 5, r1, c15, c15, 1		@ D clean/inv range top
	msr	cpsr_c, r2			@ restore interrupts
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(feroceon_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	feroceon_dma_clean_range
	bcs	feroceon_dma_inv_range
	b	feroceon_dma_flush_range
ENDPROC(feroceon_dma_map_area)

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(feroceon_range_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	feroceon_range_dma_clean_range
	bcs	feroceon_range_dma_inv_range
	b	feroceon_range_dma_flush_range
ENDPROC(feroceon_range_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(feroceon_dma_unmap_area)
	mov	pc, lr
ENDPROC(feroceon_dma_unmap_area)

ENTRY(feroceon_cache_fns)
	.long	feroceon_flush_kern_cache_all
	.long	feroceon_flush_user_cache_all
	.long	feroceon_flush_user_cache_range
	.long	feroceon_coherent_kern_range
	.long	feroceon_coherent_user_range
	.long	feroceon_flush_kern_dcache_area
	.long	feroceon_dma_map_area
	.long	feroceon_dma_unmap_area
	.long	feroceon_dma_flush_range

ENTRY(feroceon_range_cache_fns)
	.long	feroceon_flush_kern_cache_all
	.long	feroceon_flush_user_cache_all
	.long	feroceon_flush_user_cache_range
	.long	feroceon_coherent_kern_range
	.long	feroceon_coherent_user_range
	.long	feroceon_range_flush_kern_dcache_area
	.long	feroceon_range_dma_map_area
	.long	feroceon_dma_unmap_area
	.long	feroceon_range_dma_flush_range

	.align	5
ENTRY(cpu_feroceon_dcache_clean_area)
#if defined(CONFIG_CACHE_FEROCEON_L2) && \
	!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
	mov	r2, r0
	mov	r3, r1
#endif
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#if defined(CONFIG_CACHE_FEROCEON_L2) && \
	!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
1:	mcr	p15, 1, r2, c15, c9, 1		@ clean L2 entry
	add	r2, r2, #CACHE_DLINESIZE
	subs	r3, r3, #CACHE_DLINESIZE
	bhi	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_feroceon_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_feroceon_switch_mm)
#ifdef CONFIG_MMU
	/*
	 * Note: we wish to call __flush_whole_cache but we need to preserve
	 * lr to do so.  The only way without touching main memory is to
	 * use r2 which is normally used to test the VM_EXEC flag, and
	 * compensate locally for the skipped ops if it is not set.
	 */
	mov	r2, lr				@ abuse r2 to preserve lr
	bl	__flush_whole_cache
	@ if r2 contains the VM_EXEC bit then the next 2 ops are done already
	tst	r2, #VM_EXEC
	mcreq	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcreq	p15, 0, ip, c7, c10, 4		@ drain WB

	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
	mov	pc, r2
#else
	mov	pc, lr
#endif

/*
 * cpu_feroceon_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_feroceon_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext wc_disable=0
	mov	r0, r0
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#if defined(CONFIG_CACHE_FEROCEON_L2) && \
	!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
	mcr	p15, 1, r0, c15, c9, 1		@ clean L2 entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif
	mov	pc, lr

	__INIT

	.type	__feroceon_setup, #function
__feroceon_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif

	adr	r5, feroceon_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
	mov	pc, lr
	.size	__feroceon_setup, . - __feroceon_setup

	/*
	 *      B
	 *  R   P
	 * .RVI UFRS BLDP WCAM
	 * .011 .001 ..11 0101
	 *
	 */
	.type	feroceon_crval, #object
feroceon_crval:
	crval	clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */
	.type	feroceon_processor_functions, #object
feroceon_processor_functions:
	.word	v5t_early_abort
	.word	legacy_pabort
	.word	cpu_feroceon_proc_init
	.word	cpu_feroceon_proc_fin
	.word	cpu_feroceon_reset
	.word	cpu_feroceon_do_idle
	.word	cpu_feroceon_dcache_clean_area
	.word	cpu_feroceon_switch_mm
	.word	cpu_feroceon_set_pte_ext
	.size	feroceon_processor_functions, . - feroceon_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv5te"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v5"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_feroceon_name, #object
cpu_feroceon_name:
	.asciz	"Feroceon"
	.size	cpu_feroceon_name, . - cpu_feroceon_name

	.type	cpu_88fr531_name, #object
cpu_88fr531_name:
	.asciz	"Feroceon 88FR531-vd"
	.size	cpu_88fr531_name, . - cpu_88fr531_name

	.type	cpu_88fr571_name, #object
cpu_88fr571_name:
	.asciz	"Feroceon 88FR571-vd"
	.size	cpu_88fr571_name, . - cpu_88fr571_name

	.type	cpu_88fr131_name, #object
cpu_88fr131_name:
	.asciz	"Feroceon 88FR131"
	.size	cpu_88fr131_name, . - cpu_88fr131_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

#ifdef CONFIG_CPU_FEROCEON_OLD_ID
	.type	__feroceon_old_id_proc_info,#object
__feroceon_old_id_proc_info:
	.long	0x41009260
	.long	0xff00fff0
	.long	PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long	PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__feroceon_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
	.long	cpu_feroceon_name
	.long	feroceon_processor_functions
	.long	v4wbi_tlb_fns
	.long	feroceon_user_fns
	.long	feroceon_cache_fns
	.size	__feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
#endif

	.type	__88fr531_proc_info,#object
__88fr531_proc_info:
	.long	0x56055310
	.long	0xfffffff0
	.long	PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long	PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__feroceon_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
	.long	cpu_88fr531_name
	.long	feroceon_processor_functions
	.long	v4wbi_tlb_fns
	.long	feroceon_user_fns
	.long	feroceon_cache_fns
	.size	__88fr531_proc_info, . - __88fr531_proc_info

	.type	__88fr571_proc_info,#object
__88fr571_proc_info:
	.long	0x56155710
	.long	0xfffffff0
	.long	PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long	PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__feroceon_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
	.long	cpu_88fr571_name
	.long	feroceon_processor_functions
	.long	v4wbi_tlb_fns
	.long	feroceon_user_fns
	.long	feroceon_range_cache_fns
	.size	__88fr571_proc_info, . - __88fr571_proc_info

	.type	__88fr131_proc_info,#object
__88fr131_proc_info:
	.long	0x56251310
	.long	0xfffffff0
	.long	PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long	PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__feroceon_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
	.long	cpu_88fr131_name
	.long	feroceon_processor_functions
	.long	v4wbi_tlb_fns
	.long	feroceon_user_fns
	.long	feroceon_range_cache_fns
	.size	__88fr131_proc_info, . - __88fr131_proc_info
Commit	Line	Data
e50d6409 AH	1	/*
	2	* linux/arch/arm/mm/proc-feroceon.S: MMU functions for Feroceon
	3	*
	4	* Heavily based on proc-arm926.S
	5	* Maintainer: Assaf Hoffman <hoffman@marvell.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
	21
	22	#include <linux/linkage.h>
	23	#include <linux/init.h>
	24	#include <asm/assembler.h>
5ec9407d	25	#include <asm/hwcap.h>
e50d6409 AH	26	#include <asm/pgtable-hwdef.h>
	27	#include <asm/pgtable.h>
	28	#include <asm/page.h>
	29	#include <asm/ptrace.h>
	30	#include "proc-macros.S"
	31
	32	/*
	33	* This is the maximum size of an area which will be invalidated
	34	* using the single invalidate entry instructions. Anything larger
	35	* than this, and we go for the whole cache.
	36	*
	37	* This value should be chosen such that we choose the cheapest
	38	* alternative.
	39	*/
	40	#define CACHE_DLIMIT 16384
	41
	42	/*
	43	* the cache line size of the I and D cache
	44	*/
	45	#define CACHE_DLINESIZE 32
	46
6c386e58 NP	47	.bss
	48	.align 3
	49	__cache_params_loc:
	50	.space 8
	51
e50d6409	52	.text
6c386e58 NP	53	__cache_params:
	54	.word __cache_params_loc
	55
e50d6409 AH	56	/*
	57	* cpu_feroceon_proc_init()
	58	*/
	59	ENTRY(cpu_feroceon_proc_init)
6c386e58 NP	60	mrc p15, 0, r0, c0, c0, 1 @ read cache type register
	61	ldr r1, __cache_params
	62	mov r2, #(16 << 5)
	63	tst r0, #(1 << 16) @ get way
	64	mov r0, r0, lsr #18 @ get cache size order
	65	movne r3, #((4 - 1) << 30) @ 4-way
	66	and r0, r0, #0xf
	67	moveq r3, #0 @ 1-way
	68	mov r2, r2, lsl r0 @ actual cache size
	69	movne r2, r2, lsr #2 @ turned into # of sets
	70	sub r2, r2, #(1 << 5)
	71	stmia r1, {r2, r3}
e50d6409 AH	72	mov pc, lr
	73
	74	/*
	75	* cpu_feroceon_proc_fin()
	76	*/
	77	ENTRY(cpu_feroceon_proc_fin)
4360bb41 RS	78	#if defined(CONFIG_CACHE_FEROCEON_L2) && \
4360bb41 RS	79	!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
99c6dc11 LB	80	mov r0, #0
	81	mcr p15, 1, r0, c15, c9, 0 @ clean L2
	82	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	83	#endif
	84
e50d6409 AH	85	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	86	bic r0, r0, #0x1000 @ ...i............
	87	bic r0, r0, #0x000e @ ............wca.
	88	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	89	mov pc, lr
e50d6409 AH	90
	91	/*
	92	* cpu_feroceon_reset(loc)
	93	*
	94	* Perform a soft reset of the system. Put the CPU into the
	95	* same state as it would be if it had been reset, and branch
	96	* to what would be the reset vector.
	97	*
	98	* loc: location to jump to for soft reset
	99	*/
	100	.align 5
	101	ENTRY(cpu_feroceon_reset)
	102	mov ip, #0
	103	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	104	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	105	#ifdef CONFIG_MMU
	106	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
	107	#endif
	108	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	109	bic ip, ip, #0x000f @ ............wcam
	110	bic ip, ip, #0x1100 @ ...i...s........
	111	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	112	mov pc, r0
	113
	114	/*
	115	* cpu_feroceon_do_idle()
	116	*
	117	* Called with IRQs disabled
	118	*/
6b29e681	119	.align 5
e50d6409 AH	120	ENTRY(cpu_feroceon_do_idle)
	121	mov r0, #0
	122	mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
	123	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	124	mov pc, lr
	125
	126	/*
	127	* flush_user_cache_all()
	128	*
	129	* Clean and invalidate all cache entries in a particular
	130	* address space.
	131	*/
6b29e681	132	.align 5
e50d6409 AH	133	ENTRY(feroceon_flush_user_cache_all)
	134	/* FALLTHROUGH */
	135
	136	/*
	137	* flush_kern_cache_all()
	138	*
	139	* Clean and invalidate the entire cache.
	140	*/
	141	ENTRY(feroceon_flush_kern_cache_all)
	142	mov r2, #VM_EXEC
6c386e58	143
e50d6409	144	__flush_whole_cache:
6c386e58 NP	145	ldr r1, __cache_params
	146	ldmia r1, {r1, r3}
	147	1: orr ip, r1, r3
	148	2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
	149	subs ip, ip, #(1 << 30) @ next way
	150	bcs 2b
	151	subs r1, r1, #(1 << 5) @ next set
	152	bcs 1b
	153
e50d6409	154	tst r2, #VM_EXEC
6c386e58	155	mov ip, #0
e50d6409 AH	156	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	157	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	158	mov pc, lr
	159
	160	/*
	161	* flush_user_cache_range(start, end, flags)
	162	*
	163	* Clean and invalidate a range of cache entries in the
	164	* specified address range.
	165	*
	166	* - start - start address (inclusive)
	167	* - end - end address (exclusive)
	168	* - flags - vm_flags describing address space
	169	*/
6b29e681	170	.align 5
e50d6409	171	ENTRY(feroceon_flush_user_cache_range)
e50d6409 AH	172	sub r3, r1, r0 @ calculate total size
	173	cmp r3, #CACHE_DLIMIT
	174	bgt __flush_whole_cache
	175	1: tst r2, #VM_EXEC
e50d6409 AH	176	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	177	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	178	add r0, r0, #CACHE_DLINESIZE
	179	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	180	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	181	add r0, r0, #CACHE_DLINESIZE
e50d6409 AH	182	cmp r0, r1
	183	blo 1b
	184	tst r2, #VM_EXEC
6c386e58	185	mov ip, #0
e50d6409 AH	186	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	187	mov pc, lr
	188
	189	/*
	190	* coherent_kern_range(start, end)
	191	*
	192	* Ensure coherency between the Icache and the Dcache in the
	193	* region described by start, end. If you have non-snooping
	194	* Harvard caches, you need to implement this function.
	195	*
	196	* - start - virtual start address
	197	* - end - virtual end address
	198	*/
6b29e681	199	.align 5
e50d6409 AH	200	ENTRY(feroceon_coherent_kern_range)
	201	/* FALLTHROUGH */
	202
	203	/*
	204	* coherent_user_range(start, end)
	205	*
	206	* Ensure coherency between the Icache and the Dcache in the
	207	* region described by start, end. If you have non-snooping
	208	* Harvard caches, you need to implement this function.
	209	*
	210	* - start - virtual start address
	211	* - end - virtual end address
	212	*/
	213	ENTRY(feroceon_coherent_user_range)
	214	bic r0, r0, #CACHE_DLINESIZE - 1
	215	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	216	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
	217	add r0, r0, #CACHE_DLINESIZE
	218	cmp r0, r1
	219	blo 1b
	220	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	221	mov pc, lr
	222
	223	/*
2c9b9c84	224	* flush_kern_dcache_area(void *addr, size_t size)
e50d6409 AH	225	*
	226	* Ensure no D cache aliasing occurs, either with itself or
	227	* the I cache
	228	*
2c9b9c84 RK	229	* - addr - kernel address
2c9b9c84 RK	230	* - size - region size
e50d6409	231	*/
6b29e681	232	.align 5
2c9b9c84 RK	233	ENTRY(feroceon_flush_kern_dcache_area)
2c9b9c84 RK	234	add r1, r0, r1
e50d6409 AH	235	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	236	add r0, r0, #CACHE_DLINESIZE
	237	cmp r0, r1
	238	blo 1b
	239	mov r0, #0
	240	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	241	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	242	mov pc, lr
	243
836a8051	244	.align 5
2c9b9c84	245	ENTRY(feroceon_range_flush_kern_dcache_area)
836a8051 SS	246	mrs r2, cpsr
	247	add r1, r0, #PAGE_SZ - CACHE_DLINESIZE @ top addr is inclusive
	248	orr r3, r2, #PSR_I_BIT
	249	msr cpsr_c, r3 @ disable interrupts
	250	mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
	251	mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
	252	msr cpsr_c, r2 @ restore interrupts
	253	mov r0, #0
	254	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	255	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	256	mov pc, lr
	257
e50d6409 AH	258	/*
	259	* dma_inv_range(start, end)
	260	*
	261	* Invalidate (discard) the specified virtual address range.
	262	* May not write back any entries. If 'start' or 'end'
	263	* are not cache line aligned, those lines must be written
	264	* back.
	265	*
	266	* - start - virtual start address
	267	* - end - virtual end address
	268	*
	269	* (same as v4wb)
	270	*/
6b29e681	271	.align 5
702b94bf	272	feroceon_dma_inv_range:
e50d6409	273	tst r0, #CACHE_DLINESIZE - 1
836a8051	274	bic r0, r0, #CACHE_DLINESIZE - 1
e50d6409 AH	275	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	276	tst r1, #CACHE_DLINESIZE - 1
	277	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
e50d6409 AH	278	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	279	add r0, r0, #CACHE_DLINESIZE
	280	cmp r0, r1
	281	blo 1b
	282	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	283	mov pc, lr
	284
836a8051	285	.align 5
702b94bf	286	feroceon_range_dma_inv_range:
836a8051 SS	287	mrs r2, cpsr
	288	tst r0, #CACHE_DLINESIZE - 1
	289	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	290	tst r1, #CACHE_DLINESIZE - 1
	291	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	292	cmp r1, r0
	293	subne r1, r1, #1 @ top address is inclusive
	294	orr r3, r2, #PSR_I_BIT
	295	msr cpsr_c, r3 @ disable interrupts
	296	mcr p15, 5, r0, c15, c14, 0 @ D inv range start
	297	mcr p15, 5, r1, c15, c14, 1 @ D inv range top
	298	msr cpsr_c, r2 @ restore interrupts
	299	mov pc, lr
	300
e50d6409 AH	301	/*
	302	* dma_clean_range(start, end)
	303	*
	304	* Clean the specified virtual address range.
	305	*
	306	* - start - virtual start address
	307	* - end - virtual end address
	308	*
	309	* (same as v4wb)
	310	*/
6b29e681	311	.align 5
702b94bf	312	feroceon_dma_clean_range:
e50d6409 AH	313	bic r0, r0, #CACHE_DLINESIZE - 1
	314	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	315	add r0, r0, #CACHE_DLINESIZE
	316	cmp r0, r1
	317	blo 1b
e50d6409 AH	318	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	319	mov pc, lr
	320
836a8051	321	.align 5
702b94bf	322	feroceon_range_dma_clean_range:
836a8051 SS	323	mrs r2, cpsr
	324	cmp r1, r0
	325	subne r1, r1, #1 @ top address is inclusive
	326	orr r3, r2, #PSR_I_BIT
	327	msr cpsr_c, r3 @ disable interrupts
	328	mcr p15, 5, r0, c15, c13, 0 @ D clean range start
	329	mcr p15, 5, r1, c15, c13, 1 @ D clean range top
	330	msr cpsr_c, r2 @ restore interrupts
	331	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	332	mov pc, lr
	333
e50d6409 AH	334	/*
	335	* dma_flush_range(start, end)
	336	*
	337	* Clean and invalidate the specified virtual address range.
	338	*
	339	* - start - virtual start address
	340	* - end - virtual end address
	341	*/
6b29e681	342	.align 5
e50d6409 AH	343	ENTRY(feroceon_dma_flush_range)
e50d6409 AH	344	bic r0, r0, #CACHE_DLINESIZE - 1
6b29e681	345	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
e50d6409 AH	346	add r0, r0, #CACHE_DLINESIZE
	347	cmp r0, r1
	348	blo 1b
	349	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	350	mov pc, lr
	351
836a8051 SS	352	.align 5
	353	ENTRY(feroceon_range_dma_flush_range)
	354	mrs r2, cpsr
	355	cmp r1, r0
	356	subne r1, r1, #1 @ top address is inclusive
	357	orr r3, r2, #PSR_I_BIT
	358	msr cpsr_c, r3 @ disable interrupts
	359	mcr p15, 5, r0, c15, c15, 0 @ D clean/inv range start
	360	mcr p15, 5, r1, c15, c15, 1 @ D clean/inv range top
	361	msr cpsr_c, r2 @ restore interrupts
	362	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	363	mov pc, lr
	364
a9c9147e RK	365	/*
	366	* dma_map_area(start, size, dir)
	367	* - start - kernel virtual start address
	368	* - size - size of region
	369	* - dir - DMA direction
	370	*/
	371	ENTRY(feroceon_dma_map_area)
	372	add r1, r1, r0
	373	cmp r2, #DMA_TO_DEVICE
	374	beq feroceon_dma_clean_range
	375	bcs feroceon_dma_inv_range
	376	b feroceon_dma_flush_range
	377	ENDPROC(feroceon_dma_map_area)
	378
	379	/*
	380	* dma_map_area(start, size, dir)
	381	* - start - kernel virtual start address
	382	* - size - size of region
	383	* - dir - DMA direction
	384	*/
	385	ENTRY(feroceon_range_dma_map_area)
	386	add r1, r1, r0
	387	cmp r2, #DMA_TO_DEVICE
	388	beq feroceon_range_dma_clean_range
	389	bcs feroceon_range_dma_inv_range
	390	b feroceon_range_dma_flush_range
	391	ENDPROC(feroceon_range_dma_map_area)
	392
	393	/*
	394	* dma_unmap_area(start, size, dir)
	395	* - start - kernel virtual start address
	396	* - size - size of region
	397	* - dir - DMA direction
	398	*/
	399	ENTRY(feroceon_dma_unmap_area)
	400	mov pc, lr
	401	ENDPROC(feroceon_dma_unmap_area)
	402
e50d6409 AH	403	ENTRY(feroceon_cache_fns)
	404	.long feroceon_flush_kern_cache_all
	405	.long feroceon_flush_user_cache_all
	406	.long feroceon_flush_user_cache_range
	407	.long feroceon_coherent_kern_range
	408	.long feroceon_coherent_user_range
2c9b9c84	409	.long feroceon_flush_kern_dcache_area
a9c9147e RK	410	.long feroceon_dma_map_area
a9c9147e RK	411	.long feroceon_dma_unmap_area
e50d6409 AH	412	.long feroceon_dma_flush_range
e50d6409 AH	413
836a8051 SS	414	ENTRY(feroceon_range_cache_fns)
	415	.long feroceon_flush_kern_cache_all
	416	.long feroceon_flush_user_cache_all
	417	.long feroceon_flush_user_cache_range
	418	.long feroceon_coherent_kern_range
	419	.long feroceon_coherent_user_range
2c9b9c84	420	.long feroceon_range_flush_kern_dcache_area
a9c9147e RK	421	.long feroceon_range_dma_map_area
a9c9147e RK	422	.long feroceon_dma_unmap_area
836a8051 SS	423	.long feroceon_range_dma_flush_range
836a8051 SS	424
6b29e681	425	.align 5
e50d6409	426	ENTRY(cpu_feroceon_dcache_clean_area)
4360bb41 RS	427	#if defined(CONFIG_CACHE_FEROCEON_L2) && \
4360bb41 RS	428	!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
99c6dc11 LB	429	mov r2, r0
	430	mov r3, r1
	431	#endif
e50d6409 AH	432	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	433	add r0, r0, #CACHE_DLINESIZE
	434	subs r1, r1, #CACHE_DLINESIZE
	435	bhi 1b
4360bb41 RS	436	#if defined(CONFIG_CACHE_FEROCEON_L2) && \
4360bb41 RS	437	!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
99c6dc11 LB	438	1: mcr p15, 1, r2, c15, c9, 1 @ clean L2 entry
	439	add r2, r2, #CACHE_DLINESIZE
	440	subs r3, r3, #CACHE_DLINESIZE
	441	bhi 1b
	442	#endif
e50d6409 AH	443	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	444	mov pc, lr
	445
	446	/* =============================== PageTable ============================== */
	447
	448	/*
	449	* cpu_feroceon_switch_mm(pgd)
	450	*
	451	* Set the translation base pointer to be as described by pgd.
	452	*
	453	* pgd: new page tables
	454	*/
	455	.align 5
	456	ENTRY(cpu_feroceon_switch_mm)
	457	#ifdef CONFIG_MMU
6c386e58 NP	458	/*
	459	* Note: we wish to call __flush_whole_cache but we need to preserve
	460	* lr to do so. The only way without touching main memory is to
	461	* use r2 which is normally used to test the VM_EXEC flag, and
	462	* compensate locally for the skipped ops if it is not set.
	463	*/
	464	mov r2, lr @ abuse r2 to preserve lr
	465	bl __flush_whole_cache
	466	@ if r2 contains the VM_EXEC bit then the next 2 ops are done already
	467	tst r2, #VM_EXEC
	468	mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
	469	mcreq p15, 0, ip, c7, c10, 4 @ drain WB
	470
e50d6409 AH	471	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
e50d6409 AH	472	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
6c386e58 NP	473	mov pc, r2
6c386e58 NP	474	#else
e50d6409	475	mov pc, lr
6c386e58	476	#endif
e50d6409 AH	477
	478	/*
	479	* cpu_feroceon_set_pte_ext(ptep, pte, ext)
	480	*
	481	* Set a PTE and flush it out
	482	*/
	483	.align 5
	484	ENTRY(cpu_feroceon_set_pte_ext)
	485	#ifdef CONFIG_MMU
da091653	486	armv3_set_pte_ext wc_disable=0
e50d6409	487	mov r0, r0
e50d6409	488	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
4360bb41 RS	489	#if defined(CONFIG_CACHE_FEROCEON_L2) && \
4360bb41 RS	490	!defined(CONFIG_CACHE_FEROCEON_L2_WRITETHROUGH)
99c6dc11 LB	491	mcr p15, 1, r0, c15, c9, 1 @ clean L2 entry
99c6dc11 LB	492	#endif
e50d6409 AH	493	mcr p15, 0, r0, c7, c10, 4 @ drain WB
	494	#endif
	495	mov pc, lr
	496
	497	__INIT
	498
	499	.type __feroceon_setup, #function
	500	__feroceon_setup:
	501	mov r0, #0
	502	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	503	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
	504	#ifdef CONFIG_MMU
	505	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
	506	#endif
	507
e50d6409 AH	508	adr r5, feroceon_crval
	509	ldmia r5, {r5, r6}
	510	mrc p15, 0, r0, c1, c0 @ get control register v4
	511	bic r0, r0, r5
	512	orr r0, r0, r6
e50d6409 AH	513	mov pc, lr
	514	.size __feroceon_setup, . - __feroceon_setup
	515
	516	/*
188237e2 SB	517	* B
	518	* R P
	519	* .RVI UFRS BLDP WCAM
	520	* .011 .001 ..11 0101
e50d6409 AH	521	*
	522	*/
	523	.type feroceon_crval, #object
	524	feroceon_crval:
188237e2	525	crval clear=0x0000773f, mmuset=0x00003135, ucset=0x00001134
e50d6409 AH	526
	527	__INITDATA
	528
	529	/*
	530	* Purpose : Function pointers used to access above functions - all calls
	531	* come through these
	532	*/
	533	.type feroceon_processor_functions, #object
	534	feroceon_processor_functions:
	535	.word v5t_early_abort
4fb28474	536	.word legacy_pabort
e50d6409 AH	537	.word cpu_feroceon_proc_init
	538	.word cpu_feroceon_proc_fin
	539	.word cpu_feroceon_reset
	540	.word cpu_feroceon_do_idle
	541	.word cpu_feroceon_dcache_clean_area
	542	.word cpu_feroceon_switch_mm
	543	.word cpu_feroceon_set_pte_ext
	544	.size feroceon_processor_functions, . - feroceon_processor_functions
	545
	546	.section ".rodata"
	547
	548	.type cpu_arch_name, #object
	549	cpu_arch_name:
	550	.asciz "armv5te"
	551	.size cpu_arch_name, . - cpu_arch_name
	552
	553	.type cpu_elf_name, #object
	554	cpu_elf_name:
	555	.asciz "v5"
	556	.size cpu_elf_name, . - cpu_elf_name
	557
	558	.type cpu_feroceon_name, #object
	559	cpu_feroceon_name:
	560	.asciz "Feroceon"
	561	.size cpu_feroceon_name, . - cpu_feroceon_name
	562
ee0dd840 LB	563	.type cpu_88fr531_name, #object
	564	cpu_88fr531_name:
	565	.asciz "Feroceon 88FR531-vd"
	566	.size cpu_88fr531_name, . - cpu_88fr531_name
	567
0a17c7bc LB	568	.type cpu_88fr571_name, #object
	569	cpu_88fr571_name:
	570	.asciz "Feroceon 88FR571-vd"
	571	.size cpu_88fr571_name, . - cpu_88fr571_name
	572
9c2af6c5 LB	573	.type cpu_88fr131_name, #object
	574	cpu_88fr131_name:
	575	.asciz "Feroceon 88FR131"
	576	.size cpu_88fr131_name, . - cpu_88fr131_name
	577
e50d6409 AH	578	.align
	579
	580	.section ".proc.info.init", #alloc, #execinstr
	581
d910a0aa TP	582	#ifdef CONFIG_CPU_FEROCEON_OLD_ID
	583	.type __feroceon_old_id_proc_info,#object
	584	__feroceon_old_id_proc_info:
ab6d15d5 KW	585	.long 0x41009260
ab6d15d5 KW	586	.long 0xff00fff0
e7068ad3	587	.long PMD_TYPE_SECT \| \
d910a0aa TP	588	PMD_SECT_BUFFERABLE \| \
	589	PMD_SECT_CACHEABLE \| \
	590	PMD_BIT4 \| \
	591	PMD_SECT_AP_WRITE \| \
	592	PMD_SECT_AP_READ
e7068ad3	593	.long PMD_TYPE_SECT \| \
d910a0aa TP	594	PMD_BIT4 \| \
	595	PMD_SECT_AP_WRITE \| \
	596	PMD_SECT_AP_READ
	597	b __feroceon_setup
	598	.long cpu_arch_name
	599	.long cpu_elf_name
	600	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP
	601	.long cpu_feroceon_name
	602	.long feroceon_processor_functions
	603	.long v4wbi_tlb_fns
0ed15071	604	.long feroceon_user_fns
d910a0aa TP	605	.long feroceon_cache_fns
	606	.size __feroceon_old_id_proc_info, . - __feroceon_old_id_proc_info
	607	#endif
	608
ee0dd840 LB	609	.type __88fr531_proc_info,#object
ee0dd840 LB	610	__88fr531_proc_info:
e50d6409 AH	611	.long 0x56055310
e50d6409 AH	612	.long 0xfffffff0
e7068ad3	613	.long PMD_TYPE_SECT \| \
e50d6409 AH	614	PMD_SECT_BUFFERABLE \| \
	615	PMD_SECT_CACHEABLE \| \
	616	PMD_BIT4 \| \
	617	PMD_SECT_AP_WRITE \| \
	618	PMD_SECT_AP_READ
e7068ad3	619	.long PMD_TYPE_SECT \| \
e50d6409 AH	620	PMD_BIT4 \| \
	621	PMD_SECT_AP_WRITE \| \
	622	PMD_SECT_AP_READ
	623	b __feroceon_setup
	624	.long cpu_arch_name
	625	.long cpu_elf_name
	626	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP
ee0dd840	627	.long cpu_88fr531_name
e50d6409 AH	628	.long feroceon_processor_functions
e50d6409 AH	629	.long v4wbi_tlb_fns
0ed15071	630	.long feroceon_user_fns
e50d6409	631	.long feroceon_cache_fns
ee0dd840	632	.size __88fr531_proc_info, . - __88fr531_proc_info
9c2af6c5	633
0a17c7bc LB	634	.type __88fr571_proc_info,#object
	635	__88fr571_proc_info:
	636	.long 0x56155710
	637	.long 0xfffffff0
	638	.long PMD_TYPE_SECT \| \
	639	PMD_SECT_BUFFERABLE \| \
	640	PMD_SECT_CACHEABLE \| \
	641	PMD_BIT4 \| \
	642	PMD_SECT_AP_WRITE \| \
	643	PMD_SECT_AP_READ
	644	.long PMD_TYPE_SECT \| \
	645	PMD_BIT4 \| \
	646	PMD_SECT_AP_WRITE \| \
	647	PMD_SECT_AP_READ
	648	b __feroceon_setup
	649	.long cpu_arch_name
	650	.long cpu_elf_name
	651	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP
	652	.long cpu_88fr571_name
	653	.long feroceon_processor_functions
	654	.long v4wbi_tlb_fns
	655	.long feroceon_user_fns
	656	.long feroceon_range_cache_fns
	657	.size __88fr571_proc_info, . - __88fr571_proc_info
	658
9c2af6c5 LB	659	.type __88fr131_proc_info,#object
	660	__88fr131_proc_info:
	661	.long 0x56251310
	662	.long 0xfffffff0
	663	.long PMD_TYPE_SECT \| \
	664	PMD_SECT_BUFFERABLE \| \
	665	PMD_SECT_CACHEABLE \| \
	666	PMD_BIT4 \| \
	667	PMD_SECT_AP_WRITE \| \
	668	PMD_SECT_AP_READ
	669	.long PMD_TYPE_SECT \| \
	670	PMD_BIT4 \| \
	671	PMD_SECT_AP_WRITE \| \
	672	PMD_SECT_AP_READ
	673	b __feroceon_setup
	674	.long cpu_arch_name
	675	.long cpu_elf_name
	676	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP
	677	.long cpu_88fr131_name
	678	.long feroceon_processor_functions
	679	.long v4wbi_tlb_fns
	680	.long feroceon_user_fns
	681	.long feroceon_range_cache_fns
	682	.size __88fr131_proc_info, . - __88fr131_proc_info