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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-sa110.S | |
3 | * | |
4 | * Copyright (C) 1997-2002 Russell King | |
d090ddda | 5 | * hacked for non-paged-MM by Hyok S. Choi, 2003. |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * MMU functions for SA110 | |
12 | * | |
13 | * These are the low level assembler for performing cache and TLB | |
14 | * functions on the StrongARM-110. | |
15 | */ | |
16 | #include <linux/linkage.h> | |
17 | #include <linux/init.h> | |
18 | #include <asm/assembler.h> | |
e6ae744d | 19 | #include <asm/asm-offsets.h> |
5ec9407d | 20 | #include <asm/hwcap.h> |
a09e64fb | 21 | #include <mach/hardware.h> |
74945c86 | 22 | #include <asm/pgtable-hwdef.h> |
1da177e4 LT |
23 | #include <asm/pgtable.h> |
24 | #include <asm/ptrace.h> | |
25 | ||
bb8d5a55 TG |
26 | #include "proc-macros.S" |
27 | ||
1da177e4 LT |
28 | /* |
29 | * the cache line size of the I and D cache | |
30 | */ | |
31 | #define DCACHELINESIZE 32 | |
95f3df6b | 32 | |
1da177e4 LT |
33 | .text |
34 | ||
35 | /* | |
36 | * cpu_sa110_proc_init() | |
37 | */ | |
38 | ENTRY(cpu_sa110_proc_init) | |
39 | mov r0, #0 | |
40 | mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching | |
41 | mov pc, lr | |
42 | ||
43 | /* | |
44 | * cpu_sa110_proc_fin() | |
45 | */ | |
46 | ENTRY(cpu_sa110_proc_fin) | |
47 | stmfd sp!, {lr} | |
48 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE | |
49 | msr cpsr_c, ip | |
50 | bl v4wb_flush_kern_cache_all @ clean caches | |
51 | 1: mov r0, #0 | |
52 | mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching | |
53 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | |
54 | bic r0, r0, #0x1000 @ ...i............ | |
55 | bic r0, r0, #0x000e @ ............wca. | |
56 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
57 | ldmfd sp!, {pc} | |
58 | ||
59 | /* | |
60 | * cpu_sa110_reset(loc) | |
61 | * | |
62 | * Perform a soft reset of the system. Put the CPU into the | |
63 | * same state as it would be if it had been reset, and branch | |
64 | * to what would be the reset vector. | |
65 | * | |
66 | * loc: location to jump to for soft reset | |
67 | */ | |
68 | .align 5 | |
69 | ENTRY(cpu_sa110_reset) | |
70 | mov ip, #0 | |
71 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | |
72 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
d090ddda | 73 | #ifdef CONFIG_MMU |
1da177e4 | 74 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
d090ddda | 75 | #endif |
1da177e4 LT |
76 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register |
77 | bic ip, ip, #0x000f @ ............wcam | |
78 | bic ip, ip, #0x1100 @ ...i...s........ | |
79 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
80 | mov pc, r0 | |
81 | ||
82 | /* | |
83 | * cpu_sa110_do_idle(type) | |
84 | * | |
85 | * Cause the processor to idle | |
86 | * | |
87 | * type: call type: | |
88 | * 0 = slow idle | |
89 | * 1 = fast idle | |
90 | * 2 = switch to slow processor clock | |
91 | * 3 = switch to fast processor clock | |
92 | */ | |
93 | .align 5 | |
94 | ||
95 | ENTRY(cpu_sa110_do_idle) | |
96 | mcr p15, 0, ip, c15, c2, 2 @ disable clock switching | |
97 | ldr r1, =UNCACHEABLE_ADDR @ load from uncacheable loc | |
98 | ldr r1, [r1, #0] @ force switch to MCLK | |
99 | mov r0, r0 @ safety | |
100 | mov r0, r0 @ safety | |
101 | mov r0, r0 @ safety | |
102 | mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned | |
103 | mov r0, r0 @ safety | |
104 | mov r0, r0 @ safety | |
105 | mov r0, r0 @ safety | |
106 | mcr p15, 0, r0, c15, c1, 2 @ enable clock switching | |
107 | mov pc, lr | |
108 | ||
109 | /* ================================= CACHE ================================ */ | |
110 | ||
111 | /* | |
112 | * cpu_sa110_dcache_clean_area(addr,sz) | |
113 | * | |
114 | * Clean the specified entry of any caches such that the MMU | |
115 | * translation fetches will obtain correct data. | |
116 | * | |
117 | * addr: cache-unaligned virtual address | |
118 | */ | |
119 | .align 5 | |
120 | ENTRY(cpu_sa110_dcache_clean_area) | |
121 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
122 | add r0, r0, #DCACHELINESIZE | |
123 | subs r1, r1, #DCACHELINESIZE | |
124 | bhi 1b | |
125 | mov pc, lr | |
126 | ||
127 | /* =============================== PageTable ============================== */ | |
128 | ||
129 | /* | |
130 | * cpu_sa110_switch_mm(pgd) | |
131 | * | |
132 | * Set the translation base pointer to be as described by pgd. | |
133 | * | |
134 | * pgd: new page tables | |
135 | */ | |
136 | .align 5 | |
137 | ENTRY(cpu_sa110_switch_mm) | |
d090ddda | 138 | #ifdef CONFIG_MMU |
95f3df6b RK |
139 | str lr, [sp, #-4]! |
140 | bl v4wb_flush_kern_cache_all @ clears IP | |
1da177e4 | 141 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
95f3df6b RK |
142 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
143 | ldr pc, [sp], #4 | |
d090ddda HC |
144 | #else |
145 | mov pc, lr | |
146 | #endif | |
1da177e4 LT |
147 | |
148 | /* | |
ad1ae2fe | 149 | * cpu_sa110_set_pte_ext(ptep, pte, ext) |
1da177e4 LT |
150 | * |
151 | * Set a PTE and flush it out | |
152 | */ | |
153 | .align 5 | |
ad1ae2fe | 154 | ENTRY(cpu_sa110_set_pte_ext) |
d090ddda | 155 | #ifdef CONFIG_MMU |
da091653 | 156 | armv3_set_pte_ext wc_disable=0 |
1da177e4 LT |
157 | mov r0, r0 |
158 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
159 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
d090ddda | 160 | #endif |
1da177e4 LT |
161 | mov pc, lr |
162 | ||
163 | __INIT | |
164 | ||
165 | .type __sa110_setup, #function | |
166 | __sa110_setup: | |
167 | mov r10, #0 | |
168 | mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 | |
169 | mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4 | |
d090ddda | 170 | #ifdef CONFIG_MMU |
1da177e4 | 171 | mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 |
d090ddda | 172 | #endif |
22b19086 RK |
173 | |
174 | adr r5, sa110_crval | |
175 | ldmia r5, {r5, r6} | |
1da177e4 | 176 | mrc p15, 0, r0, c1, c0 @ get control register v4 |
1da177e4 | 177 | bic r0, r0, r5 |
22b19086 | 178 | orr r0, r0, r6 |
1da177e4 LT |
179 | mov pc, lr |
180 | .size __sa110_setup, . - __sa110_setup | |
181 | ||
182 | /* | |
183 | * R | |
184 | * .RVI ZFRS BLDP WCAM | |
185 | * ..01 0001 ..11 1101 | |
186 | * | |
187 | */ | |
22b19086 RK |
188 | .type sa110_crval, #object |
189 | sa110_crval: | |
190 | crval clear=0x00003f3f, mmuset=0x0000113d, ucset=0x00001130 | |
1da177e4 LT |
191 | |
192 | __INITDATA | |
193 | ||
194 | /* | |
195 | * Purpose : Function pointers used to access above functions - all calls | |
196 | * come through these | |
197 | */ | |
198 | ||
199 | .type sa110_processor_functions, #object | |
200 | ENTRY(sa110_processor_functions) | |
201 | .word v4_early_abort | |
4fb28474 | 202 | .word legacy_pabort |
1da177e4 LT |
203 | .word cpu_sa110_proc_init |
204 | .word cpu_sa110_proc_fin | |
205 | .word cpu_sa110_reset | |
206 | .word cpu_sa110_do_idle | |
207 | .word cpu_sa110_dcache_clean_area | |
208 | .word cpu_sa110_switch_mm | |
ad1ae2fe | 209 | .word cpu_sa110_set_pte_ext |
1da177e4 LT |
210 | .size sa110_processor_functions, . - sa110_processor_functions |
211 | ||
212 | .section ".rodata" | |
213 | ||
214 | .type cpu_arch_name, #object | |
215 | cpu_arch_name: | |
216 | .asciz "armv4" | |
217 | .size cpu_arch_name, . - cpu_arch_name | |
218 | ||
219 | .type cpu_elf_name, #object | |
220 | cpu_elf_name: | |
221 | .asciz "v4" | |
222 | .size cpu_elf_name, . - cpu_elf_name | |
223 | ||
224 | .type cpu_sa110_name, #object | |
225 | cpu_sa110_name: | |
226 | .asciz "StrongARM-110" | |
227 | .size cpu_sa110_name, . - cpu_sa110_name | |
228 | ||
229 | .align | |
230 | ||
02b7dd12 | 231 | .section ".proc.info.init", #alloc, #execinstr |
1da177e4 LT |
232 | |
233 | .type __sa110_proc_info,#object | |
234 | __sa110_proc_info: | |
235 | .long 0x4401a100 | |
236 | .long 0xfffffff0 | |
237 | .long PMD_TYPE_SECT | \ | |
238 | PMD_SECT_BUFFERABLE | \ | |
239 | PMD_SECT_CACHEABLE | \ | |
240 | PMD_SECT_AP_WRITE | \ | |
241 | PMD_SECT_AP_READ | |
8799ee9f RK |
242 | .long PMD_TYPE_SECT | \ |
243 | PMD_SECT_AP_WRITE | \ | |
244 | PMD_SECT_AP_READ | |
1da177e4 LT |
245 | b __sa110_setup |
246 | .long cpu_arch_name | |
247 | .long cpu_elf_name | |
248 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT | |
249 | .long cpu_sa110_name | |
250 | .long sa110_processor_functions | |
251 | .long v4wb_tlb_fns | |
252 | .long v4wb_user_fns | |
253 | .long v4wb_cache_fns | |
254 | .size __sa110_proc_info, . - __sa110_proc_info |