[mirror_ubuntu-zesty-kernel.git] / arch / arm / mm / proc-v6.S

/*
 *  linux/arch/arm/mm/proc-v6.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *  Modified by Catalin Marinas for noMMU support
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv6 processor support.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#define D_CACHE_LINE_SIZE	32

#define TTB_C		(1 << 0)
#define TTB_S		(1 << 1)
#define TTB_IMP		(1 << 2)
#define TTB_RGN_NC	(0 << 3)
#define TTB_RGN_WBWA	(1 << 3)
#define TTB_RGN_WT	(2 << 3)
#define TTB_RGN_WB	(3 << 3)

#define TTB_FLAGS_UP	TTB_RGN_WBWA
#define PMD_FLAGS_UP	PMD_SECT_WB
#define TTB_FLAGS_SMP	TTB_RGN_WBWA|TTB_S
#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S

ENTRY(cpu_v6_proc_init)
	ret	lr

ENTRY(cpu_v6_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ret	lr

/*
 *	cpu_v6_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 */
	.align	5
	.pushsection	.idmap.text, "ax"
ENTRY(cpu_v6_reset)
	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x1			@ ...............m
	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
	mov	r1, #0
	mcr	p15, 0, r1, c7, c5, 4		@ ISB
	ret	r0
ENDPROC(cpu_v6_reset)
	.popsection

/*
 *	cpu_v6_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */

/* See jira SW-5991 for details of this workaround */
ENTRY(cpu_v6_do_idle)
	.align 5
	mov     r1, #2
1:	subs	r1, #1
	nop
	mcreq	p15, 0, r1, c7, c10, 4		@ DWB - WFI may enter a low-power mode
	mcreq	p15, 0, r1, c7, c0, 4		@ wait for interrupt
	nop
	nop
	nop
	bne 1b
	ret	lr

ENTRY(cpu_v6_dcache_clean_area)
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #D_CACHE_LINE_SIZE
	subs	r1, r1, #D_CACHE_LINE_SIZE
	bhi	1b
	ret	lr

/*
 *	cpu_v6_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys
 *
 *	- pgd_phys - physical address of new TTB
 *
 *	It is assumed that:
 *	- we are not using split page tables
 */
ENTRY(cpu_v6_switch_mm)
#ifdef CONFIG_MMU
	mov	r2, #0
	mmid	r1, r1				@ get mm->context.id
	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
#ifdef CONFIG_PID_IN_CONTEXTIDR
	mrc	p15, 0, r2, c13, c0, 1		@ read current context ID
	bic	r2, r2, #0xff			@ extract the PID
	and	r1, r1, #0xff
	orr	r1, r1, r2			@ insert into new context ID
#endif
	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
#endif
	ret	lr

/*
 *	cpu_v6_set_pte_ext(ptep, pte, ext)
 *
 *	Set a level 2 translation table entry.
 *
 *	- ptep  - pointer to level 2 translation table entry
 *		  (hardware version is stored at -1024 bytes)
 *	- pte   - PTE value to store
 *	- ext	- value for extended PTE bits
 */
	armv6_mt_table cpu_v6

ENTRY(cpu_v6_set_pte_ext)
#ifdef CONFIG_MMU
	armv6_set_pte_ext cpu_v6
#endif
	ret	lr

/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
.globl	cpu_v6_suspend_size
.equ	cpu_v6_suspend_size, 4 * 6
#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v6_do_suspend)
	stmfd	sp!, {r4 - r9, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
#ifdef CONFIG_MMU
	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
	mrc	p15, 0, r6, c2, c0, 1	@ Translation table base 1
#endif
	mrc	p15, 0, r7, c1, c0, 1	@ auxiliary control register
	mrc	p15, 0, r8, c1, c0, 2	@ co-processor access control
	mrc	p15, 0, r9, c1, c0, 0	@ control register
	stmia	r0, {r4 - r9}
	ldmfd	sp!, {r4- r9, pc}
ENDPROC(cpu_v6_do_suspend)

ENTRY(cpu_v6_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c14, 0	@ clean+invalidate D cache
	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
	mcr	p15, 0, ip, c7, c15, 0	@ clean+invalidate cache
	mcr	p15, 0, ip, c7, c10, 4	@ drain write buffer
	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
	ldmia	r0, {r4 - r9}
	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
#ifdef CONFIG_MMU
	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
	mcr	p15, 0, r1, c2, c0, 0	@ Translation table base 0
	mcr	p15, 0, r6, c2, c0, 1	@ Translation table base 1
	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
#endif
	mcr	p15, 0, r7, c1, c0, 1	@ auxiliary control register
	mcr	p15, 0, r8, c1, c0, 2	@ co-processor access control
	mcr	p15, 0, ip, c7, c5, 4	@ ISB
	mov	r0, r9			@ control register
	b	cpu_resume_mmu
ENDPROC(cpu_v6_do_resume)
#endif

	string	cpu_v6_name, "ARMv6-compatible processor"

	.align

/*
 *	__v6_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	We automatically detect if we have a Harvard cache, and use the
 *	Harvard cache control instructions insead of the unified cache
 *	control instructions.
 *
 *	This should be able to cover all ARMv6 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v6_setup:
#ifdef CONFIG_SMP
	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)	@ Enable SMP/nAMP mode
	ALT_UP(nop)
	orr	r0, r0, #0x20
	ALT_SMP(mcr	p15, 0, r0, c1, c0, 1)
	ALT_UP(nop)
#endif

	mov	r0, #0
	mcr	p15, 0, r0, c7, c14, 0		@ clean+invalidate D cache
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c15, 0		@ clean+invalidate cache
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7, 0		@ invalidate I + D TLBs
	mcr	p15, 0, r0, c2, c0, 2		@ TTB control register
	ALT_SMP(orr	r4, r4, #TTB_FLAGS_SMP)
	ALT_UP(orr	r4, r4, #TTB_FLAGS_UP)
	ALT_SMP(orr	r8, r8, #TTB_FLAGS_SMP)
	ALT_UP(orr	r8, r8, #TTB_FLAGS_UP)
	mcr	p15, 0, r8, c2, c0, 1		@ load TTB1
#endif /* CONFIG_MMU */
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer and
						@ complete invalidations
	adr	r5, v6_crval
	ldmia	r5, {r5, r6}
 ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
#ifdef CONFIG_ARM_ERRATA_364296
	/*
	 * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
	 * corruption with hit-under-miss enabled). The conditional code below
	 * (setting the undocumented bit 31 in the auxiliary control register
	 * and the FI bit in the control register) disables hit-under-miss
	 * without putting the processor into full low interrupt latency mode.
	 */
	ldr	r6, =0x4107b362			@ id for ARM1136 r0p2
	mrc	p15, 0, r5, c0, c0, 0		@ get processor id
	teq	r5, r6				@ check for the faulty core
	mrceq	p15, 0, r5, c1, c0, 1		@ load aux control reg
	orreq	r5, r5, #(1 << 31)		@ set the undocumented bit 31
	mcreq	p15, 0, r5, c1, c0, 1		@ write aux control reg
	orreq	r0, r0, #(1 << 21)		@ low interrupt latency configuration
#endif
	ret	lr				@ return to head.S:__ret

	/*
	 *         V X F   I D LR
	 * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
	 * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
	 *         0 110       0011 1.00 .111 1101 < we want
	 */
	.type	v6_crval, #object
v6_crval:
	crval	clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1

	.section ".rodata"

	string	cpu_arch_name, "armv6"
	string	cpu_elf_name, "v6"
	.align

	.section ".proc.info.init", #alloc

	/*
	 * Match any ARMv6 processor core.
	 */
	.type	__v6_proc_info, #object
__v6_proc_info:
	.long	0x0007b000
	.long	0x0007f000
	ALT_SMP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_SMP)
	ALT_UP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_UP)
	.long   PMD_TYPE_SECT | \
		PMD_SECT_XN | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	initfn	__v6_setup, __v6_proc_info
	.long	cpu_arch_name
	.long	cpu_elf_name
	/* See also feat_v6_fixup() for HWCAP_TLS */
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS
	.long	cpu_v6_name
	.long	v6_processor_functions
	.long	v6wbi_tlb_fns
	.long	v6_user_fns
	.long	v6_cache_fns
	.size	__v6_proc_info, . - __v6_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-v6.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
d090ddda	5	* Modified by Catalin Marinas for noMMU support
1da177e4 LT	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This is the "shell" of the ARMv6 processor support.
	12	*/
991da17e	13	#include <linux/init.h>
1da177e4 LT	14	#include <linux/linkage.h>
1da177e4 LT	15	#include <asm/assembler.h>
e6ae744d	16	#include <asm/asm-offsets.h>
5ec9407d	17	#include <asm/hwcap.h>
74945c86	18	#include <asm/pgtable-hwdef.h>
1da177e4 LT	19	#include <asm/pgtable.h>
	20
	21	#include "proc-macros.S"
	22
	23	#define D_CACHE_LINE_SIZE 32
	24
3747b36e RK	25	#define TTB_C (1 << 0)
	26	#define TTB_S (1 << 1)
	27	#define TTB_IMP (1 << 2)
	28	#define TTB_RGN_NC (0 << 3)
	29	#define TTB_RGN_WBWA (1 << 3)
	30	#define TTB_RGN_WT (2 << 3)
	31	#define TTB_RGN_WB (3 << 3)
	32
f00ec48f RK	33	#define TTB_FLAGS_UP TTB_RGN_WBWA
	34	#define PMD_FLAGS_UP PMD_SECT_WB
	35	#define TTB_FLAGS_SMP TTB_RGN_WBWA\|TTB_S
	36	#define PMD_FLAGS_SMP PMD_SECT_WBWA\|PMD_SECT_S
f2131d34	37
1da177e4	38	ENTRY(cpu_v6_proc_init)
6ebbf2ce	39	ret lr
1da177e4 LT	40
1da177e4 LT	41	ENTRY(cpu_v6_proc_fin)
67c5587a TL	42	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	43	bic r0, r0, #0x1000 @ ...i............
	44	bic r0, r0, #0x0006 @ .............ca.
	45	mcr p15, 0, r0, c1, c0, 0 @ disable caches
6ebbf2ce	46	ret lr
1da177e4 LT	47
	48	/*
	49	* cpu_v6_reset(loc)
	50	*
	51	* Perform a soft reset of the system. Put the CPU into the
	52	* same state as it would be if it had been reset, and branch
	53	* to what would be the reset vector.
	54	*
	55	* - loc - location to jump to for soft reset
1da177e4 LT	56	*/
1da177e4 LT	57	.align 5
1a4baafa	58	.pushsection .idmap.text, "ax"
1da177e4	59	ENTRY(cpu_v6_reset)
f4daf06f WD	60	mrc p15, 0, r1, c1, c0, 0 @ ctrl register
	61	bic r1, r1, #0x1 @ ...............m
	62	mcr p15, 0, r1, c1, c0, 0 @ disable MMU
	63	mov r1, #0
	64	mcr p15, 0, r1, c7, c5, 4 @ ISB
6ebbf2ce	65	ret r0
1a4baafa WD	66	ENDPROC(cpu_v6_reset)
1a4baafa WD	67	.popsection
1da177e4 LT	68
	69	/*
	70	* cpu_v6_do_idle()
	71	*
	72	* Idle the processor (eg, wait for interrupt).
	73	*
	74	* IRQs are already disabled.
	75	*/
967e6def	76
967e6def	77	/* See jira SW-5991 for details of this workaround */
1da177e4	78	ENTRY(cpu_v6_do_idle)
967e6def	79	.align 5
	80	mov r1, #2
	81	1: subs r1, #1
	82	nop
	83	mcreq p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode
	84	mcreq p15, 0, r1, c7, c0, 4 @ wait for interrupt
	85	nop
	86	nop
	87	nop
	88	bne 1b
6ebbf2ce	89	ret lr
1da177e4 LT	90
1da177e4 LT	91	ENTRY(cpu_v6_dcache_clean_area)
1da177e4 LT	92	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	93	add r0, r0, #D_CACHE_LINE_SIZE
	94	subs r1, r1, #D_CACHE_LINE_SIZE
	95	bhi 1b
6ebbf2ce	96	ret lr
1da177e4 LT	97
1da177e4 LT	98	/*
2b6e204f	99	* cpu_v6_switch_mm(pgd_phys, tsk)
1da177e4 LT	100	*
	101	* Set the translation table base pointer to be pgd_phys
	102	*
	103	* - pgd_phys - physical address of new TTB
	104	*
	105	* It is assumed that:
	106	* - we are not using split page tables
	107	*/
	108	ENTRY(cpu_v6_switch_mm)
d090ddda	109	#ifdef CONFIG_MMU
1da177e4	110	mov r2, #0
251019fb	111	mmid r1, r1 @ get mm->context.id
f00ec48f RK	112	ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
f00ec48f RK	113	ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
d93742f5	114	mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
1da177e4 LT	115	mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
1da177e4 LT	116	mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
575320d6 WD	117	#ifdef CONFIG_PID_IN_CONTEXTIDR
	118	mrc p15, 0, r2, c13, c0, 1 @ read current context ID
	119	bic r2, r2, #0xff @ extract the PID
	120	and r1, r1, #0xff
	121	orr r1, r1, r2 @ insert into new context ID
	122	#endif
1da177e4	123	mcr p15, 0, r1, c13, c0, 1 @ set context ID
d090ddda	124	#endif
6ebbf2ce	125	ret lr
1da177e4	126
1da177e4	127	/*
ad1ae2fe	128	* cpu_v6_set_pte_ext(ptep, pte, ext)
1da177e4 LT	129	*
	130	* Set a level 2 translation table entry.
	131	*
	132	* - ptep - pointer to level 2 translation table entry
	133	* (hardware version is stored at -1024 bytes)
	134	* - pte - PTE value to store
ad1ae2fe	135	* - ext - value for extended PTE bits
1da177e4	136	*/
639b0ae7 RK	137	armv6_mt_table cpu_v6
639b0ae7 RK	138
ad1ae2fe	139	ENTRY(cpu_v6_set_pte_ext)
d090ddda	140	#ifdef CONFIG_MMU
639b0ae7	141	armv6_set_pte_ext cpu_v6
d090ddda	142	#endif
6ebbf2ce	143	ret lr
1da177e4	144
f6b0fa02 RK	145	/* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */
f6b0fa02 RK	146	.globl cpu_v6_suspend_size
1aede681	147	.equ cpu_v6_suspend_size, 4 * 6
b6c7aabd	148	#ifdef CONFIG_ARM_CPU_SUSPEND
f6b0fa02	149	ENTRY(cpu_v6_do_suspend)
1aede681	150	stmfd sp!, {r4 - r9, lr}
f6b0fa02	151	mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
aa1aadc3	152	#ifdef CONFIG_MMU
1aede681 RK	153	mrc p15, 0, r5, c3, c0, 0 @ Domain ID
1aede681 RK	154	mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1
aa1aadc3	155	#endif
1aede681 RK	156	mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register
	157	mrc p15, 0, r8, c1, c0, 2 @ co-processor access control
	158	mrc p15, 0, r9, c1, c0, 0 @ control register
	159	stmia r0, {r4 - r9}
	160	ldmfd sp!, {r4- r9, pc}
f6b0fa02 RK	161	ENDPROC(cpu_v6_do_suspend)
	162
	163	ENTRY(cpu_v6_do_resume)
	164	mov ip, #0
	165	mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache
	166	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	167	mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache
	168	mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
1aede681 RK	169	mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
1aede681 RK	170	ldmia r0, {r4 - r9}
f6b0fa02	171	mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
aa1aadc3	172	#ifdef CONFIG_MMU
1aede681	173	mcr p15, 0, r5, c3, c0, 0 @ Domain ID
de8e71ca RK	174	ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
	175	ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
	176	mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0
1aede681	177	mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1
aa1aadc3 WD	178	mcr p15, 0, ip, c2, c0, 2 @ TTB control register
aa1aadc3 WD	179	#endif
1aede681 RK	180	mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register
1aede681 RK	181	mcr p15, 0, r8, c1, c0, 2 @ co-processor access control
f6b0fa02	182	mcr p15, 0, ip, c7, c5, 4 @ ISB
1aede681	183	mov r0, r9 @ control register
f6b0fa02 RK	184	b cpu_resume_mmu
f6b0fa02 RK	185	ENDPROC(cpu_v6_do_resume)
f6b0fa02	186	#endif
1da177e4	187
7b7dc6e8	188	string cpu_v6_name, "ARMv6-compatible processor"
edabd38e	189
1da177e4 LT	190	.align
1da177e4 LT	191
1da177e4 LT	192	/*
	193	* __v6_setup
	194	*
	195	* Initialise TLB, Caches, and MMU state ready to switch the MMU
	196	* on. Return in r0 the new CP15 C1 control register setting.
	197	*
	198	* We automatically detect if we have a Harvard cache, and use the
	199	* Harvard cache control instructions insead of the unified cache
	200	* control instructions.
	201	*
	202	* This should be able to cover all ARMv6 cores.
	203	*
	204	* It is assumed that:
	205	* - cache type register is implemented
	206	*/
	207	__v6_setup:
862184fe	208	#ifdef CONFIG_SMP
f00ec48f RK	209	ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode
f00ec48f RK	210	ALT_UP(nop)
862184fe	211	orr r0, r0, #0x20
f00ec48f RK	212	ALT_SMP(mcr p15, 0, r0, c1, c0, 1)
f00ec48f RK	213	ALT_UP(nop)
862184fe RK	214	#endif
862184fe RK	215
1da177e4 LT	216	mov r0, #0
	217	mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache
	218	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	219	mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache
d090ddda	220	#ifdef CONFIG_MMU
1da177e4 LT	221	mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs
1da177e4 LT	222	mcr p15, 0, r0, c2, c0, 2 @ TTB control register
f00ec48f RK	223	ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
f00ec48f RK	224	ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
d427958a CM	225	ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
	226	ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
	227	mcr p15, 0, r8, c2, c0, 1 @ load TTB1
d090ddda	228	#endif /* CONFIG_MMU */
bae0ca2b WD	229	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer and
bae0ca2b WD	230	@ complete invalidations
22b19086 RK	231	adr r5, v6_crval
22b19086 RK	232	ldmia r5, {r5, r6}
457c2403	233	ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
1da177e4	234	mrc p15, 0, r0, c1, c0, 0 @ read control register
1da177e4	235	bic r0, r0, r5 @ clear bits them
22b19086	236	orr r0, r0, r6 @ set them
145e10e1 CM	237	#ifdef CONFIG_ARM_ERRATA_364296
	238	/*
	239	* Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data
	240	* corruption with hit-under-miss enabled). The conditional code below
	241	* (setting the undocumented bit 31 in the auxiliary control register
	242	* and the FI bit in the control register) disables hit-under-miss
	243	* without putting the processor into full low interrupt latency mode.
	244	*/
	245	ldr r6, =0x4107b362 @ id for ARM1136 r0p2
	246	mrc p15, 0, r5, c0, c0, 0 @ get processor id
	247	teq r5, r6 @ check for the faulty core
	248	mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg
	249	orreq r5, r5, #(1 << 31) @ set the undocumented bit 31
	250	mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg
	251	orreq r0, r0, #(1 << 21) @ low interrupt latency configuration
	252	#endif
6ebbf2ce	253	ret lr @ return to head.S:__ret
1da177e4 LT	254
	255	/*
	256	* V X F I D LR
	257	* .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM
	258	* rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced
	259	* 0 110 0011 1.00 .111 1101 < we want
	260	*/
22b19086 RK	261	.type v6_crval, #object
	262	v6_crval:
	263	crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c
1da177e4	264
5085f3ff RK	265	__INITDATA
5085f3ff RK	266
7b7dc6e8 DM	267	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
7b7dc6e8 DM	268	define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1
1da177e4	269
5085f3ff RK	270	.section ".rodata"
5085f3ff RK	271
7b7dc6e8 DM	272	string cpu_arch_name, "armv6"
7b7dc6e8 DM	273	string cpu_elf_name, "v6"
1da177e4 LT	274	.align
1da177e4 LT	275
bf35706f	276	.section ".proc.info.init", #alloc
1da177e4 LT	277
	278	/*
	279	* Match any ARMv6 processor core.
	280	*/
	281	.type __v6_proc_info, #object
	282	__v6_proc_info:
	283	.long 0x0007b000
	284	.long 0x0007f000
f00ec48f RK	285	ALT_SMP(.long \
	286	PMD_TYPE_SECT \| \
	287	PMD_SECT_AP_WRITE \| \
	288	PMD_SECT_AP_READ \| \
	289	PMD_FLAGS_SMP)
	290	ALT_UP(.long \
	291	PMD_TYPE_SECT \| \
1da177e4	292	PMD_SECT_AP_WRITE \| \
4b46d641	293	PMD_SECT_AP_READ \| \
f00ec48f	294	PMD_FLAGS_UP)
8799ee9f RK	295	.long PMD_TYPE_SECT \| \
	296	PMD_SECT_XN \| \
	297	PMD_SECT_AP_WRITE \| \
	298	PMD_SECT_AP_READ
bf35706f	299	initfn __v6_setup, __v6_proc_info
1da177e4 LT	300	.long cpu_arch_name
1da177e4 LT	301	.long cpu_elf_name
f159f4ed TL	302	/* See also feat_v6_fixup() for HWCAP_TLS */
f159f4ed TL	303	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_JAVA\|HWCAP_TLS
1da177e4 LT	304	.long cpu_v6_name
	305	.long v6_processor_functions
	306	.long v6wbi_tlb_fns
	307	.long v6_user_fns
	308	.long v6_cache_fns
	309	.size __v6_proc_info, . - __v6_proc_info