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1b6ba46b CM |
1 | /* |
2 | * arch/arm/mm/proc-v7-3level.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * Copyright (C) 2011 ARM Ltd. | |
6 | * Author: Catalin Marinas <catalin.marinas@arm.com> | |
7 | * based on arch/arm/mm/proc-v7-2level.S | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License version 2 as | |
11 | * published by the Free Software Foundation. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #define TTB_IRGN_NC (0 << 8) | |
24 | #define TTB_IRGN_WBWA (1 << 8) | |
25 | #define TTB_IRGN_WT (2 << 8) | |
26 | #define TTB_IRGN_WB (3 << 8) | |
27 | #define TTB_RGN_NC (0 << 10) | |
28 | #define TTB_RGN_OC_WBWA (1 << 10) | |
29 | #define TTB_RGN_OC_WT (2 << 10) | |
30 | #define TTB_RGN_OC_WB (3 << 10) | |
31 | #define TTB_S (3 << 12) | |
32 | #define TTB_EAE (1 << 31) | |
33 | ||
34 | /* PTWs cacheable, inner WB not shareable, outer WB not shareable */ | |
35 | #define TTB_FLAGS_UP (TTB_IRGN_WB|TTB_RGN_OC_WB) | |
36 | #define PMD_FLAGS_UP (PMD_SECT_WB) | |
37 | ||
38 | /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ | |
39 | #define TTB_FLAGS_SMP (TTB_IRGN_WBWA|TTB_S|TTB_RGN_OC_WBWA) | |
40 | #define PMD_FLAGS_SMP (PMD_SECT_WBWA|PMD_SECT_S) | |
41 | ||
42 | /* | |
43 | * cpu_v7_switch_mm(pgd_phys, tsk) | |
44 | * | |
45 | * Set the translation table base pointer to be pgd_phys (physical address of | |
46 | * the new TTB). | |
47 | */ | |
48 | ENTRY(cpu_v7_switch_mm) | |
49 | #ifdef CONFIG_MMU | |
50 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | |
51 | and r3, r1, #0xff | |
52 | mov r3, r3, lsl #(48 - 32) @ ASID | |
53 | mcrr p15, 0, r0, r3, c2 @ set TTB 0 | |
54 | isb | |
55 | #endif | |
56 | mov pc, lr | |
57 | ENDPROC(cpu_v7_switch_mm) | |
58 | ||
59 | /* | |
60 | * cpu_v7_set_pte_ext(ptep, pte) | |
61 | * | |
62 | * Set a level 2 translation table entry. | |
63 | * - ptep - pointer to level 3 translation table entry | |
64 | * - pte - PTE value to store (64-bit in r2 and r3) | |
65 | */ | |
66 | ENTRY(cpu_v7_set_pte_ext) | |
67 | #ifdef CONFIG_MMU | |
68 | tst r2, #L_PTE_PRESENT | |
69 | beq 1f | |
70 | tst r3, #1 << (55 - 32) @ L_PTE_DIRTY | |
71 | orreq r2, #L_PTE_RDONLY | |
72 | 1: strd r2, r3, [r0] | |
73 | mcr p15, 0, r0, c7, c10, 1 @ flush_pte | |
74 | #endif | |
75 | mov pc, lr | |
76 | ENDPROC(cpu_v7_set_pte_ext) | |
77 | ||
78 | /* | |
79 | * Memory region attributes for LPAE (defined in pgtable-3level.h): | |
80 | * | |
81 | * n = AttrIndx[2:0] | |
82 | * | |
83 | * n MAIR | |
84 | * UNCACHED 000 00000000 | |
85 | * BUFFERABLE 001 01000100 | |
86 | * DEV_WC 001 01000100 | |
87 | * WRITETHROUGH 010 10101010 | |
88 | * WRITEBACK 011 11101110 | |
89 | * DEV_CACHED 011 11101110 | |
90 | * DEV_SHARED 100 00000100 | |
91 | * DEV_NONSHARED 100 00000100 | |
92 | * unused 101 | |
93 | * unused 110 | |
94 | * WRITEALLOC 111 11111111 | |
95 | */ | |
96 | .equ PRRR, 0xeeaa4400 @ MAIR0 | |
97 | .equ NMRR, 0xff000004 @ MAIR1 | |
98 | ||
99 | /* | |
100 | * Macro for setting up the TTBRx and TTBCR registers. | |
101 | * - \ttbr1 updated. | |
102 | */ | |
103 | .macro v7_ttb_setup, zero, ttbr0, ttbr1, tmp | |
104 | ldr \tmp, =swapper_pg_dir @ swapper_pg_dir virtual address | |
105 | cmp \ttbr1, \tmp @ PHYS_OFFSET > PAGE_OFFSET? (branch below) | |
106 | mrc p15, 0, \tmp, c2, c0, 2 @ TTB control register | |
107 | orr \tmp, \tmp, #TTB_EAE | |
108 | ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP) | |
109 | ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP) | |
110 | ALT_SMP(orr \tmp, \tmp, #TTB_FLAGS_SMP << 16) | |
111 | ALT_UP(orr \tmp, \tmp, #TTB_FLAGS_UP << 16) | |
112 | /* | |
113 | * TTBR0/TTBR1 split (PAGE_OFFSET): | |
114 | * 0x40000000: T0SZ = 2, T1SZ = 0 (not used) | |
115 | * 0x80000000: T0SZ = 0, T1SZ = 1 | |
116 | * 0xc0000000: T0SZ = 0, T1SZ = 2 | |
117 | * | |
118 | * Only use this feature if PHYS_OFFSET <= PAGE_OFFSET, otherwise | |
119 | * booting secondary CPUs would end up using TTBR1 for the identity | |
120 | * mapping set up in TTBR0. | |
121 | */ | |
122 | bhi 9001f @ PHYS_OFFSET > PAGE_OFFSET? | |
123 | orr \tmp, \tmp, #(((PAGE_OFFSET >> 30) - 1) << 16) @ TTBCR.T1SZ | |
124 | #if defined CONFIG_VMSPLIT_2G | |
125 | /* PAGE_OFFSET == 0x80000000, T1SZ == 1 */ | |
126 | add \ttbr1, \ttbr1, #1 << 4 @ skip two L1 entries | |
127 | #elif defined CONFIG_VMSPLIT_3G | |
128 | /* PAGE_OFFSET == 0xc0000000, T1SZ == 2 */ | |
129 | add \ttbr1, \ttbr1, #4096 * (1 + 3) @ only L2 used, skip pgd+3*pmd | |
130 | #endif | |
131 | /* CONFIG_VMSPLIT_1G does not need TTBR1 adjustment */ | |
132 | 9001: mcr p15, 0, \tmp, c2, c0, 2 @ TTB control register | |
133 | mcrr p15, 1, \ttbr1, \zero, c2 @ load TTBR1 | |
134 | .endm | |
135 | ||
136 | __CPUINIT | |
137 | ||
138 | /* | |
139 | * AT | |
140 | * TFR EV X F IHD LR S | |
141 | * .EEE ..EE PUI. .TAT 4RVI ZWRS BLDP WCAM | |
142 | * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced | |
143 | * 11 0 110 1 0011 1100 .111 1101 < we want | |
144 | */ | |
145 | .align 2 | |
146 | .type v7_crval, #object | |
147 | v7_crval: | |
148 | crval clear=0x0120c302, mmuset=0x30c23c7d, ucset=0x00c01c7c | |
149 | ||
150 | .previous |