]>
Commit | Line | Data |
---|---|---|
bbe88886 CM |
1 | /* |
2 | * linux/arch/arm/mm/proc-v7.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This is the "shell" of the ARMv7 processor support. | |
11 | */ | |
12 | #include <linux/linkage.h> | |
13 | #include <asm/assembler.h> | |
14 | #include <asm/asm-offsets.h> | |
15 | #include <asm/elf.h> | |
16 | #include <asm/pgtable-hwdef.h> | |
17 | #include <asm/pgtable.h> | |
18 | ||
19 | #include "proc-macros.S" | |
20 | ||
21 | #define TTB_C (1 << 0) | |
22 | #define TTB_S (1 << 1) | |
23 | #define TTB_RGN_OC_WT (2 << 3) | |
24 | #define TTB_RGN_OC_WB (3 << 3) | |
25 | ||
26 | ENTRY(cpu_v7_proc_init) | |
27 | mov pc, lr | |
93ed3970 | 28 | ENDPROC(cpu_v7_proc_init) |
bbe88886 CM |
29 | |
30 | ENTRY(cpu_v7_proc_fin) | |
31 | mov pc, lr | |
93ed3970 | 32 | ENDPROC(cpu_v7_proc_fin) |
bbe88886 CM |
33 | |
34 | /* | |
35 | * cpu_v7_reset(loc) | |
36 | * | |
37 | * Perform a soft reset of the system. Put the CPU into the | |
38 | * same state as it would be if it had been reset, and branch | |
39 | * to what would be the reset vector. | |
40 | * | |
41 | * - loc - location to jump to for soft reset | |
42 | * | |
43 | * It is assumed that: | |
44 | */ | |
45 | .align 5 | |
46 | ENTRY(cpu_v7_reset) | |
47 | mov pc, r0 | |
93ed3970 | 48 | ENDPROC(cpu_v7_reset) |
bbe88886 CM |
49 | |
50 | /* | |
51 | * cpu_v7_do_idle() | |
52 | * | |
53 | * Idle the processor (eg, wait for interrupt). | |
54 | * | |
55 | * IRQs are already disabled. | |
56 | */ | |
57 | ENTRY(cpu_v7_do_idle) | |
58 | .long 0xe320f003 @ ARM V7 WFI instruction | |
59 | mov pc, lr | |
93ed3970 | 60 | ENDPROC(cpu_v7_do_idle) |
bbe88886 CM |
61 | |
62 | ENTRY(cpu_v7_dcache_clean_area) | |
63 | #ifndef TLB_CAN_READ_FROM_L1_CACHE | |
64 | dcache_line_size r2, r3 | |
65 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
66 | add r0, r0, r2 | |
67 | subs r1, r1, r2 | |
68 | bhi 1b | |
69 | dsb | |
70 | #endif | |
71 | mov pc, lr | |
93ed3970 | 72 | ENDPROC(cpu_v7_dcache_clean_area) |
bbe88886 CM |
73 | |
74 | /* | |
75 | * cpu_v7_switch_mm(pgd_phys, tsk) | |
76 | * | |
77 | * Set the translation table base pointer to be pgd_phys | |
78 | * | |
79 | * - pgd_phys - physical address of new TTB | |
80 | * | |
81 | * It is assumed that: | |
82 | * - we are not using split page tables | |
83 | */ | |
84 | ENTRY(cpu_v7_switch_mm) | |
2eb8c82b | 85 | #ifdef CONFIG_MMU |
bbe88886 CM |
86 | mov r2, #0 |
87 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | |
88 | orr r0, r0, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB | |
89 | mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID | |
90 | isb | |
91 | 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | |
92 | isb | |
93 | mcr p15, 0, r1, c13, c0, 1 @ set context ID | |
94 | isb | |
2eb8c82b | 95 | #endif |
bbe88886 | 96 | mov pc, lr |
93ed3970 | 97 | ENDPROC(cpu_v7_switch_mm) |
bbe88886 CM |
98 | |
99 | /* | |
100 | * cpu_v7_set_pte_ext(ptep, pte) | |
101 | * | |
102 | * Set a level 2 translation table entry. | |
103 | * | |
104 | * - ptep - pointer to level 2 translation table entry | |
105 | * (hardware version is stored at -1024 bytes) | |
106 | * - pte - PTE value to store | |
107 | * - ext - value for extended PTE bits | |
108 | * | |
109 | * Permissions: | |
110 | * YUWD APX AP1 AP0 SVC User | |
111 | * 0xxx 0 0 0 no acc no acc | |
112 | * 100x 1 0 1 r/o no acc | |
113 | * 10x0 1 0 1 r/o no acc | |
114 | * 1011 0 0 1 r/w no acc | |
115 | * 110x 0 1 0 r/w r/o | |
116 | * 11x0 0 1 0 r/w r/o | |
117 | * 1111 0 1 1 r/w r/w | |
118 | */ | |
119 | ENTRY(cpu_v7_set_pte_ext) | |
2eb8c82b | 120 | #ifdef CONFIG_MMU |
bbe88886 CM |
121 | str r1, [r0], #-2048 @ linux version |
122 | ||
123 | bic r3, r1, #0x000003f0 | |
124 | bic r3, r3, #0x00000003 | |
125 | orr r3, r3, r2 | |
126 | orr r3, r3, #PTE_EXT_AP0 | 2 | |
127 | ||
128 | tst r1, #L_PTE_WRITE | |
129 | tstne r1, #L_PTE_DIRTY | |
130 | orreq r3, r3, #PTE_EXT_APX | |
131 | ||
132 | tst r1, #L_PTE_USER | |
133 | orrne r3, r3, #PTE_EXT_AP1 | |
134 | tstne r3, #PTE_EXT_APX | |
135 | bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 | |
136 | ||
137 | tst r1, #L_PTE_YOUNG | |
138 | biceq r3, r3, #PTE_EXT_APX | PTE_EXT_AP_MASK | |
139 | ||
140 | tst r1, #L_PTE_EXEC | |
141 | orreq r3, r3, #PTE_EXT_XN | |
142 | ||
143 | tst r1, #L_PTE_PRESENT | |
144 | moveq r3, #0 | |
145 | ||
146 | str r3, [r0] | |
147 | mcr p15, 0, r0, c7, c10, 1 @ flush_pte | |
2eb8c82b | 148 | #endif |
bbe88886 | 149 | mov pc, lr |
93ed3970 | 150 | ENDPROC(cpu_v7_set_pte_ext) |
bbe88886 CM |
151 | |
152 | cpu_v7_name: | |
153 | .ascii "ARMv7 Processor" | |
154 | .align | |
155 | ||
156 | .section ".text.init", #alloc, #execinstr | |
157 | ||
158 | /* | |
159 | * __v7_setup | |
160 | * | |
161 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | |
162 | * on. Return in r0 the new CP15 C1 control register setting. | |
163 | * | |
164 | * We automatically detect if we have a Harvard cache, and use the | |
165 | * Harvard cache control instructions insead of the unified cache | |
166 | * control instructions. | |
167 | * | |
168 | * This should be able to cover all ARMv7 cores. | |
169 | * | |
170 | * It is assumed that: | |
171 | * - cache type register is implemented | |
172 | */ | |
173 | __v7_setup: | |
174 | adr r12, __v7_setup_stack @ the local stack | |
175 | stmia r12, {r0-r5, r7, r9, r11, lr} | |
176 | bl v7_flush_dcache_all | |
177 | ldmia r12, {r0-r5, r7, r9, r11, lr} | |
178 | mov r10, #0 | |
179 | #ifdef HARVARD_CACHE | |
180 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate | |
181 | #endif | |
182 | dsb | |
2eb8c82b | 183 | #ifdef CONFIG_MMU |
bbe88886 CM |
184 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
185 | mcr p15, 0, r10, c2, c0, 2 @ TTB control register | |
186 | orr r4, r4, #TTB_RGN_OC_WB @ mark PTWs outer cacheable, WB | |
187 | mcr p15, 0, r4, c2, c0, 0 @ load TTB0 | |
188 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 | |
189 | mov r10, #0x1f @ domains 0, 1 = manager | |
190 | mcr p15, 0, r10, c3, c0, 0 @ load domain access register | |
2eb8c82b CM |
191 | #endif |
192 | adr r5, v7_crval | |
193 | ldmia r5, {r5, r6} | |
194 | mrc p15, 0, r0, c1, c0, 0 @ read control register | |
195 | bic r0, r0, r5 @ clear bits them | |
196 | orr r0, r0, r6 @ set them | |
bbe88886 | 197 | mov pc, lr @ return to head.S:__ret |
93ed3970 | 198 | ENDPROC(__v7_setup) |
bbe88886 CM |
199 | |
200 | /* | |
201 | * V X F I D LR | |
202 | * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM | |
203 | * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced | |
204 | * 0 110 0011 1.00 .111 1101 < we want | |
205 | */ | |
2eb8c82b CM |
206 | .type v7_crval, #object |
207 | v7_crval: | |
208 | crval clear=0x0120c302, mmuset=0x00c0387d, ucset=0x00c0187c | |
bbe88886 CM |
209 | |
210 | __v7_setup_stack: | |
211 | .space 4 * 11 @ 11 registers | |
212 | ||
213 | .type v7_processor_functions, #object | |
214 | ENTRY(v7_processor_functions) | |
215 | .word v7_early_abort | |
4a1fd556 | 216 | .word pabort_ifar |
bbe88886 CM |
217 | .word cpu_v7_proc_init |
218 | .word cpu_v7_proc_fin | |
219 | .word cpu_v7_reset | |
220 | .word cpu_v7_do_idle | |
221 | .word cpu_v7_dcache_clean_area | |
222 | .word cpu_v7_switch_mm | |
223 | .word cpu_v7_set_pte_ext | |
224 | .size v7_processor_functions, . - v7_processor_functions | |
225 | ||
226 | .type cpu_arch_name, #object | |
227 | cpu_arch_name: | |
228 | .asciz "armv7" | |
229 | .size cpu_arch_name, . - cpu_arch_name | |
230 | ||
231 | .type cpu_elf_name, #object | |
232 | cpu_elf_name: | |
233 | .asciz "v7" | |
234 | .size cpu_elf_name, . - cpu_elf_name | |
235 | .align | |
236 | ||
237 | .section ".proc.info.init", #alloc, #execinstr | |
238 | ||
239 | /* | |
240 | * Match any ARMv7 processor core. | |
241 | */ | |
242 | .type __v7_proc_info, #object | |
243 | __v7_proc_info: | |
244 | .long 0x000f0000 @ Required ID value | |
245 | .long 0x000f0000 @ Mask for ID | |
246 | .long PMD_TYPE_SECT | \ | |
247 | PMD_SECT_BUFFERABLE | \ | |
248 | PMD_SECT_CACHEABLE | \ | |
249 | PMD_SECT_AP_WRITE | \ | |
250 | PMD_SECT_AP_READ | |
251 | .long PMD_TYPE_SECT | \ | |
252 | PMD_SECT_XN | \ | |
253 | PMD_SECT_AP_WRITE | \ | |
254 | PMD_SECT_AP_READ | |
255 | b __v7_setup | |
256 | .long cpu_arch_name | |
257 | .long cpu_elf_name | |
258 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP | |
259 | .long cpu_v7_name | |
260 | .long v7_processor_functions | |
2ccdd1e7 | 261 | .long v7wbi_tlb_fns |
bbe88886 CM |
262 | .long v6_user_fns |
263 | .long v7_cache_fns | |
264 | .size __v7_proc_info, . - __v7_proc_info |