[mirror_ubuntu-artful-kernel.git] / arch / arm / mm / proc-v7.S

/*
 *  linux/arch/arm/mm/proc-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#ifdef CONFIG_ARM_LPAE
#include "proc-v7-3level.S"
#else
#include "proc-v7-2level.S"
#endif

ENTRY(cpu_v7_proc_init)
	mov	pc, lr
ENDPROC(cpu_v7_proc_init)

ENTRY(cpu_v7_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr
ENDPROC(cpu_v7_proc_fin)

/*
 *	cpu_v7_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 *
 *	This code must be executed using a flat identity mapping with
 *      caches disabled.
 */
	.align	5
	.pushsection	.idmap.text, "ax"
ENTRY(cpu_v7_reset)
	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x1			@ ...............m
 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
	isb
	bx	r0
ENDPROC(cpu_v7_reset)
	.popsection

/*
 *	cpu_v7_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	mov	pc, lr
ENDPROC(cpu_v7_do_idle)

ENTRY(cpu_v7_dcache_clean_area)
	ALT_SMP(mov	pc, lr)			@ MP extensions imply L1 PTW
	ALT_UP(W(nop))
	dcache_line_size r2, r3
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	1b
	dsb
	mov	pc, lr
ENDPROC(cpu_v7_dcache_clean_area)

	string	cpu_v7_name, "ARMv7 Processor"
	.align

/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl	cpu_v7_suspend_size
.equ	cpu_v7_suspend_size, 4 * 8
#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v7_do_suspend)
	stmfd	sp!, {r4 - r10, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	stmia	r0!, {r4 - r5}
#ifdef CONFIG_MMU
	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
#endif
	mrc	p15, 0, r8, c1, c0, 0	@ Control register
	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
	stmia	r0, {r6 - r11}
	ldmfd	sp!, {r4 - r10, pc}
ENDPROC(cpu_v7_do_suspend)

ENTRY(cpu_v7_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
	ldmia	r0!, {r4 - r5}
	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	ldmia	r0, {r6 - r11}
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
#ifndef CONFIG_ARM_LPAE
	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
#endif
	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
	ldr	r4, =PRRR		@ PRRR
	ldr	r5, =NMRR		@ NMRR
	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
#endif	/* CONFIG_MMU */
	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
	teq	r4, r9			@ Is it already set?
	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
	isb
	dsb
	mov	r0, r8			@ control register
	b	cpu_resume_mmu
ENDPROC(cpu_v7_do_resume)
#endif

	__CPUINIT

/*
 *	__v7_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	This should be able to cover all ARMv7 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v7_ca5mp_setup:
__v7_ca9mp_setup:
	mov	r10, #(1 << 0)			@ TLB ops broadcasting
	b	1f
__v7_ca7mp_setup:
__v7_ca15mp_setup:
	mov	r10, #0
1:
#ifdef CONFIG_SMP
	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
	mcreq	p15, 0, r0, c1, c0, 1
#endif
	b	__v7_setup

__v7_pj4b_setup:
#ifdef CONFIG_CPU_PJ4B

/* Auxiliary Debug Modes Control 1 Register */
#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */

/* Auxiliary Debug Modes Control 2 Register */
#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
			    PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)

/* Auxiliary Functional Modes Control Register 0 */
#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */

/* Auxiliary Debug Modes Control 0 Register */
#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */

	/* Auxiliary Debug Modes Control 1 Register */
	mrc	p15, 1,	r0, c15, c1, 1
	orr     r0, r0, #PJ4B_CLEAN_LINE
	orr     r0, r0, #PJ4B_BCK_OFF_STREX
	orr     r0, r0, #PJ4B_INTER_PARITY
	bic	r0, r0, #PJ4B_STATIC_BP
	mcr	p15, 1,	r0, c15, c1, 1

	/* Auxiliary Debug Modes Control 2 Register */
	mrc	p15, 1,	r0, c15, c1, 2
	bic	r0, r0, #PJ4B_FAST_LDR
	orr	r0, r0, #PJ4B_AUX_DBG_CTRL2
	mcr	p15, 1,	r0, c15, c1, 2

	/* Auxiliary Functional Modes Control Register 0 */
	mrc	p15, 1,	r0, c15, c2, 0
#ifdef CONFIG_SMP
	orr	r0, r0, #PJ4B_SMP_CFB
#endif
	orr	r0, r0, #PJ4B_L1_PAR_CHK
	orr	r0, r0, #PJ4B_BROADCAST_CACHE
	mcr	p15, 1,	r0, c15, c2, 0

	/* Auxiliary Debug Modes Control 0 Register */
	mrc	p15, 1,	r0, c15, c1, 0
	orr	r0, r0, #PJ4B_WFI_WFE
	mcr	p15, 1,	r0, c15, c1, 0

#endif /* CONFIG_CPU_PJ4B */

__v7_setup:
	adr	r12, __v7_setup_stack		@ the local stack
	stmia	r12, {r0-r5, r7, r9, r11, lr}
	bl      v7_flush_dcache_louis
	ldmia	r12, {r0-r5, r7, r9, r11, lr}

	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
	and	r10, r0, #0xff000000		@ ARM?
	teq	r10, #0x41000000
	bne	3f
	and	r5, r0, #0x00f00000		@ variant
	and	r6, r0, #0x0000000f		@ revision
	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
	ubfx	r0, r0, #4, #12			@ primary part number

	/* Cortex-A8 Errata */
	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
	teq	r0, r10
	bne	2f
#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)

	teq	r5, #0x00100000			@ only present in r1p*
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_458693
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_460075
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
	tsteq	r10, #1 << 22
	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
#endif
	b	3f

	/* Cortex-A9 Errata */
2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
	teq	r0, r10
	bne	3f
#ifdef CONFIG_ARM_ERRATA_742230
	cmp	r6, #0x22			@ only present up to r2p2
	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrle	r10, r10, #1 << 4		@ set bit #4
	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_742231
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 12		@ set bit #12
	orreq	r10, r10, #1 << 22		@ set bit #22
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
	teq	r5, #0x00200000			@ only present in r2p*
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 6		@ set bit #6
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0
	ALT_UP_B(1f)
	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrlt	r10, r10, #1 << 11		@ set bit #11
	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
1:
#endif

3:	mov	r10, #0
	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
	dsb
#ifdef CONFIG_MMU
	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
	v7_ttb_setup r10, r4, r8, r5		@ TTBCR, TTBRx setup
	ldr	r5, =PRRR			@ PRRR
	ldr	r6, =NMRR			@ NMRR
	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
#endif
#ifndef CONFIG_ARM_THUMBEE
	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
	and	r0, r0, #(0xf << 12)		@ ThumbEE enabled field
	teq	r0, #(1 << 12)			@ check if ThumbEE is present
	bne	1f
	mov	r5, #0
	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0
	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR
	orr	r0, r0, #1			@ set the 1st bit in order to
	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access
1:
#endif
	adr	r5, v7_crval
	ldmia	r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8
	orr	r6, r6, #1 << 25		@ big-endian page tables
#endif
#ifdef CONFIG_SWP_EMULATE
	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
#endif
   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
	mov	pc, lr				@ return to head.S:__ret
ENDPROC(__v7_setup)

	.align	2
__v7_setup_stack:
	.space	4 * 11				@ 11 registers

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1

	.section ".rodata"

	string	cpu_arch_name, "armv7"
	string	cpu_elf_name, "v7"
	.align

	.section ".proc.info.init", #alloc, #execinstr

	/*
	 * Standard v7 proc info content
	 */
.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
			PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
	.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
	W(b)	\initfunc
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
		HWCAP_EDSP | HWCAP_TLS | \hwcaps
	.long	cpu_v7_name
	.long	v7_processor_functions
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
.endm

#ifndef CONFIG_ARM_LPAE
	/*
	 * ARM Ltd. Cortex A5 processor.
	 */
	.type   __v7_ca5mp_proc_info, #object
__v7_ca5mp_proc_info:
	.long	0x410fc050
	.long	0xff0ffff0
	__v7_proc __v7_ca5mp_setup
	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info

	/*
	 * ARM Ltd. Cortex A9 processor.
	 */
	.type   __v7_ca9mp_proc_info, #object
__v7_ca9mp_proc_info:
	.long	0x410fc090
	.long	0xff0ffff0
	__v7_proc __v7_ca9mp_setup
	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info

#endif	/* CONFIG_ARM_LPAE */

	/*
	 * Marvell PJ4B processor.
	 */
	.type   __v7_pj4b_proc_info, #object
__v7_pj4b_proc_info:
	.long	0x562f5840
	.long	0xfffffff0
	__v7_proc __v7_pj4b_setup
	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info

	/*
	 * ARM Ltd. Cortex A7 processor.
	 */
	.type	__v7_ca7mp_proc_info, #object
__v7_ca7mp_proc_info:
	.long	0x410fc070
	.long	0xff0ffff0
	__v7_proc __v7_ca7mp_setup
	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info

	/*
	 * ARM Ltd. Cortex A15 processor.
	 */
	.type	__v7_ca15mp_proc_info, #object
__v7_ca15mp_proc_info:
	.long	0x410fc0f0
	.long	0xff0ffff0
	__v7_proc __v7_ca15mp_setup
	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info

	/*
	 * Qualcomm Inc. Krait processors.
	 */
	.type	__krait_proc_info, #object
__krait_proc_info:
	.long	0x510f0400		@ Required ID value
	.long	0xff0ffc00		@ Mask for ID
	/*
	 * Some Krait processors don't indicate support for SDIV and UDIV
	 * instructions in the ARM instruction set, even though they actually
	 * do support them.
	 */
	__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
	.size	__krait_proc_info, . - __krait_proc_info

	/*
	 * Match any ARMv7 processor core.
	 */
	.type	__v7_proc_info, #object
__v7_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
	__v7_proc __v7_setup
	.size	__v7_proc_info, . - __v7_proc_info
Commit	Line	Data
bbe88886 CM	1	/*
	2	* linux/arch/arm/mm/proc-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This is the "shell" of the ARMv7 processor support.
	11	*/
991da17e	12	#include <linux/init.h>
bbe88886 CM	13	#include <linux/linkage.h>
	14	#include <asm/assembler.h>
	15	#include <asm/asm-offsets.h>
5ec9407d	16	#include <asm/hwcap.h>
bbe88886 CM	17	#include <asm/pgtable-hwdef.h>
	18	#include <asm/pgtable.h>
	19
	20	#include "proc-macros.S"
	21
1b6ba46b CM	22	#ifdef CONFIG_ARM_LPAE
	23	#include "proc-v7-3level.S"
	24	#else
8d2cd3a3	25	#include "proc-v7-2level.S"
1b6ba46b	26	#endif
73b63efa	27
bbe88886 CM	28	ENTRY(cpu_v7_proc_init)
bbe88886 CM	29	mov pc, lr
93ed3970	30	ENDPROC(cpu_v7_proc_init)
bbe88886 CM	31
bbe88886 CM	32	ENTRY(cpu_v7_proc_fin)
1f667c69 TL	33	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	34	bic r0, r0, #0x1000 @ ...i............
	35	bic r0, r0, #0x0006 @ .............ca.
	36	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	37	mov pc, lr
93ed3970	38	ENDPROC(cpu_v7_proc_fin)
bbe88886 CM	39
	40	/*
	41	* cpu_v7_reset(loc)
	42	*
	43	* Perform a soft reset of the system. Put the CPU into the
	44	* same state as it would be if it had been reset, and branch
	45	* to what would be the reset vector.
	46	*
	47	* - loc - location to jump to for soft reset
f4daf06f WD	48	*
	49	* This code must be executed using a flat identity mapping with
	50	* caches disabled.
bbe88886 CM	51	*/
bbe88886 CM	52	.align 5
1a4baafa	53	.pushsection .idmap.text, "ax"
bbe88886	54	ENTRY(cpu_v7_reset)
f4daf06f WD	55	mrc p15, 0, r1, c1, c0, 0 @ ctrl register
f4daf06f WD	56	bic r1, r1, #0x1 @ ...............m
0f81bb6b	57	THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
f4daf06f WD	58	mcr p15, 0, r1, c1, c0, 0 @ disable MMU
f4daf06f WD	59	isb
153cd8e8	60	bx r0
93ed3970	61	ENDPROC(cpu_v7_reset)
1a4baafa	62	.popsection
bbe88886 CM	63
	64	/*
	65	* cpu_v7_do_idle()
	66	*
	67	* Idle the processor (eg, wait for interrupt).
	68	*
	69	* IRQs are already disabled.
	70	*/
	71	ENTRY(cpu_v7_do_idle)
8553cb67	72	dsb @ WFI may enter a low-power mode
000b5025	73	wfi
bbe88886	74	mov pc, lr
93ed3970	75	ENDPROC(cpu_v7_do_idle)
bbe88886 CM	76
bbe88886 CM	77	ENTRY(cpu_v7_dcache_clean_area)
ae8a8b95 WD	78	ALT_SMP(mov pc, lr) @ MP extensions imply L1 PTW
ae8a8b95 WD	79	ALT_UP(W(nop))
bbe88886 CM	80	dcache_line_size r2, r3
	81	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	82	add r0, r0, r2
	83	subs r1, r1, r2
	84	bhi 1b
	85	dsb
bbe88886	86	mov pc, lr
93ed3970	87	ENDPROC(cpu_v7_dcache_clean_area)
bbe88886	88
78a8f3c3	89	string cpu_v7_name, "ARMv7 Processor"
bbe88886 CM	90	.align
bbe88886 CM	91
f6b0fa02 RK	92	/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
f6b0fa02 RK	93	.globl cpu_v7_suspend_size
1b6ba46b	94	.equ cpu_v7_suspend_size, 4 * 8
15e0d9e3	95	#ifdef CONFIG_ARM_CPU_SUSPEND
f6b0fa02	96	ENTRY(cpu_v7_do_suspend)
de8e71ca	97	stmfd sp!, {r4 - r10, lr}
f6b0fa02	98	mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
1aede681 RK	99	mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
1aede681 RK	100	stmia r0!, {r4 - r5}
aa1aadc3	101	#ifdef CONFIG_MMU
f6b0fa02	102	mrc p15, 0, r6, c3, c0, 0 @ Domain ID
de8e71ca	103	mrc p15, 0, r7, c2, c0, 1 @ TTB 1
1b6ba46b	104	mrc p15, 0, r11, c2, c0, 2 @ TTB control register
aa1aadc3	105	#endif
de8e71ca RK	106	mrc p15, 0, r8, c1, c0, 0 @ Control register
	107	mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
	108	mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
1b6ba46b	109	stmia r0, {r6 - r11}
de8e71ca	110	ldmfd sp!, {r4 - r10, pc}
f6b0fa02 RK	111	ENDPROC(cpu_v7_do_suspend)
	112
	113	ENTRY(cpu_v7_do_resume)
	114	mov ip, #0
f6b0fa02	115	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
1aede681 RK	116	mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
1aede681 RK	117	ldmia r0!, {r4 - r5}
f6b0fa02	118	mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
1aede681	119	mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
1b6ba46b	120	ldmia r0, {r6 - r11}
aa1aadc3 WD	121	#ifdef CONFIG_MMU
aa1aadc3 WD	122	mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
f6b0fa02	123	mcr p15, 0, r6, c3, c0, 0 @ Domain ID
1b6ba46b	124	#ifndef CONFIG_ARM_LPAE
de8e71ca RK	125	ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
de8e71ca RK	126	ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
1b6ba46b	127	#endif
de8e71ca RK	128	mcr p15, 0, r1, c2, c0, 0 @ TTB 0
de8e71ca RK	129	mcr p15, 0, r7, c2, c0, 1 @ TTB 1
1b6ba46b	130	mcr p15, 0, r11, c2, c0, 2 @ TTB control register
f6b0fa02 RK	131	ldr r4, =PRRR @ PRRR
	132	ldr r5, =NMRR @ NMRR
	133	mcr p15, 0, r4, c10, c2, 0 @ write PRRR
	134	mcr p15, 0, r5, c10, c2, 1 @ write NMRR
aa1aadc3 WD	135	#endif /* CONFIG_MMU */
	136	mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
	137	teq r4, r9 @ Is it already set?
	138	mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
	139	mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
f6b0fa02	140	isb
f35235a3	141	dsb
de8e71ca	142	mov r0, r8 @ control register
f6b0fa02 RK	143	b cpu_resume_mmu
f6b0fa02 RK	144	ENDPROC(cpu_v7_do_resume)
f6b0fa02 RK	145	#endif
f6b0fa02 RK	146
5085f3ff	147	__CPUINIT
bbe88886 CM	148
	149	/*
	150	* __v7_setup
	151	*
	152	* Initialise TLB, Caches, and MMU state ready to switch the MMU
	153	* on. Return in r0 the new CP15 C1 control register setting.
	154	*
bbe88886 CM	155	* This should be able to cover all ARMv7 cores.
	156	*
	157	* It is assumed that:
	158	* - cache type register is implemented
	159	*/
15eb169b	160	__v7_ca5mp_setup:
14eff181	161	__v7_ca9mp_setup:
7665d9d2 WD	162	mov r10, #(1 << 0) @ TLB ops broadcasting
7665d9d2 WD	163	b 1f
b4244738	164	__v7_ca7mp_setup:
7665d9d2 WD	165	__v7_ca15mp_setup:
	166	mov r10, #0
	167	1:
73b63efa	168	#ifdef CONFIG_SMP
f00ec48f RK	169	ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
f00ec48f RK	170	ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
1b3a02eb	171	tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
7665d9d2 WD	172	orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
	173	orreq r0, r0, r10 @ Enable CPU-specific SMP bits
	174	mcreq p15, 0, r0, c1, c0, 1
73b63efa	175	#endif
d106de38	176	b __v7_setup
de490193 GC	177
	178	__v7_pj4b_setup:
	179	#ifdef CONFIG_CPU_PJ4B
	180
	181	/* Auxiliary Debug Modes Control 1 Register */
	182	#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
	183	#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
	184	#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
	185	#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
	186
	187	/* Auxiliary Debug Modes Control 2 Register */
	188	#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
	189	#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
	190	#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
	191	#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
	192	#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
	193	#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA \| PJ4B_CWF \|\
	194	PJ4B_OUTSDNG_NC \| PJ4B_L1_REP_RR)
	195
	196	/* Auxiliary Functional Modes Control Register 0 */
	197	#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
	198	#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
	199	#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
	200
	201	/* Auxiliary Debug Modes Control 0 Register */
	202	#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
	203
	204	/* Auxiliary Debug Modes Control 1 Register */
	205	mrc p15, 1, r0, c15, c1, 1
	206	orr r0, r0, #PJ4B_CLEAN_LINE
	207	orr r0, r0, #PJ4B_BCK_OFF_STREX
	208	orr r0, r0, #PJ4B_INTER_PARITY
	209	bic r0, r0, #PJ4B_STATIC_BP
	210	mcr p15, 1, r0, c15, c1, 1
	211
	212	/* Auxiliary Debug Modes Control 2 Register */
	213	mrc p15, 1, r0, c15, c1, 2
	214	bic r0, r0, #PJ4B_FAST_LDR
	215	orr r0, r0, #PJ4B_AUX_DBG_CTRL2
	216	mcr p15, 1, r0, c15, c1, 2
	217
	218	/* Auxiliary Functional Modes Control Register 0 */
	219	mrc p15, 1, r0, c15, c2, 0
	220	#ifdef CONFIG_SMP
	221	orr r0, r0, #PJ4B_SMP_CFB
	222	#endif
	223	orr r0, r0, #PJ4B_L1_PAR_CHK
	224	orr r0, r0, #PJ4B_BROADCAST_CACHE
	225	mcr p15, 1, r0, c15, c2, 0
	226
	227	/* Auxiliary Debug Modes Control 0 Register */
	228	mrc p15, 1, r0, c15, c1, 0
	229	orr r0, r0, #PJ4B_WFI_WFE
	230	mcr p15, 1, r0, c15, c1, 0
	231
	232	#endif /* CONFIG_CPU_PJ4B */
	233
14eff181	234	__v7_setup:
bbe88886 CM	235	adr r12, __v7_setup_stack @ the local stack
bbe88886 CM	236	stmia r12, {r0-r5, r7, r9, r11, lr}
6323fa22	237	bl v7_flush_dcache_louis
bbe88886	238	ldmia r12, {r0-r5, r7, r9, r11, lr}
1946d6ef RK	239
	240	mrc p15, 0, r0, c0, c0, 0 @ read main ID register
	241	and r10, r0, #0xff000000 @ ARM?
	242	teq r10, #0x41000000
9f05027c	243	bne 3f
1946d6ef RK	244	and r5, r0, #0x00f00000 @ variant
1946d6ef RK	245	and r6, r0, #0x0000000f @ revision
6491848d WD	246	orr r6, r6, r5, lsr #20-4 @ combine variant and revision
6491848d WD	247	ubfx r0, r0, #4, #12 @ primary part number
1946d6ef	248
6491848d WD	249	/* Cortex-A8 Errata */
	250	ldr r10, =0x00000c08 @ Cortex-A8 primary part number
	251	teq r0, r10
	252	bne 2f
62e4d357 RH	253	#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
62e4d357 RH	254
1946d6ef RK	255	teq r5, #0x00100000 @ only present in r1p*
	256	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	257	orreq r10, r10, #(1 << 6) @ set IBE to 1
	258	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
855c551f CM	259	#endif
855c551f CM	260	#ifdef CONFIG_ARM_ERRATA_458693
6491848d	261	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	262	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	263	orreq r10, r10, #(1 << 5) @ set L1NEON to 1
	264	orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
	265	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
0516e464 CM	266	#endif
0516e464 CM	267	#ifdef CONFIG_ARM_ERRATA_460075
6491848d	268	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	269	mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
	270	tsteq r10, #1 << 22
	271	orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
	272	mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
7ce236fc	273	#endif
9f05027c WD	274	b 3f
	275
	276	/* Cortex-A9 Errata */
	277	2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
	278	teq r0, r10
	279	bne 3f
	280	#ifdef CONFIG_ARM_ERRATA_742230
	281	cmp r6, #0x22 @ only present up to r2p2
	282	mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
	283	orrle r10, r10, #1 << 4 @ set bit #4
	284	mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
	285	#endif
a672e99b WD	286	#ifdef CONFIG_ARM_ERRATA_742231
	287	teq r6, #0x20 @ present in r2p0
	288	teqne r6, #0x21 @ present in r2p1
	289	teqne r6, #0x22 @ present in r2p2
	290	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	291	orreq r10, r10, #1 << 12 @ set bit #12
	292	orreq r10, r10, #1 << 22 @ set bit #22
	293	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	294	#endif
475d92fc	295	#ifdef CONFIG_ARM_ERRATA_743622
efbc74ac	296	teq r5, #0x00200000 @ only present in r2p*
475d92fc WD	297	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	298	orreq r10, r10, #1 << 6 @ set bit #6
	299	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	300	#endif
ba90c516 DM	301	#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
	302	ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
	303	ALT_UP_B(1f)
9a27c27c WD	304	mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
	305	orrlt r10, r10, #1 << 11 @ set bit #11
	306	mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
ba90c516	307	1:
9a27c27c	308	#endif
1946d6ef	309
9f05027c	310	3: mov r10, #0
bbe88886	311	mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
bbe88886	312	dsb
2eb8c82b	313	#ifdef CONFIG_MMU
bbe88886	314	mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
8d2cd3a3	315	v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
f6b0fa02 RK	316	ldr r5, =PRRR @ PRRR
f6b0fa02 RK	317	ldr r6, =NMRR @ NMRR
3f69c0c1 RK	318	mcr p15, 0, r5, c10, c2, 0 @ write PRRR
3f69c0c1 RK	319	mcr p15, 0, r6, c10, c2, 1 @ write NMRR
078c0454 JA	320	#endif
	321	#ifndef CONFIG_ARM_THUMBEE
	322	mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
	323	and r0, r0, #(0xf << 12) @ ThumbEE enabled field
	324	teq r0, #(1 << 12) @ check if ThumbEE is present
	325	bne 1f
	326	mov r5, #0
	327	mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
	328	mrc p14, 6, r0, c0, c0, 0 @ load TEECR
	329	orr r0, r0, #1 @ set the 1st bit in order to
	330	mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
	331	1:
bdaaaec3	332	#endif
2eb8c82b CM	333	adr r5, v7_crval
2eb8c82b CM	334	ldmia r5, {r5, r6}
26584853 CM	335	#ifdef CONFIG_CPU_ENDIAN_BE8
26584853 CM	336	orr r6, r6, #1 << 25 @ big-endian page tables
64d2dc38 LL	337	#endif
	338	#ifdef CONFIG_SWP_EMULATE
	339	orr r5, r5, #(1 << 10) @ set SW bit in "clear"
	340	bic r6, r6, #(1 << 10) @ clear it in "mmuset"
26584853	341	#endif
2eb8c82b CM	342	mrc p15, 0, r0, c1, c0, 0 @ read control register
	343	bic r0, r0, r5 @ clear bits them
	344	orr r0, r0, r6 @ set them
347c8b70	345	THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
bbe88886	346	mov pc, lr @ return to head.S:__ret
93ed3970	347	ENDPROC(__v7_setup)
bbe88886	348
8d2cd3a3	349	.align 2
bbe88886 CM	350	__v7_setup_stack:
	351	.space 4 * 11 @ 11 registers
	352
5085f3ff RK	353	__INITDATA
5085f3ff RK	354
78a8f3c3 DM	355	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
78a8f3c3 DM	356	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
bbe88886	357
5085f3ff RK	358	.section ".rodata"
5085f3ff RK	359
78a8f3c3 DM	360	string cpu_arch_name, "armv7"
78a8f3c3 DM	361	string cpu_elf_name, "v7"
bbe88886 CM	362	.align
	363
	364	.section ".proc.info.init", #alloc, #execinstr
	365
dc939cd8 PM	366	/*
	367	* Standard v7 proc info content
	368	*/
	369	.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
	370	ALT_SMP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_SECT_AP_READ \| \
1b6ba46b	371	PMD_SECT_AF \| PMD_FLAGS_SMP \| \mm_mmuflags)
dc939cd8	372	ALT_UP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_SECT_AP_READ \| \
1b6ba46b CM	373	PMD_SECT_AF \| PMD_FLAGS_UP \| \mm_mmuflags)
	374	.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| \
	375	PMD_SECT_AP_READ \| PMD_SECT_AF \| \io_mmuflags
dc939cd8	376	W(b) \initfunc
14eff181 DW	377	.long cpu_arch_name
14eff181 DW	378	.long cpu_elf_name
dc939cd8 PM	379	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB \| HWCAP_FAST_MULT \| \
dc939cd8 PM	380	HWCAP_EDSP \| HWCAP_TLS \| \hwcaps
14eff181 DW	381	.long cpu_v7_name
	382	.long v7_processor_functions
	383	.long v7wbi_tlb_fns
	384	.long v6_user_fns
	385	.long v7_cache_fns
dc939cd8 PM	386	.endm
dc939cd8 PM	387
1b6ba46b	388	#ifndef CONFIG_ARM_LPAE
15eb169b PM	389	/*
	390	* ARM Ltd. Cortex A5 processor.
	391	*/
	392	.type __v7_ca5mp_proc_info, #object
	393	__v7_ca5mp_proc_info:
	394	.long 0x410fc050
	395	.long 0xff0ffff0
	396	__v7_proc __v7_ca5mp_setup
	397	.size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
	398
dc939cd8 PM	399	/*
	400	* ARM Ltd. Cortex A9 processor.
	401	*/
	402	.type __v7_ca9mp_proc_info, #object
	403	__v7_ca9mp_proc_info:
	404	.long 0x410fc090
	405	.long 0xff0ffff0
	406	__v7_proc __v7_ca9mp_setup
14eff181	407	.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
de490193	408
b361d61d GC	409	#endif /* CONFIG_ARM_LPAE */
b361d61d GC	410
de490193 GC	411	/*
	412	* Marvell PJ4B processor.
	413	*/
	414	.type __v7_pj4b_proc_info, #object
	415	__v7_pj4b_proc_info:
	416	.long 0x562f5840
	417	.long 0xfffffff0
	418	__v7_proc __v7_pj4b_setup
	419	.size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
14eff181	420
868dbf90 WD	421	/*
	422	* ARM Ltd. Cortex A7 processor.
	423	*/
	424	.type __v7_ca7mp_proc_info, #object
	425	__v7_ca7mp_proc_info:
	426	.long 0x410fc070
	427	.long 0xff0ffff0
8164f7af	428	__v7_proc __v7_ca7mp_setup
868dbf90 WD	429	.size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
868dbf90 WD	430
7665d9d2 WD	431	/*
	432	* ARM Ltd. Cortex A15 processor.
	433	*/
	434	.type __v7_ca15mp_proc_info, #object
	435	__v7_ca15mp_proc_info:
	436	.long 0x410fc0f0
	437	.long 0xff0ffff0
8164f7af	438	__v7_proc __v7_ca15mp_setup
7665d9d2 WD	439	.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
7665d9d2 WD	440
120ecfaf SM	441	/*
	442	* Qualcomm Inc. Krait processors.
	443	*/
	444	.type __krait_proc_info, #object
	445	__krait_proc_info:
	446	.long 0x510f0400 @ Required ID value
	447	.long 0xff0ffc00 @ Mask for ID
	448	/*
	449	* Some Krait processors don't indicate support for SDIV and UDIV
	450	* instructions in the ARM instruction set, even though they actually
	451	* do support them.
	452	*/
	453	__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
	454	.size __krait_proc_info, . - __krait_proc_info
	455
bbe88886 CM	456	/*
	457	* Match any ARMv7 processor core.
	458	*/
	459	.type __v7_proc_info, #object
	460	__v7_proc_info:
	461	.long 0x000f0000 @ Required ID value
	462	.long 0x000f0000 @ Mask for ID
dc939cd8	463	__v7_proc __v7_setup
bbe88886	464	.size __v7_proc_info, . - __v7_proc_info