[mirror_ubuntu-artful-kernel.git] / arch / arm / mm / proc-v7.S

/*
 *  linux/arch/arm/mm/proc-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#define TTB_S		(1 << 1)
#define TTB_RGN_NC	(0 << 3)
#define TTB_RGN_OC_WBWA	(1 << 3)
#define TTB_RGN_OC_WT	(2 << 3)
#define TTB_RGN_OC_WB	(3 << 3)
#define TTB_NOS		(1 << 5)
#define TTB_IRGN_NC	((0 << 0) | (0 << 6))
#define TTB_IRGN_WBWA	((0 << 0) | (1 << 6))
#define TTB_IRGN_WT	((1 << 0) | (0 << 6))
#define TTB_IRGN_WB	((1 << 0) | (1 << 6))

/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
#define PMD_FLAGS_UP	PMD_SECT_WB

/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S

ENTRY(cpu_v7_proc_init)
	mov	pc, lr
ENDPROC(cpu_v7_proc_init)

ENTRY(cpu_v7_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr
ENDPROC(cpu_v7_proc_fin)

/*
 *	cpu_v7_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_v7_reset)
	mov	pc, r0
ENDPROC(cpu_v7_reset)

/*
 *	cpu_v7_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	mov	pc, lr
ENDPROC(cpu_v7_do_idle)

ENTRY(cpu_v7_dcache_clean_area)
#ifndef TLB_CAN_READ_FROM_L1_CACHE
	dcache_line_size r2, r3
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	1b
	dsb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_dcache_clean_area)

/*
 *	cpu_v7_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys
 *
 *	- pgd_phys - physical address of new TTB
 *
 *	It is assumed that:
 *	- we are not using split page tables
 */
ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
	mov	r2, #0
	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
#ifdef CONFIG_ARM_ERRATA_430973
	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
#endif
	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
	isb
1:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
	isb
	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
	isb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_switch_mm)

/*
 *	cpu_v7_set_pte_ext(ptep, pte)
 *
 *	Set a level 2 translation table entry.
 *
 *	- ptep  - pointer to level 2 translation table entry
 *		  (hardware version is stored at +2048 bytes)
 *	- pte   - PTE value to store
 *	- ext	- value for extended PTE bits
 */
ENTRY(cpu_v7_set_pte_ext)
#ifdef CONFIG_MMU
	str	r1, [r0]			@ linux version

	bic	r3, r1, #0x000003f0
	bic	r3, r3, #PTE_TYPE_MASK
	orr	r3, r3, r2
	orr	r3, r3, #PTE_EXT_AP0 | 2

	tst	r1, #1 << 4
	orrne	r3, r3, #PTE_EXT_TEX(1)

	eor	r1, r1, #L_PTE_DIRTY
	tst	r1, #L_PTE_RDONLY | L_PTE_DIRTY
	orrne	r3, r3, #PTE_EXT_APX

	tst	r1, #L_PTE_USER
	orrne	r3, r3, #PTE_EXT_AP1
#ifdef CONFIG_CPU_USE_DOMAINS
	@ allow kernel read/write access to read-only user pages
	tstne	r3, #PTE_EXT_APX
	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
#endif

	tst	r1, #L_PTE_XN
	orrne	r3, r3, #PTE_EXT_XN

	tst	r1, #L_PTE_YOUNG
	tstne	r1, #L_PTE_PRESENT
	moveq	r3, #0

 ARM(	str	r3, [r0, #2048]! )
 THUMB(	add	r0, r0, #2048 )
 THUMB(	str	r3, [r0] )
	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
#endif
	mov	pc, lr
ENDPROC(cpu_v7_set_pte_ext)

cpu_v7_name:
	.ascii	"ARMv7 Processor"
	.align

	__CPUINIT

/*
 *	__v7_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	We automatically detect if we have a Harvard cache, and use the
 *	Harvard cache control instructions insead of the unified cache
 *	control instructions.
 *
 *	This should be able to cover all ARMv7 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v7_ca9mp_setup:
#ifdef CONFIG_SMP
	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
	orreq	r0, r0, #(1 << 6) | (1 << 0)	@ Enable SMP/nAMP mode and
	mcreq	p15, 0, r0, c1, c0, 1		@ TLB ops broadcasting
#endif
__v7_setup:
	adr	r12, __v7_setup_stack		@ the local stack
	stmia	r12, {r0-r5, r7, r9, r11, lr}
	bl	v7_flush_dcache_all
	ldmia	r12, {r0-r5, r7, r9, r11, lr}

	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
	and	r10, r0, #0xff000000		@ ARM?
	teq	r10, #0x41000000
	bne	3f
	and	r5, r0, #0x00f00000		@ variant
	and	r6, r0, #0x0000000f		@ revision
	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
	ubfx	r0, r0, #4, #12			@ primary part number

	/* Cortex-A8 Errata */
	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
	teq	r0, r10
	bne	2f
#ifdef CONFIG_ARM_ERRATA_430973
	teq	r5, #0x00100000			@ only present in r1p*
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_458693
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_460075
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
	tsteq	r10, #1 << 22
	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
#endif
	b	3f

	/* Cortex-A9 Errata */
2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
	teq	r0, r10
	bne	3f
#ifdef CONFIG_ARM_ERRATA_742230
	cmp	r6, #0x22			@ only present up to r2p2
	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrle	r10, r10, #1 << 4		@ set bit #4
	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_742231
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 12		@ set bit #12
	orreq	r10, r10, #1 << 22		@ set bit #22
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 6		@ set bit #6
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif

3:	mov	r10, #0
#ifdef HARVARD_CACHE
	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
#endif
	dsb
#ifdef CONFIG_MMU
	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
	ALT_SMP(orr	r4, r4, #TTB_FLAGS_SMP)
	ALT_UP(orr	r4, r4, #TTB_FLAGS_UP)
	mcr	p15, 0, r4, c2, c0, 1		@ load TTB1
	/*
	 * Memory region attributes with SCTLR.TRE=1
	 *
	 *   n = TEX[0],C,B
	 *   TR = PRRR[2n+1:2n]		- memory type
	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
	 *
	 *			n	TR	IR	OR
	 *   UNCACHED		000	00
	 *   BUFFERABLE		001	10	00	00
	 *   WRITETHROUGH	010	10	10	10
	 *   WRITEBACK		011	10	11	11
	 *   reserved		110
	 *   WRITEALLOC		111	10	01	01
	 *   DEV_SHARED		100	01
	 *   DEV_NONSHARED	100	01
	 *   DEV_WC		001	10
	 *   DEV_CACHED		011	10
	 *
	 * Other attributes:
	 *
	 *   DS0 = PRRR[16] = 0		- device shareable property
	 *   DS1 = PRRR[17] = 1		- device shareable property
	 *   NS0 = PRRR[18] = 0		- normal shareable property
	 *   NS1 = PRRR[19] = 1		- normal shareable property
	 *   NOS = PRRR[24+n] = 1	- not outer shareable
	 */
	ldr	r5, =0xff0a81a8			@ PRRR
	ldr	r6, =0x40e040e0			@ NMRR
	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
#endif
	adr	r5, v7_crval
	ldmia	r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8
	orr	r6, r6, #1 << 25		@ big-endian page tables
#endif
#ifdef CONFIG_SWP_EMULATE
	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
#endif
   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
	mov	pc, lr				@ return to head.S:__ret
ENDPROC(__v7_setup)

	/*   AT
	 *  TFR   EV X F   I D LR    S
	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
	 *    1    0 110       0011 1100 .111 1101 < we want
	 */
	.type	v7_crval, #object
v7_crval:
	crval	clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c

__v7_setup_stack:
	.space	4 * 11				@ 11 registers

	__INITDATA

	.type	v7_processor_functions, #object
ENTRY(v7_processor_functions)
	.word	v7_early_abort
	.word	v7_pabort
	.word	cpu_v7_proc_init
	.word	cpu_v7_proc_fin
	.word	cpu_v7_reset
	.word	cpu_v7_do_idle
	.word	cpu_v7_dcache_clean_area
	.word	cpu_v7_switch_mm
	.word	cpu_v7_set_pte_ext
	.size	v7_processor_functions, . - v7_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv7"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v7"
	.size	cpu_elf_name, . - cpu_elf_name
	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type   __v7_ca9mp_proc_info, #object
__v7_ca9mp_proc_info:
	.long	0x410fc090		@ Required ID value
	.long	0xff0ffff0		@ Mask for ID
	ALT_SMP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_SMP)
	ALT_UP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_UP)
	.long   PMD_TYPE_SECT | \
		PMD_SECT_XN | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	W(b)	__v7_ca9mp_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
	.long	cpu_v7_name
	.long	v7_processor_functions
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info

	/*
	 * Match any ARMv7 processor core.
	 */
	.type	__v7_proc_info, #object
__v7_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
	ALT_SMP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_SMP)
	ALT_UP(.long \
		PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \
		PMD_FLAGS_UP)
	.long   PMD_TYPE_SECT | \
		PMD_SECT_XN | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	W(b)	__v7_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
	.long	cpu_v7_name
	.long	v7_processor_functions
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
	.size	__v7_proc_info, . - __v7_proc_info
Commit	Line	Data
bbe88886 CM	1	/*
	2	* linux/arch/arm/mm/proc-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This is the "shell" of the ARMv7 processor support.
	11	*/
991da17e	12	#include <linux/init.h>
bbe88886 CM	13	#include <linux/linkage.h>
	14	#include <asm/assembler.h>
	15	#include <asm/asm-offsets.h>
5ec9407d	16	#include <asm/hwcap.h>
bbe88886 CM	17	#include <asm/pgtable-hwdef.h>
	18	#include <asm/pgtable.h>
	19
	20	#include "proc-macros.S"
	21
bbe88886	22	#define TTB_S (1 << 1)
73b63efa JC	23	#define TTB_RGN_NC (0 << 3)
73b63efa JC	24	#define TTB_RGN_OC_WBWA (1 << 3)
bbe88886 CM	25	#define TTB_RGN_OC_WT (2 << 3)
bbe88886 CM	26	#define TTB_RGN_OC_WB (3 << 3)
ba3c0263 TT	27	#define TTB_NOS (1 << 5)
	28	#define TTB_IRGN_NC ((0 << 0) \| (0 << 6))
	29	#define TTB_IRGN_WBWA ((0 << 0) \| (1 << 6))
	30	#define TTB_IRGN_WT ((1 << 0) \| (0 << 6))
	31	#define TTB_IRGN_WB ((1 << 0) \| (1 << 6))
bbe88886	32
ba3c0263	33	/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
f00ec48f RK	34	#define TTB_FLAGS_UP TTB_IRGN_WB\|TTB_RGN_OC_WB
	35	#define PMD_FLAGS_UP PMD_SECT_WB
	36
ba3c0263	37	/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
f00ec48f RK	38	#define TTB_FLAGS_SMP TTB_IRGN_WBWA\|TTB_S\|TTB_NOS\|TTB_RGN_OC_WBWA
f00ec48f RK	39	#define PMD_FLAGS_SMP PMD_SECT_WBWA\|PMD_SECT_S
73b63efa	40
bbe88886 CM	41	ENTRY(cpu_v7_proc_init)
bbe88886 CM	42	mov pc, lr
93ed3970	43	ENDPROC(cpu_v7_proc_init)
bbe88886 CM	44
bbe88886 CM	45	ENTRY(cpu_v7_proc_fin)
1f667c69 TL	46	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	47	bic r0, r0, #0x1000 @ ...i............
	48	bic r0, r0, #0x0006 @ .............ca.
	49	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	50	mov pc, lr
93ed3970	51	ENDPROC(cpu_v7_proc_fin)
bbe88886 CM	52
	53	/*
	54	* cpu_v7_reset(loc)
	55	*
	56	* Perform a soft reset of the system. Put the CPU into the
	57	* same state as it would be if it had been reset, and branch
	58	* to what would be the reset vector.
	59	*
	60	* - loc - location to jump to for soft reset
bbe88886 CM	61	*/
	62	.align 5
	63	ENTRY(cpu_v7_reset)
	64	mov pc, r0
93ed3970	65	ENDPROC(cpu_v7_reset)
bbe88886 CM	66
	67	/*
	68	* cpu_v7_do_idle()
	69	*
	70	* Idle the processor (eg, wait for interrupt).
	71	*
	72	* IRQs are already disabled.
	73	*/
	74	ENTRY(cpu_v7_do_idle)
8553cb67	75	dsb @ WFI may enter a low-power mode
000b5025	76	wfi
bbe88886	77	mov pc, lr
93ed3970	78	ENDPROC(cpu_v7_do_idle)
bbe88886 CM	79
	80	ENTRY(cpu_v7_dcache_clean_area)
	81	#ifndef TLB_CAN_READ_FROM_L1_CACHE
	82	dcache_line_size r2, r3
	83	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	84	add r0, r0, r2
	85	subs r1, r1, r2
	86	bhi 1b
	87	dsb
	88	#endif
	89	mov pc, lr
93ed3970	90	ENDPROC(cpu_v7_dcache_clean_area)
bbe88886 CM	91
	92	/*
	93	* cpu_v7_switch_mm(pgd_phys, tsk)
	94	*
	95	* Set the translation table base pointer to be pgd_phys
	96	*
	97	* - pgd_phys - physical address of new TTB
	98	*
	99	* It is assumed that:
	100	* - we are not using split page tables
	101	*/
	102	ENTRY(cpu_v7_switch_mm)
2eb8c82b	103	#ifdef CONFIG_MMU
bbe88886 CM	104	mov r2, #0
bbe88886 CM	105	ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
f00ec48f RK	106	ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
f00ec48f RK	107	ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
7ce236fc CM	108	#ifdef CONFIG_ARM_ERRATA_430973
	109	mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
	110	#endif
bbe88886 CM	111	mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
	112	isb
	113	1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
	114	isb
	115	mcr p15, 0, r1, c13, c0, 1 @ set context ID
	116	isb
2eb8c82b	117	#endif
bbe88886	118	mov pc, lr
93ed3970	119	ENDPROC(cpu_v7_switch_mm)
bbe88886 CM	120
	121	/*
	122	* cpu_v7_set_pte_ext(ptep, pte)
	123	*
	124	* Set a level 2 translation table entry.
	125	*
	126	* - ptep - pointer to level 2 translation table entry
d30e45ee	127	* (hardware version is stored at +2048 bytes)
bbe88886 CM	128	* - pte - PTE value to store
bbe88886 CM	129	* - ext - value for extended PTE bits
bbe88886 CM	130	*/
bbe88886 CM	131	ENTRY(cpu_v7_set_pte_ext)
2eb8c82b	132	#ifdef CONFIG_MMU
d30e45ee	133	str r1, [r0] @ linux version
bbe88886 CM	134
bbe88886 CM	135	bic r3, r1, #0x000003f0
3f69c0c1	136	bic r3, r3, #PTE_TYPE_MASK
bbe88886 CM	137	orr r3, r3, r2
	138	orr r3, r3, #PTE_EXT_AP0 \| 2
	139
b1cce6b1	140	tst r1, #1 << 4
3f69c0c1 RK	141	orrne r3, r3, #PTE_EXT_TEX(1)
3f69c0c1 RK	142
36bb94ba RK	143	eor r1, r1, #L_PTE_DIRTY
	144	tst r1, #L_PTE_RDONLY \| L_PTE_DIRTY
	145	orrne r3, r3, #PTE_EXT_APX
bbe88886 CM	146
	147	tst r1, #L_PTE_USER
	148	orrne r3, r3, #PTE_EXT_AP1
247055aa CM	149	#ifdef CONFIG_CPU_USE_DOMAINS
247055aa CM	150	@ allow kernel read/write access to read-only user pages
bbe88886 CM	151	tstne r3, #PTE_EXT_APX
bbe88886 CM	152	bicne r3, r3, #PTE_EXT_APX \| PTE_EXT_AP0
247055aa	153	#endif
bbe88886	154
9522d7e4 RK	155	tst r1, #L_PTE_XN
9522d7e4 RK	156	orrne r3, r3, #PTE_EXT_XN
bbe88886	157
3f69c0c1 RK	158	tst r1, #L_PTE_YOUNG
3f69c0c1 RK	159	tstne r1, #L_PTE_PRESENT
bbe88886 CM	160	moveq r3, #0
bbe88886 CM	161
874d5d3c DM	162	ARM( str r3, [r0, #2048]! )
	163	THUMB( add r0, r0, #2048 )
	164	THUMB( str r3, [r0] )
bbe88886	165	mcr p15, 0, r0, c7, c10, 1 @ flush_pte
2eb8c82b	166	#endif
bbe88886	167	mov pc, lr
93ed3970	168	ENDPROC(cpu_v7_set_pte_ext)
bbe88886 CM	169
	170	cpu_v7_name:
	171	.ascii "ARMv7 Processor"
	172	.align
	173
5085f3ff	174	__CPUINIT
bbe88886 CM	175
	176	/*
	177	* __v7_setup
	178	*
	179	* Initialise TLB, Caches, and MMU state ready to switch the MMU
	180	* on. Return in r0 the new CP15 C1 control register setting.
	181	*
	182	* We automatically detect if we have a Harvard cache, and use the
	183	* Harvard cache control instructions insead of the unified cache
	184	* control instructions.
	185	*
	186	* This should be able to cover all ARMv7 cores.
	187	*
	188	* It is assumed that:
	189	* - cache type register is implemented
	190	*/
14eff181	191	__v7_ca9mp_setup:
73b63efa	192	#ifdef CONFIG_SMP
f00ec48f RK	193	ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
f00ec48f RK	194	ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
1b3a02eb TT	195	tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
	196	orreq r0, r0, #(1 << 6) \| (1 << 0) @ Enable SMP/nAMP mode and
	197	mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting
73b63efa	198	#endif
14eff181	199	__v7_setup:
bbe88886 CM	200	adr r12, __v7_setup_stack @ the local stack
	201	stmia r12, {r0-r5, r7, r9, r11, lr}
	202	bl v7_flush_dcache_all
	203	ldmia r12, {r0-r5, r7, r9, r11, lr}
1946d6ef RK	204
	205	mrc p15, 0, r0, c0, c0, 0 @ read main ID register
	206	and r10, r0, #0xff000000 @ ARM?
	207	teq r10, #0x41000000
9f05027c	208	bne 3f
1946d6ef RK	209	and r5, r0, #0x00f00000 @ variant
1946d6ef RK	210	and r6, r0, #0x0000000f @ revision
6491848d WD	211	orr r6, r6, r5, lsr #20-4 @ combine variant and revision
6491848d WD	212	ubfx r0, r0, #4, #12 @ primary part number
1946d6ef	213
6491848d WD	214	/* Cortex-A8 Errata */
	215	ldr r10, =0x00000c08 @ Cortex-A8 primary part number
	216	teq r0, r10
	217	bne 2f
7ce236fc	218	#ifdef CONFIG_ARM_ERRATA_430973
1946d6ef RK	219	teq r5, #0x00100000 @ only present in r1p*
	220	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	221	orreq r10, r10, #(1 << 6) @ set IBE to 1
	222	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
855c551f CM	223	#endif
855c551f CM	224	#ifdef CONFIG_ARM_ERRATA_458693
6491848d	225	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	226	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	227	orreq r10, r10, #(1 << 5) @ set L1NEON to 1
	228	orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
	229	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
0516e464 CM	230	#endif
0516e464 CM	231	#ifdef CONFIG_ARM_ERRATA_460075
6491848d	232	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	233	mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
	234	tsteq r10, #1 << 22
	235	orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
	236	mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
7ce236fc	237	#endif
9f05027c WD	238	b 3f
	239
	240	/* Cortex-A9 Errata */
	241	2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
	242	teq r0, r10
	243	bne 3f
	244	#ifdef CONFIG_ARM_ERRATA_742230
	245	cmp r6, #0x22 @ only present up to r2p2
	246	mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
	247	orrle r10, r10, #1 << 4 @ set bit #4
	248	mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
	249	#endif
a672e99b WD	250	#ifdef CONFIG_ARM_ERRATA_742231
	251	teq r6, #0x20 @ present in r2p0
	252	teqne r6, #0x21 @ present in r2p1
	253	teqne r6, #0x22 @ present in r2p2
	254	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	255	orreq r10, r10, #1 << 12 @ set bit #12
	256	orreq r10, r10, #1 << 22 @ set bit #22
	257	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	258	#endif
475d92fc WD	259	#ifdef CONFIG_ARM_ERRATA_743622
	260	teq r6, #0x20 @ present in r2p0
	261	teqne r6, #0x21 @ present in r2p1
	262	teqne r6, #0x22 @ present in r2p2
	263	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	264	orreq r10, r10, #1 << 6 @ set bit #6
	265	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	266	#endif
1946d6ef	267
9f05027c	268	3: mov r10, #0
bbe88886 CM	269	#ifdef HARVARD_CACHE
	270	mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
	271	#endif
	272	dsb
2eb8c82b	273	#ifdef CONFIG_MMU
bbe88886 CM	274	mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
bbe88886 CM	275	mcr p15, 0, r10, c2, c0, 2 @ TTB control register
f00ec48f RK	276	ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
f00ec48f RK	277	ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
bbe88886	278	mcr p15, 0, r4, c2, c0, 1 @ load TTB1
23d1c515 CM	279	/*
	280	* Memory region attributes with SCTLR.TRE=1
	281	*
	282	* n = TEX[0],C,B
	283	* TR = PRRR[2n+1:2n] - memory type
	284	* IR = NMRR[2n+1:2n] - inner cacheable property
	285	* OR = NMRR[2n+17:2n+16] - outer cacheable property
	286	*
	287	* n TR IR OR
	288	* UNCACHED 000 00
	289	* BUFFERABLE 001 10 00 00
	290	* WRITETHROUGH 010 10 10 10
	291	* WRITEBACK 011 10 11 11
	292	* reserved 110
	293	* WRITEALLOC 111 10 01 01
	294	* DEV_SHARED 100 01
	295	* DEV_NONSHARED 100 01
	296	* DEV_WC 001 10
	297	* DEV_CACHED 011 10
	298	*
	299	* Other attributes:
	300	*
	301	* DS0 = PRRR[16] = 0 - device shareable property
	302	* DS1 = PRRR[17] = 1 - device shareable property
	303	* NS0 = PRRR[18] = 0 - normal shareable property
	304	* NS1 = PRRR[19] = 1 - normal shareable property
	305	* NOS = PRRR[24+n] = 1 - not outer shareable
	306	*/
	307	ldr r5, =0xff0a81a8 @ PRRR
	308	ldr r6, =0x40e040e0 @ NMRR
3f69c0c1 RK	309	mcr p15, 0, r5, c10, c2, 0 @ write PRRR
3f69c0c1 RK	310	mcr p15, 0, r6, c10, c2, 1 @ write NMRR
bdaaaec3	311	#endif
2eb8c82b CM	312	adr r5, v7_crval
2eb8c82b CM	313	ldmia r5, {r5, r6}
26584853 CM	314	#ifdef CONFIG_CPU_ENDIAN_BE8
26584853 CM	315	orr r6, r6, #1 << 25 @ big-endian page tables
64d2dc38 LL	316	#endif
	317	#ifdef CONFIG_SWP_EMULATE
	318	orr r5, r5, #(1 << 10) @ set SW bit in "clear"
	319	bic r6, r6, #(1 << 10) @ clear it in "mmuset"
26584853	320	#endif
2eb8c82b CM	321	mrc p15, 0, r0, c1, c0, 0 @ read control register
	322	bic r0, r0, r5 @ clear bits them
	323	orr r0, r0, r6 @ set them
347c8b70	324	THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
bbe88886	325	mov pc, lr @ return to head.S:__ret
93ed3970	326	ENDPROC(__v7_setup)
bbe88886	327
b1cce6b1	328	/* AT
213fb2a8 CM	329	* TFR EV X F I D LR S
213fb2a8 CM	330	* .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
b1cce6b1	331	* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
213fb2a8	332	* 1 0 110 0011 1100 .111 1101 < we want
bbe88886	333	*/
2eb8c82b CM	334	.type v7_crval, #object
2eb8c82b CM	335	v7_crval:
213fb2a8	336	crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
bbe88886 CM	337
	338	__v7_setup_stack:
	339	.space 4 * 11 @ 11 registers
	340
5085f3ff RK	341	__INITDATA
5085f3ff RK	342
bbe88886 CM	343	.type v7_processor_functions, #object
	344	ENTRY(v7_processor_functions)
	345	.word v7_early_abort
4fb28474	346	.word v7_pabort
bbe88886 CM	347	.word cpu_v7_proc_init
	348	.word cpu_v7_proc_fin
	349	.word cpu_v7_reset
	350	.word cpu_v7_do_idle
	351	.word cpu_v7_dcache_clean_area
	352	.word cpu_v7_switch_mm
	353	.word cpu_v7_set_pte_ext
	354	.size v7_processor_functions, . - v7_processor_functions
	355
5085f3ff RK	356	.section ".rodata"
5085f3ff RK	357
bbe88886 CM	358	.type cpu_arch_name, #object
	359	cpu_arch_name:
	360	.asciz "armv7"
	361	.size cpu_arch_name, . - cpu_arch_name
	362
	363	.type cpu_elf_name, #object
	364	cpu_elf_name:
	365	.asciz "v7"
	366	.size cpu_elf_name, . - cpu_elf_name
	367	.align
	368
	369	.section ".proc.info.init", #alloc, #execinstr
	370
14eff181 DW	371	.type __v7_ca9mp_proc_info, #object
	372	__v7_ca9mp_proc_info:
	373	.long 0x410fc090 @ Required ID value
	374	.long 0xff0ffff0 @ Mask for ID
f00ec48f RK	375	ALT_SMP(.long \
	376	PMD_TYPE_SECT \| \
	377	PMD_SECT_AP_WRITE \| \
	378	PMD_SECT_AP_READ \| \
	379	PMD_FLAGS_SMP)
	380	ALT_UP(.long \
	381	PMD_TYPE_SECT \| \
14eff181 DW	382	PMD_SECT_AP_WRITE \| \
14eff181 DW	383	PMD_SECT_AP_READ \| \
f00ec48f	384	PMD_FLAGS_UP)
14eff181 DW	385	.long PMD_TYPE_SECT \| \
	386	PMD_SECT_XN \| \
	387	PMD_SECT_AP_WRITE \| \
	388	PMD_SECT_AP_READ
6323875d	389	W(b) __v7_ca9mp_setup
14eff181 DW	390	.long cpu_arch_name
14eff181 DW	391	.long cpu_elf_name
c0bb5862	392	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_TLS
14eff181 DW	393	.long cpu_v7_name
	394	.long v7_processor_functions
	395	.long v7wbi_tlb_fns
	396	.long v6_user_fns
	397	.long v7_cache_fns
	398	.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
	399
bbe88886 CM	400	/*
	401	* Match any ARMv7 processor core.
	402	*/
	403	.type __v7_proc_info, #object
	404	__v7_proc_info:
	405	.long 0x000f0000 @ Required ID value
	406	.long 0x000f0000 @ Mask for ID
f00ec48f RK	407	ALT_SMP(.long \
	408	PMD_TYPE_SECT \| \
	409	PMD_SECT_AP_WRITE \| \
	410	PMD_SECT_AP_READ \| \
	411	PMD_FLAGS_SMP)
	412	ALT_UP(.long \
	413	PMD_TYPE_SECT \| \
bbe88886	414	PMD_SECT_AP_WRITE \| \
4b46d641	415	PMD_SECT_AP_READ \| \
f00ec48f	416	PMD_FLAGS_UP)
bbe88886 CM	417	.long PMD_TYPE_SECT \| \
	418	PMD_SECT_XN \| \
	419	PMD_SECT_AP_WRITE \| \
	420	PMD_SECT_AP_READ
6323875d	421	W(b) __v7_setup
bbe88886 CM	422	.long cpu_arch_name
bbe88886 CM	423	.long cpu_elf_name
f159f4ed	424	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_TLS
bbe88886 CM	425	.long cpu_v7_name
bbe88886 CM	426	.long v7_processor_functions
2ccdd1e7	427	.long v7wbi_tlb_fns
bbe88886 CM	428	.long v6_user_fns
	429	.long v7_cache_fns
	430	.size __v7_proc_info, . - __v7_proc_info