[mirror_ubuntu-artful-kernel.git] / arch / arm / mm / proc-v7.S

/*
 *  linux/arch/arm/mm/proc-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#define TTB_S		(1 << 1)
#define TTB_RGN_NC	(0 << 3)
#define TTB_RGN_OC_WBWA	(1 << 3)
#define TTB_RGN_OC_WT	(2 << 3)
#define TTB_RGN_OC_WB	(3 << 3)
#define TTB_NOS		(1 << 5)
#define TTB_IRGN_NC	((0 << 0) | (0 << 6))
#define TTB_IRGN_WBWA	((0 << 0) | (1 << 6))
#define TTB_IRGN_WT	((1 << 0) | (0 << 6))
#define TTB_IRGN_WB	((1 << 0) | (1 << 6))

/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
#define TTB_FLAGS_UP	TTB_IRGN_WB|TTB_RGN_OC_WB
#define PMD_FLAGS_UP	PMD_SECT_WB

/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
#define TTB_FLAGS_SMP	TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA
#define PMD_FLAGS_SMP	PMD_SECT_WBWA|PMD_SECT_S

ENTRY(cpu_v7_proc_init)
	mov	pc, lr
ENDPROC(cpu_v7_proc_init)

ENTRY(cpu_v7_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr
ENDPROC(cpu_v7_proc_fin)

/*
 *	cpu_v7_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 *
 *	This code must be executed using a flat identity mapping with
 *      caches disabled.
 */
	.align	5
ENTRY(cpu_v7_reset)
	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x1			@ ...............m
 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
	isb
	mov	pc, r0
ENDPROC(cpu_v7_reset)

/*
 *	cpu_v7_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	mov	pc, lr
ENDPROC(cpu_v7_do_idle)

ENTRY(cpu_v7_dcache_clean_area)
#ifndef TLB_CAN_READ_FROM_L1_CACHE
	dcache_line_size r2, r3
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	1b
	dsb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_dcache_clean_area)

/*
 *	cpu_v7_switch_mm(pgd_phys, tsk)
 *
 *	Set the translation table base pointer to be pgd_phys
 *
 *	- pgd_phys - physical address of new TTB
 *
 *	It is assumed that:
 *	- we are not using split page tables
 */
ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
	mov	r2, #0
	ldr	r1, [r1, #MM_CONTEXT_ID]	@ get mm->context.id
	ALT_SMP(orr	r0, r0, #TTB_FLAGS_SMP)
	ALT_UP(orr	r0, r0, #TTB_FLAGS_UP)
#ifdef CONFIG_ARM_ERRATA_430973
	mcr	p15, 0, r2, c7, c5, 6		@ flush BTAC/BTB
#endif
#ifdef CONFIG_ARM_ERRATA_754322
	dsb
#endif
	mcr	p15, 0, r2, c13, c0, 1		@ set reserved context ID
	isb
1:	mcr	p15, 0, r0, c2, c0, 0		@ set TTB 0
	isb
#ifdef CONFIG_ARM_ERRATA_754322
	dsb
#endif
	mcr	p15, 0, r1, c13, c0, 1		@ set context ID
	isb
#endif
	mov	pc, lr
ENDPROC(cpu_v7_switch_mm)

/*
 *	cpu_v7_set_pte_ext(ptep, pte)
 *
 *	Set a level 2 translation table entry.
 *
 *	- ptep  - pointer to level 2 translation table entry
 *		  (hardware version is stored at +2048 bytes)
 *	- pte   - PTE value to store
 *	- ext	- value for extended PTE bits
 */
ENTRY(cpu_v7_set_pte_ext)
#ifdef CONFIG_MMU
	str	r1, [r0]			@ linux version

	bic	r3, r1, #0x000003f0
	bic	r3, r3, #PTE_TYPE_MASK
	orr	r3, r3, r2
	orr	r3, r3, #PTE_EXT_AP0 | 2

	tst	r1, #1 << 4
	orrne	r3, r3, #PTE_EXT_TEX(1)

	eor	r1, r1, #L_PTE_DIRTY
	tst	r1, #L_PTE_RDONLY | L_PTE_DIRTY
	orrne	r3, r3, #PTE_EXT_APX

	tst	r1, #L_PTE_USER
	orrne	r3, r3, #PTE_EXT_AP1
#ifdef CONFIG_CPU_USE_DOMAINS
	@ allow kernel read/write access to read-only user pages
	tstne	r3, #PTE_EXT_APX
	bicne	r3, r3, #PTE_EXT_APX | PTE_EXT_AP0
#endif

	tst	r1, #L_PTE_XN
	orrne	r3, r3, #PTE_EXT_XN

	tst	r1, #L_PTE_YOUNG
	tstne	r1, #L_PTE_PRESENT
	moveq	r3, #0

 ARM(	str	r3, [r0, #2048]! )
 THUMB(	add	r0, r0, #2048 )
 THUMB(	str	r3, [r0] )
	mcr	p15, 0, r0, c7, c10, 1		@ flush_pte
#endif
	mov	pc, lr
ENDPROC(cpu_v7_set_pte_ext)

	string	cpu_v7_name, "ARMv7 Processor"
	.align

	/*
	 * Memory region attributes with SCTLR.TRE=1
	 *
	 *   n = TEX[0],C,B
	 *   TR = PRRR[2n+1:2n]		- memory type
	 *   IR = NMRR[2n+1:2n]		- inner cacheable property
	 *   OR = NMRR[2n+17:2n+16]	- outer cacheable property
	 *
	 *			n	TR	IR	OR
	 *   UNCACHED		000	00
	 *   BUFFERABLE		001	10	00	00
	 *   WRITETHROUGH	010	10	10	10
	 *   WRITEBACK		011	10	11	11
	 *   reserved		110
	 *   WRITEALLOC		111	10	01	01
	 *   DEV_SHARED		100	01
	 *   DEV_NONSHARED	100	01
	 *   DEV_WC		001	10
	 *   DEV_CACHED		011	10
	 *
	 * Other attributes:
	 *
	 *   DS0 = PRRR[16] = 0		- device shareable property
	 *   DS1 = PRRR[17] = 1		- device shareable property
	 *   NS0 = PRRR[18] = 0		- normal shareable property
	 *   NS1 = PRRR[19] = 1		- normal shareable property
	 *   NOS = PRRR[24+n] = 1	- not outer shareable
	 */
.equ	PRRR,	0xff0a81a8
.equ	NMRR,	0x40e040e0

/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl	cpu_v7_suspend_size
.equ	cpu_v7_suspend_size, 4 * 7
#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v7_do_suspend)
	stmfd	sp!, {r4 - r10, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	stmia	r0!, {r4 - r5}
	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
	mrc	p15, 0, r8, c1, c0, 0	@ Control register
	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
	stmia	r0, {r6 - r10}
	ldmfd	sp!, {r4 - r10, pc}
ENDPROC(cpu_v7_do_suspend)

ENTRY(cpu_v7_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
	ldmia	r0!, {r4 - r5}
	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	ldmia	r0, {r6 - r10}
	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
	mcr	p15, 0, ip, c2, c0, 2	@ TTB control register
	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
	teq	r4, r9			@ Is it already set?
	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
	ldr	r4, =PRRR		@ PRRR
	ldr	r5, =NMRR		@ NMRR
	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
	isb
	dsb
	mov	r0, r8			@ control register
	b	cpu_resume_mmu
ENDPROC(cpu_v7_do_resume)
#endif

	__CPUINIT

/*
 *	__v7_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	We automatically detect if we have a Harvard cache, and use the
 *	Harvard cache control instructions insead of the unified cache
 *	control instructions.
 *
 *	This should be able to cover all ARMv7 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v7_ca5mp_setup:
__v7_ca9mp_setup:
	mov	r10, #(1 << 0)			@ TLB ops broadcasting
	b	1f
__v7_ca15mp_setup:
	mov	r10, #0
1:
#ifdef CONFIG_SMP
	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
	mcreq	p15, 0, r0, c1, c0, 1
#endif
__v7_setup:
	adr	r12, __v7_setup_stack		@ the local stack
	stmia	r12, {r0-r5, r7, r9, r11, lr}
	bl	v7_flush_dcache_all
	ldmia	r12, {r0-r5, r7, r9, r11, lr}

	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
	and	r10, r0, #0xff000000		@ ARM?
	teq	r10, #0x41000000
	bne	3f
	and	r5, r0, #0x00f00000		@ variant
	and	r6, r0, #0x0000000f		@ revision
	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
	ubfx	r0, r0, #4, #12			@ primary part number

	/* Cortex-A8 Errata */
	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
	teq	r0, r10
	bne	2f
#ifdef CONFIG_ARM_ERRATA_430973
	teq	r5, #0x00100000			@ only present in r1p*
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_458693
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_460075
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
	tsteq	r10, #1 << 22
	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
#endif
	b	3f

	/* Cortex-A9 Errata */
2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
	teq	r0, r10
	bne	3f
#ifdef CONFIG_ARM_ERRATA_742230
	cmp	r6, #0x22			@ only present up to r2p2
	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrle	r10, r10, #1 << 4		@ set bit #4
	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_742231
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 12		@ set bit #12
	orreq	r10, r10, #1 << 22		@ set bit #22
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 6		@ set bit #6
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_751472
	cmp	r6, #0x30			@ present prior to r3p0
	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrlt	r10, r10, #1 << 11		@ set bit #11
	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif

3:	mov	r10, #0
#ifdef HARVARD_CACHE
	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
#endif
	dsb
#ifdef CONFIG_MMU
	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
	mcr	p15, 0, r10, c2, c0, 2		@ TTB control register
	ALT_SMP(orr	r4, r4, #TTB_FLAGS_SMP)
	ALT_UP(orr	r4, r4, #TTB_FLAGS_UP)
	ALT_SMP(orr	r8, r8, #TTB_FLAGS_SMP)
	ALT_UP(orr	r8, r8, #TTB_FLAGS_UP)
	mcr	p15, 0, r8, c2, c0, 1		@ load TTB1
	ldr	r5, =PRRR			@ PRRR
	ldr	r6, =NMRR			@ NMRR
	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
#endif
	adr	r5, v7_crval
	ldmia	r5, {r5, r6}
#ifdef CONFIG_CPU_ENDIAN_BE8
	orr	r6, r6, #1 << 25		@ big-endian page tables
#endif
#ifdef CONFIG_SWP_EMULATE
	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
#endif
   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
	mov	pc, lr				@ return to head.S:__ret
ENDPROC(__v7_setup)

	/*   AT
	 *  TFR   EV X F   I D LR    S
	 * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
	 * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
	 *    1    0 110       0011 1100 .111 1101 < we want
	 */
	.type	v7_crval, #object
v7_crval:
	crval	clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c

__v7_setup_stack:
	.space	4 * 11				@ 11 registers

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1

	.section ".rodata"

	string	cpu_arch_name, "armv7"
	string	cpu_elf_name, "v7"
	.align

	.section ".proc.info.init", #alloc, #execinstr

	/*
	 * Standard v7 proc info content
	 */
.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
			PMD_FLAGS_SMP | \mm_mmuflags)
	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
			PMD_FLAGS_UP | \mm_mmuflags)
	.long	PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | \io_mmuflags
	W(b)	\initfunc
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
		HWCAP_EDSP | HWCAP_TLS | \hwcaps
	.long	cpu_v7_name
	.long	v7_processor_functions
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
.endm

	/*
	 * ARM Ltd. Cortex A5 processor.
	 */
	.type   __v7_ca5mp_proc_info, #object
__v7_ca5mp_proc_info:
	.long	0x410fc050
	.long	0xff0ffff0
	__v7_proc __v7_ca5mp_setup
	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info

	/*
	 * ARM Ltd. Cortex A9 processor.
	 */
	.type   __v7_ca9mp_proc_info, #object
__v7_ca9mp_proc_info:
	.long	0x410fc090
	.long	0xff0ffff0
	__v7_proc __v7_ca9mp_setup
	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info

	/*
	 * ARM Ltd. Cortex A15 processor.
	 */
	.type	__v7_ca15mp_proc_info, #object
__v7_ca15mp_proc_info:
	.long	0x410fc0f0
	.long	0xff0ffff0
	__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info

	/*
	 * Match any ARMv7 processor core.
	 */
	.type	__v7_proc_info, #object
__v7_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
	__v7_proc __v7_setup
	.size	__v7_proc_info, . - __v7_proc_info
Commit	Line	Data
bbe88886 CM	1	/*
	2	* linux/arch/arm/mm/proc-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This is the "shell" of the ARMv7 processor support.
	11	*/
991da17e	12	#include <linux/init.h>
bbe88886 CM	13	#include <linux/linkage.h>
	14	#include <asm/assembler.h>
	15	#include <asm/asm-offsets.h>
5ec9407d	16	#include <asm/hwcap.h>
bbe88886 CM	17	#include <asm/pgtable-hwdef.h>
	18	#include <asm/pgtable.h>
	19
	20	#include "proc-macros.S"
	21
bbe88886	22	#define TTB_S (1 << 1)
73b63efa JC	23	#define TTB_RGN_NC (0 << 3)
73b63efa JC	24	#define TTB_RGN_OC_WBWA (1 << 3)
bbe88886 CM	25	#define TTB_RGN_OC_WT (2 << 3)
bbe88886 CM	26	#define TTB_RGN_OC_WB (3 << 3)
ba3c0263 TT	27	#define TTB_NOS (1 << 5)
	28	#define TTB_IRGN_NC ((0 << 0) \| (0 << 6))
	29	#define TTB_IRGN_WBWA ((0 << 0) \| (1 << 6))
	30	#define TTB_IRGN_WT ((1 << 0) \| (0 << 6))
	31	#define TTB_IRGN_WB ((1 << 0) \| (1 << 6))
bbe88886	32
ba3c0263	33	/* PTWs cacheable, inner WB not shareable, outer WB not shareable */
f00ec48f RK	34	#define TTB_FLAGS_UP TTB_IRGN_WB\|TTB_RGN_OC_WB
	35	#define PMD_FLAGS_UP PMD_SECT_WB
	36
ba3c0263	37	/* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */
f00ec48f RK	38	#define TTB_FLAGS_SMP TTB_IRGN_WBWA\|TTB_S\|TTB_NOS\|TTB_RGN_OC_WBWA
f00ec48f RK	39	#define PMD_FLAGS_SMP PMD_SECT_WBWA\|PMD_SECT_S
73b63efa	40
bbe88886 CM	41	ENTRY(cpu_v7_proc_init)
bbe88886 CM	42	mov pc, lr
93ed3970	43	ENDPROC(cpu_v7_proc_init)
bbe88886 CM	44
bbe88886 CM	45	ENTRY(cpu_v7_proc_fin)
1f667c69 TL	46	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	47	bic r0, r0, #0x1000 @ ...i............
	48	bic r0, r0, #0x0006 @ .............ca.
	49	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	50	mov pc, lr
93ed3970	51	ENDPROC(cpu_v7_proc_fin)
bbe88886 CM	52
	53	/*
	54	* cpu_v7_reset(loc)
	55	*
	56	* Perform a soft reset of the system. Put the CPU into the
	57	* same state as it would be if it had been reset, and branch
	58	* to what would be the reset vector.
	59	*
	60	* - loc - location to jump to for soft reset
f4daf06f WD	61	*
	62	* This code must be executed using a flat identity mapping with
	63	* caches disabled.
bbe88886 CM	64	*/
	65	.align 5
	66	ENTRY(cpu_v7_reset)
f4daf06f WD	67	mrc p15, 0, r1, c1, c0, 0 @ ctrl register
f4daf06f WD	68	bic r1, r1, #0x1 @ ...............m
0f81bb6b	69	THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
f4daf06f WD	70	mcr p15, 0, r1, c1, c0, 0 @ disable MMU
f4daf06f WD	71	isb
bbe88886	72	mov pc, r0
93ed3970	73	ENDPROC(cpu_v7_reset)
bbe88886 CM	74
	75	/*
	76	* cpu_v7_do_idle()
	77	*
	78	* Idle the processor (eg, wait for interrupt).
	79	*
	80	* IRQs are already disabled.
	81	*/
	82	ENTRY(cpu_v7_do_idle)
8553cb67	83	dsb @ WFI may enter a low-power mode
000b5025	84	wfi
bbe88886	85	mov pc, lr
93ed3970	86	ENDPROC(cpu_v7_do_idle)
bbe88886 CM	87
	88	ENTRY(cpu_v7_dcache_clean_area)
	89	#ifndef TLB_CAN_READ_FROM_L1_CACHE
	90	dcache_line_size r2, r3
	91	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	92	add r0, r0, r2
	93	subs r1, r1, r2
	94	bhi 1b
	95	dsb
	96	#endif
	97	mov pc, lr
93ed3970	98	ENDPROC(cpu_v7_dcache_clean_area)
bbe88886 CM	99
	100	/*
	101	* cpu_v7_switch_mm(pgd_phys, tsk)
	102	*
	103	* Set the translation table base pointer to be pgd_phys
	104	*
	105	* - pgd_phys - physical address of new TTB
	106	*
	107	* It is assumed that:
	108	* - we are not using split page tables
	109	*/
	110	ENTRY(cpu_v7_switch_mm)
2eb8c82b	111	#ifdef CONFIG_MMU
bbe88886 CM	112	mov r2, #0
bbe88886 CM	113	ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id
f00ec48f RK	114	ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP)
f00ec48f RK	115	ALT_UP(orr r0, r0, #TTB_FLAGS_UP)
7ce236fc CM	116	#ifdef CONFIG_ARM_ERRATA_430973
7ce236fc CM	117	mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
fcbdc5fe	118	#endif
07989b7a RK	119	#ifdef CONFIG_ARM_ERRATA_754322
	120	dsb
	121	#endif
	122	mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID
	123	isb
	124	1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0
bbe88886	125	isb
fcbdc5fe WD	126	#ifdef CONFIG_ARM_ERRATA_754322
	127	dsb
	128	#endif
bbe88886 CM	129	mcr p15, 0, r1, c13, c0, 1 @ set context ID
bbe88886 CM	130	isb
2eb8c82b	131	#endif
bbe88886	132	mov pc, lr
93ed3970	133	ENDPROC(cpu_v7_switch_mm)
bbe88886 CM	134
	135	/*
	136	* cpu_v7_set_pte_ext(ptep, pte)
	137	*
	138	* Set a level 2 translation table entry.
	139	*
	140	* - ptep - pointer to level 2 translation table entry
d30e45ee	141	* (hardware version is stored at +2048 bytes)
bbe88886 CM	142	* - pte - PTE value to store
bbe88886 CM	143	* - ext - value for extended PTE bits
bbe88886 CM	144	*/
bbe88886 CM	145	ENTRY(cpu_v7_set_pte_ext)
2eb8c82b	146	#ifdef CONFIG_MMU
d30e45ee	147	str r1, [r0] @ linux version
bbe88886 CM	148
bbe88886 CM	149	bic r3, r1, #0x000003f0
3f69c0c1	150	bic r3, r3, #PTE_TYPE_MASK
bbe88886 CM	151	orr r3, r3, r2
	152	orr r3, r3, #PTE_EXT_AP0 \| 2
	153
b1cce6b1	154	tst r1, #1 << 4
3f69c0c1 RK	155	orrne r3, r3, #PTE_EXT_TEX(1)
3f69c0c1 RK	156
36bb94ba RK	157	eor r1, r1, #L_PTE_DIRTY
	158	tst r1, #L_PTE_RDONLY \| L_PTE_DIRTY
	159	orrne r3, r3, #PTE_EXT_APX
bbe88886 CM	160
	161	tst r1, #L_PTE_USER
	162	orrne r3, r3, #PTE_EXT_AP1
247055aa CM	163	#ifdef CONFIG_CPU_USE_DOMAINS
247055aa CM	164	@ allow kernel read/write access to read-only user pages
bbe88886 CM	165	tstne r3, #PTE_EXT_APX
bbe88886 CM	166	bicne r3, r3, #PTE_EXT_APX \| PTE_EXT_AP0
247055aa	167	#endif
bbe88886	168
9522d7e4 RK	169	tst r1, #L_PTE_XN
9522d7e4 RK	170	orrne r3, r3, #PTE_EXT_XN
bbe88886	171
3f69c0c1 RK	172	tst r1, #L_PTE_YOUNG
3f69c0c1 RK	173	tstne r1, #L_PTE_PRESENT
bbe88886 CM	174	moveq r3, #0
bbe88886 CM	175
874d5d3c DM	176	ARM( str r3, [r0, #2048]! )
	177	THUMB( add r0, r0, #2048 )
	178	THUMB( str r3, [r0] )
bbe88886	179	mcr p15, 0, r0, c7, c10, 1 @ flush_pte
2eb8c82b	180	#endif
bbe88886	181	mov pc, lr
93ed3970	182	ENDPROC(cpu_v7_set_pte_ext)
bbe88886	183
78a8f3c3	184	string cpu_v7_name, "ARMv7 Processor"
bbe88886 CM	185	.align
bbe88886 CM	186
f6b0fa02 RK	187	/*
	188	* Memory region attributes with SCTLR.TRE=1
	189	*
	190	* n = TEX[0],C,B
	191	* TR = PRRR[2n+1:2n] - memory type
	192	* IR = NMRR[2n+1:2n] - inner cacheable property
	193	* OR = NMRR[2n+17:2n+16] - outer cacheable property
	194	*
	195	* n TR IR OR
	196	* UNCACHED 000 00
	197	* BUFFERABLE 001 10 00 00
	198	* WRITETHROUGH 010 10 10 10
	199	* WRITEBACK 011 10 11 11
	200	* reserved 110
	201	* WRITEALLOC 111 10 01 01
	202	* DEV_SHARED 100 01
	203	* DEV_NONSHARED 100 01
	204	* DEV_WC 001 10
	205	* DEV_CACHED 011 10
	206	*
	207	* Other attributes:
	208	*
	209	* DS0 = PRRR[16] = 0 - device shareable property
	210	* DS1 = PRRR[17] = 1 - device shareable property
	211	* NS0 = PRRR[18] = 0 - normal shareable property
	212	* NS1 = PRRR[19] = 1 - normal shareable property
	213	* NOS = PRRR[24+n] = 1 - not outer shareable
	214	*/
	215	.equ PRRR, 0xff0a81a8
	216	.equ NMRR, 0x40e040e0
	217
	218	/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
	219	.globl cpu_v7_suspend_size
1aede681	220	.equ cpu_v7_suspend_size, 4 * 7
15e0d9e3	221	#ifdef CONFIG_ARM_CPU_SUSPEND
f6b0fa02	222	ENTRY(cpu_v7_do_suspend)
de8e71ca	223	stmfd sp!, {r4 - r10, lr}
f6b0fa02	224	mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
1aede681 RK	225	mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
1aede681 RK	226	stmia r0!, {r4 - r5}
f6b0fa02	227	mrc p15, 0, r6, c3, c0, 0 @ Domain ID
de8e71ca RK	228	mrc p15, 0, r7, c2, c0, 1 @ TTB 1
	229	mrc p15, 0, r8, c1, c0, 0 @ Control register
	230	mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
	231	mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
	232	stmia r0, {r6 - r10}
	233	ldmfd sp!, {r4 - r10, pc}
f6b0fa02 RK	234	ENDPROC(cpu_v7_do_suspend)
	235
	236	ENTRY(cpu_v7_do_resume)
	237	mov ip, #0
	238	mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
	239	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
1aede681 RK	240	mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
1aede681 RK	241	ldmia r0!, {r4 - r5}
f6b0fa02	242	mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
1aede681	243	mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
de8e71ca	244	ldmia r0, {r6 - r10}
f6b0fa02	245	mcr p15, 0, r6, c3, c0, 0 @ Domain ID
de8e71ca RK	246	ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
	247	ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
	248	mcr p15, 0, r1, c2, c0, 0 @ TTB 0
	249	mcr p15, 0, r7, c2, c0, 1 @ TTB 1
f6b0fa02	250	mcr p15, 0, ip, c2, c0, 2 @ TTB control register
25904157	251	mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
de8e71ca RK	252	teq r4, r9 @ Is it already set?
	253	mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
	254	mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
f6b0fa02 RK	255	ldr r4, =PRRR @ PRRR
	256	ldr r5, =NMRR @ NMRR
	257	mcr p15, 0, r4, c10, c2, 0 @ write PRRR
	258	mcr p15, 0, r5, c10, c2, 1 @ write NMRR
	259	isb
f35235a3	260	dsb
de8e71ca	261	mov r0, r8 @ control register
f6b0fa02 RK	262	b cpu_resume_mmu
f6b0fa02 RK	263	ENDPROC(cpu_v7_do_resume)
f6b0fa02 RK	264	#endif
f6b0fa02 RK	265
5085f3ff	266	__CPUINIT
bbe88886 CM	267
	268	/*
	269	* __v7_setup
	270	*
	271	* Initialise TLB, Caches, and MMU state ready to switch the MMU
	272	* on. Return in r0 the new CP15 C1 control register setting.
	273	*
	274	* We automatically detect if we have a Harvard cache, and use the
	275	* Harvard cache control instructions insead of the unified cache
	276	* control instructions.
	277	*
	278	* This should be able to cover all ARMv7 cores.
	279	*
	280	* It is assumed that:
	281	* - cache type register is implemented
	282	*/
15eb169b	283	__v7_ca5mp_setup:
14eff181	284	__v7_ca9mp_setup:
7665d9d2 WD	285	mov r10, #(1 << 0) @ TLB ops broadcasting
	286	b 1f
	287	__v7_ca15mp_setup:
	288	mov r10, #0
	289	1:
73b63efa	290	#ifdef CONFIG_SMP
f00ec48f RK	291	ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
f00ec48f RK	292	ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
1b3a02eb	293	tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
7665d9d2 WD	294	orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
	295	orreq r0, r0, r10 @ Enable CPU-specific SMP bits
	296	mcreq p15, 0, r0, c1, c0, 1
73b63efa	297	#endif
14eff181	298	__v7_setup:
bbe88886 CM	299	adr r12, __v7_setup_stack @ the local stack
	300	stmia r12, {r0-r5, r7, r9, r11, lr}
	301	bl v7_flush_dcache_all
	302	ldmia r12, {r0-r5, r7, r9, r11, lr}
1946d6ef RK	303
	304	mrc p15, 0, r0, c0, c0, 0 @ read main ID register
	305	and r10, r0, #0xff000000 @ ARM?
	306	teq r10, #0x41000000
9f05027c	307	bne 3f
1946d6ef RK	308	and r5, r0, #0x00f00000 @ variant
1946d6ef RK	309	and r6, r0, #0x0000000f @ revision
6491848d WD	310	orr r6, r6, r5, lsr #20-4 @ combine variant and revision
6491848d WD	311	ubfx r0, r0, #4, #12 @ primary part number
1946d6ef	312
6491848d WD	313	/* Cortex-A8 Errata */
	314	ldr r10, =0x00000c08 @ Cortex-A8 primary part number
	315	teq r0, r10
	316	bne 2f
7ce236fc	317	#ifdef CONFIG_ARM_ERRATA_430973
1946d6ef RK	318	teq r5, #0x00100000 @ only present in r1p*
	319	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	320	orreq r10, r10, #(1 << 6) @ set IBE to 1
	321	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
855c551f CM	322	#endif
855c551f CM	323	#ifdef CONFIG_ARM_ERRATA_458693
6491848d	324	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	325	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	326	orreq r10, r10, #(1 << 5) @ set L1NEON to 1
	327	orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
	328	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
0516e464 CM	329	#endif
0516e464 CM	330	#ifdef CONFIG_ARM_ERRATA_460075
6491848d	331	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	332	mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
	333	tsteq r10, #1 << 22
	334	orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
	335	mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
7ce236fc	336	#endif
9f05027c WD	337	b 3f
	338
	339	/* Cortex-A9 Errata */
	340	2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
	341	teq r0, r10
	342	bne 3f
	343	#ifdef CONFIG_ARM_ERRATA_742230
	344	cmp r6, #0x22 @ only present up to r2p2
	345	mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
	346	orrle r10, r10, #1 << 4 @ set bit #4
	347	mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
	348	#endif
a672e99b WD	349	#ifdef CONFIG_ARM_ERRATA_742231
	350	teq r6, #0x20 @ present in r2p0
	351	teqne r6, #0x21 @ present in r2p1
	352	teqne r6, #0x22 @ present in r2p2
	353	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	354	orreq r10, r10, #1 << 12 @ set bit #12
	355	orreq r10, r10, #1 << 22 @ set bit #22
	356	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	357	#endif
475d92fc WD	358	#ifdef CONFIG_ARM_ERRATA_743622
	359	teq r6, #0x20 @ present in r2p0
	360	teqne r6, #0x21 @ present in r2p1
	361	teqne r6, #0x22 @ present in r2p2
	362	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	363	orreq r10, r10, #1 << 6 @ set bit #6
	364	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	365	#endif
9a27c27c WD	366	#ifdef CONFIG_ARM_ERRATA_751472
	367	cmp r6, #0x30 @ present prior to r3p0
	368	mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
	369	orrlt r10, r10, #1 << 11 @ set bit #11
	370	mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
	371	#endif
1946d6ef	372
9f05027c	373	3: mov r10, #0
bbe88886 CM	374	#ifdef HARVARD_CACHE
	375	mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
	376	#endif
	377	dsb
2eb8c82b	378	#ifdef CONFIG_MMU
bbe88886 CM	379	mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
bbe88886 CM	380	mcr p15, 0, r10, c2, c0, 2 @ TTB control register
f00ec48f RK	381	ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP)
f00ec48f RK	382	ALT_UP(orr r4, r4, #TTB_FLAGS_UP)
d427958a CM	383	ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP)
	384	ALT_UP(orr r8, r8, #TTB_FLAGS_UP)
	385	mcr p15, 0, r8, c2, c0, 1 @ load TTB1
f6b0fa02 RK	386	ldr r5, =PRRR @ PRRR
f6b0fa02 RK	387	ldr r6, =NMRR @ NMRR
3f69c0c1 RK	388	mcr p15, 0, r5, c10, c2, 0 @ write PRRR
3f69c0c1 RK	389	mcr p15, 0, r6, c10, c2, 1 @ write NMRR
bdaaaec3	390	#endif
2eb8c82b CM	391	adr r5, v7_crval
2eb8c82b CM	392	ldmia r5, {r5, r6}
26584853 CM	393	#ifdef CONFIG_CPU_ENDIAN_BE8
26584853 CM	394	orr r6, r6, #1 << 25 @ big-endian page tables
64d2dc38 LL	395	#endif
	396	#ifdef CONFIG_SWP_EMULATE
	397	orr r5, r5, #(1 << 10) @ set SW bit in "clear"
	398	bic r6, r6, #(1 << 10) @ clear it in "mmuset"
26584853	399	#endif
2eb8c82b CM	400	mrc p15, 0, r0, c1, c0, 0 @ read control register
	401	bic r0, r0, r5 @ clear bits them
	402	orr r0, r0, r6 @ set them
347c8b70	403	THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
bbe88886	404	mov pc, lr @ return to head.S:__ret
93ed3970	405	ENDPROC(__v7_setup)
bbe88886	406
b1cce6b1	407	/* AT
213fb2a8 CM	408	* TFR EV X F I D LR S
213fb2a8 CM	409	* .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM
b1cce6b1	410	* rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced
213fb2a8	411	* 1 0 110 0011 1100 .111 1101 < we want
bbe88886	412	*/
2eb8c82b CM	413	.type v7_crval, #object
2eb8c82b CM	414	v7_crval:
213fb2a8	415	crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c
bbe88886 CM	416
	417	__v7_setup_stack:
	418	.space 4 * 11 @ 11 registers
	419
5085f3ff RK	420	__INITDATA
5085f3ff RK	421
78a8f3c3 DM	422	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
78a8f3c3 DM	423	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
bbe88886	424
5085f3ff RK	425	.section ".rodata"
5085f3ff RK	426
78a8f3c3 DM	427	string cpu_arch_name, "armv7"
78a8f3c3 DM	428	string cpu_elf_name, "v7"
bbe88886 CM	429	.align
	430
	431	.section ".proc.info.init", #alloc, #execinstr
	432
dc939cd8 PM	433	/*
	434	* Standard v7 proc info content
	435	*/
	436	.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
	437	ALT_SMP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_SECT_AP_READ \| \
	438	PMD_FLAGS_SMP \| \mm_mmuflags)
	439	ALT_UP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_SECT_AP_READ \| \
	440	PMD_FLAGS_UP \| \mm_mmuflags)
	441	.long PMD_TYPE_SECT \| PMD_SECT_XN \| PMD_SECT_AP_WRITE \| \
	442	PMD_SECT_AP_READ \| \io_mmuflags
	443	W(b) \initfunc
14eff181 DW	444	.long cpu_arch_name
14eff181 DW	445	.long cpu_elf_name
dc939cd8 PM	446	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB \| HWCAP_FAST_MULT \| \
dc939cd8 PM	447	HWCAP_EDSP \| HWCAP_TLS \| \hwcaps
14eff181 DW	448	.long cpu_v7_name
	449	.long v7_processor_functions
	450	.long v7wbi_tlb_fns
	451	.long v6_user_fns
	452	.long v7_cache_fns
dc939cd8 PM	453	.endm
dc939cd8 PM	454
15eb169b PM	455	/*
	456	* ARM Ltd. Cortex A5 processor.
	457	*/
	458	.type __v7_ca5mp_proc_info, #object
	459	__v7_ca5mp_proc_info:
	460	.long 0x410fc050
	461	.long 0xff0ffff0
	462	__v7_proc __v7_ca5mp_setup
	463	.size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
	464
dc939cd8 PM	465	/*
	466	* ARM Ltd. Cortex A9 processor.
	467	*/
	468	.type __v7_ca9mp_proc_info, #object
	469	__v7_ca9mp_proc_info:
	470	.long 0x410fc090
	471	.long 0xff0ffff0
	472	__v7_proc __v7_ca9mp_setup
14eff181 DW	473	.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
14eff181 DW	474
7665d9d2 WD	475	/*
	476	* ARM Ltd. Cortex A15 processor.
	477	*/
	478	.type __v7_ca15mp_proc_info, #object
	479	__v7_ca15mp_proc_info:
	480	.long 0x410fc0f0
	481	.long 0xff0ffff0
	482	__v7_proc __v7_ca15mp_setup, hwcaps = HWCAP_IDIV
	483	.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
	484
bbe88886 CM	485	/*
	486	* Match any ARMv7 processor core.
	487	*/
	488	.type __v7_proc_info, #object
	489	__v7_proc_info:
	490	.long 0x000f0000 @ Required ID value
	491	.long 0x000f0000 @ Mask for ID
dc939cd8	492	__v7_proc __v7_setup
bbe88886	493	.size __v7_proc_info, . - __v7_proc_info