[mirror_ubuntu-artful-kernel.git] / arch / arm / mm / proc-v7.S

/*
 *  linux/arch/arm/mm/proc-v7.S
 *
 *  Copyright (C) 2001 Deep Blue Solutions Ltd.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This is the "shell" of the ARMv7 processor support.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>

#include "proc-macros.S"

#ifdef CONFIG_ARM_LPAE
#include "proc-v7-3level.S"
#else
#include "proc-v7-2level.S"
#endif

ENTRY(cpu_v7_proc_init)
	mov	pc, lr
ENDPROC(cpu_v7_proc_init)

ENTRY(cpu_v7_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x0006			@ .............ca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr
ENDPROC(cpu_v7_proc_fin)

/*
 *	cpu_v7_reset(loc)
 *
 *	Perform a soft reset of the system.  Put the CPU into the
 *	same state as it would be if it had been reset, and branch
 *	to what would be the reset vector.
 *
 *	- loc   - location to jump to for soft reset
 *
 *	This code must be executed using a flat identity mapping with
 *      caches disabled.
 */
	.align	5
	.pushsection	.idmap.text, "ax"
ENTRY(cpu_v7_reset)
	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x1			@ ...............m
 THUMB(	bic	r1, r1, #1 << 30 )		@ SCTLR.TE (Thumb exceptions)
	mcr	p15, 0, r1, c1, c0, 0		@ disable MMU
	isb
	bx	r0
ENDPROC(cpu_v7_reset)
	.popsection

/*
 *	cpu_v7_do_idle()
 *
 *	Idle the processor (eg, wait for interrupt).
 *
 *	IRQs are already disabled.
 */
ENTRY(cpu_v7_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	mov	pc, lr
ENDPROC(cpu_v7_do_idle)

ENTRY(cpu_v7_dcache_clean_area)
	ALT_SMP(W(nop))			@ MP extensions imply L1 PTW
	ALT_UP_B(1f)
	mov	pc, lr
1:	dcache_line_size r2, r3
2:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, r2
	subs	r1, r1, r2
	bhi	2b
	dsb	ishst
	mov	pc, lr
ENDPROC(cpu_v7_dcache_clean_area)

	string	cpu_v7_name, "ARMv7 Processor"
	.align

/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
.globl	cpu_v7_suspend_size
.equ	cpu_v7_suspend_size, 4 * 8
#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_v7_do_suspend)
	stmfd	sp!, {r4 - r10, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mrc	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	stmia	r0!, {r4 - r5}
#ifdef CONFIG_MMU
	mrc	p15, 0, r6, c3, c0, 0	@ Domain ID
	mrc	p15, 0, r7, c2, c0, 1	@ TTB 1
	mrc	p15, 0, r11, c2, c0, 2	@ TTB control register
#endif
	mrc	p15, 0, r8, c1, c0, 0	@ Control register
	mrc	p15, 0, r9, c1, c0, 1	@ Auxiliary control register
	mrc	p15, 0, r10, c1, c0, 2	@ Co-processor access control
	stmia	r0, {r6 - r11}
	ldmfd	sp!, {r4 - r10, pc}
ENDPROC(cpu_v7_do_suspend)

ENTRY(cpu_v7_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c5, 0	@ invalidate I cache
	mcr	p15, 0, ip, c13, c0, 1	@ set reserved context ID
	ldmia	r0!, {r4 - r5}
	mcr	p15, 0, r4, c13, c0, 0	@ FCSE/PID
	mcr	p15, 0, r5, c13, c0, 3	@ User r/o thread ID
	ldmia	r0, {r6 - r11}
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate TLBs
	mcr	p15, 0, r6, c3, c0, 0	@ Domain ID
#ifndef CONFIG_ARM_LPAE
	ALT_SMP(orr	r1, r1, #TTB_FLAGS_SMP)
	ALT_UP(orr	r1, r1, #TTB_FLAGS_UP)
#endif
	mcr	p15, 0, r1, c2, c0, 0	@ TTB 0
	mcr	p15, 0, r7, c2, c0, 1	@ TTB 1
	mcr	p15, 0, r11, c2, c0, 2	@ TTB control register
	ldr	r4, =PRRR		@ PRRR
	ldr	r5, =NMRR		@ NMRR
	mcr	p15, 0, r4, c10, c2, 0	@ write PRRR
	mcr	p15, 0, r5, c10, c2, 1	@ write NMRR
#endif	/* CONFIG_MMU */
	mrc	p15, 0, r4, c1, c0, 1	@ Read Auxiliary control register
	teq	r4, r9			@ Is it already set?
	mcrne	p15, 0, r9, c1, c0, 1	@ No, so write it
	mcr	p15, 0, r10, c1, c0, 2	@ Co-processor access control
	isb
	dsb
	mov	r0, r8			@ control register
	b	cpu_resume_mmu
ENDPROC(cpu_v7_do_resume)
#endif

#ifdef CONFIG_CPU_PJ4B
	globl_equ	cpu_pj4b_switch_mm,     cpu_v7_switch_mm
	globl_equ	cpu_pj4b_set_pte_ext,	cpu_v7_set_pte_ext
	globl_equ	cpu_pj4b_proc_init,	cpu_v7_proc_init
	globl_equ	cpu_pj4b_proc_fin, 	cpu_v7_proc_fin
	globl_equ	cpu_pj4b_reset,	   	cpu_v7_reset
#ifdef CONFIG_PJ4B_ERRATA_4742
ENTRY(cpu_pj4b_do_idle)
	dsb					@ WFI may enter a low-power mode
	wfi
	dsb					@barrier
	mov	pc, lr
ENDPROC(cpu_pj4b_do_idle)
#else
	globl_equ	cpu_pj4b_do_idle,  	cpu_v7_do_idle
#endif
	globl_equ	cpu_pj4b_dcache_clean_area,	cpu_v7_dcache_clean_area
	globl_equ	cpu_pj4b_do_suspend,	cpu_v7_do_suspend
	globl_equ	cpu_pj4b_do_resume,	cpu_v7_do_resume
	globl_equ	cpu_pj4b_suspend_size,	cpu_v7_suspend_size

#endif

/*
 *	__v7_setup
 *
 *	Initialise TLB, Caches, and MMU state ready to switch the MMU
 *	on.  Return in r0 the new CP15 C1 control register setting.
 *
 *	This should be able to cover all ARMv7 cores.
 *
 *	It is assumed that:
 *	- cache type register is implemented
 */
__v7_ca5mp_setup:
__v7_ca9mp_setup:
__v7_cr7mp_setup:
	mov	r10, #(1 << 0)			@ Cache/TLB ops broadcasting
	b	1f
__v7_ca7mp_setup:
__v7_ca15mp_setup:
	mov	r10, #0
1:
#ifdef CONFIG_SMP
	ALT_SMP(mrc	p15, 0, r0, c1, c0, 1)
	ALT_UP(mov	r0, #(1 << 6))		@ fake it for UP
	tst	r0, #(1 << 6)			@ SMP/nAMP mode enabled?
	orreq	r0, r0, #(1 << 6)		@ Enable SMP/nAMP mode
	orreq	r0, r0, r10			@ Enable CPU-specific SMP bits
	mcreq	p15, 0, r0, c1, c0, 1
#endif
	b	__v7_setup

__v7_pj4b_setup:
#ifdef CONFIG_CPU_PJ4B

/* Auxiliary Debug Modes Control 1 Register */
#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */

/* Auxiliary Debug Modes Control 2 Register */
#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA | PJ4B_CWF |\
			    PJ4B_OUTSDNG_NC | PJ4B_L1_REP_RR)

/* Auxiliary Functional Modes Control Register 0 */
#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */

/* Auxiliary Debug Modes Control 0 Register */
#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */

	/* Auxiliary Debug Modes Control 1 Register */
	mrc	p15, 1,	r0, c15, c1, 1
	orr     r0, r0, #PJ4B_CLEAN_LINE
	orr     r0, r0, #PJ4B_BCK_OFF_STREX
	orr     r0, r0, #PJ4B_INTER_PARITY
	bic	r0, r0, #PJ4B_STATIC_BP
	mcr	p15, 1,	r0, c15, c1, 1

	/* Auxiliary Debug Modes Control 2 Register */
	mrc	p15, 1,	r0, c15, c1, 2
	bic	r0, r0, #PJ4B_FAST_LDR
	orr	r0, r0, #PJ4B_AUX_DBG_CTRL2
	mcr	p15, 1,	r0, c15, c1, 2

	/* Auxiliary Functional Modes Control Register 0 */
	mrc	p15, 1,	r0, c15, c2, 0
#ifdef CONFIG_SMP
	orr	r0, r0, #PJ4B_SMP_CFB
#endif
	orr	r0, r0, #PJ4B_L1_PAR_CHK
	orr	r0, r0, #PJ4B_BROADCAST_CACHE
	mcr	p15, 1,	r0, c15, c2, 0

	/* Auxiliary Debug Modes Control 0 Register */
	mrc	p15, 1,	r0, c15, c1, 0
	orr	r0, r0, #PJ4B_WFI_WFE
	mcr	p15, 1,	r0, c15, c1, 0

#endif /* CONFIG_CPU_PJ4B */

__v7_setup:
	adr	r12, __v7_setup_stack		@ the local stack
	stmia	r12, {r0-r5, r7, r9, r11, lr}
	bl      v7_flush_dcache_louis
	ldmia	r12, {r0-r5, r7, r9, r11, lr}

	mrc	p15, 0, r0, c0, c0, 0		@ read main ID register
	and	r10, r0, #0xff000000		@ ARM?
	teq	r10, #0x41000000
	bne	3f
	and	r5, r0, #0x00f00000		@ variant
	and	r6, r0, #0x0000000f		@ revision
	orr	r6, r6, r5, lsr #20-4		@ combine variant and revision
	ubfx	r0, r0, #4, #12			@ primary part number

	/* Cortex-A8 Errata */
	ldr	r10, =0x00000c08		@ Cortex-A8 primary part number
	teq	r0, r10
	bne	2f
#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)

	teq	r5, #0x00100000			@ only present in r1p*
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 6)		@ set IBE to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_458693
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 0, r10, c1, c0, 1		@ read aux control register
	orreq	r10, r10, #(1 << 5)		@ set L1NEON to 1
	orreq	r10, r10, #(1 << 9)		@ set PLDNOP to 1
	mcreq	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif
#ifdef CONFIG_ARM_ERRATA_460075
	teq	r6, #0x20			@ only present in r2p0
	mrceq	p15, 1, r10, c9, c0, 2		@ read L2 cache aux ctrl register
	tsteq	r10, #1 << 22
	orreq	r10, r10, #(1 << 22)		@ set the Write Allocate disable bit
	mcreq	p15, 1, r10, c9, c0, 2		@ write the L2 cache aux ctrl register
#endif
	b	3f

	/* Cortex-A9 Errata */
2:	ldr	r10, =0x00000c09		@ Cortex-A9 primary part number
	teq	r0, r10
	bne	3f
#ifdef CONFIG_ARM_ERRATA_742230
	cmp	r6, #0x22			@ only present up to r2p2
	mrcle	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrle	r10, r10, #1 << 4		@ set bit #4
	mcrle	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_742231
	teq	r6, #0x20			@ present in r2p0
	teqne	r6, #0x21			@ present in r2p1
	teqne	r6, #0x22			@ present in r2p2
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 12		@ set bit #12
	orreq	r10, r10, #1 << 22		@ set bit #22
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#ifdef CONFIG_ARM_ERRATA_743622
	teq	r5, #0x00200000			@ only present in r2p*
	mrceq	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orreq	r10, r10, #1 << 6		@ set bit #6
	mcreq	p15, 0, r10, c15, c0, 1		@ write diagnostic register
#endif
#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
	ALT_SMP(cmp r6, #0x30)			@ present prior to r3p0
	ALT_UP_B(1f)
	mrclt	p15, 0, r10, c15, c0, 1		@ read diagnostic register
	orrlt	r10, r10, #1 << 11		@ set bit #11
	mcrlt	p15, 0, r10, c15, c0, 1		@ write diagnostic register
1:
#endif

	/* Cortex-A15 Errata */
3:	ldr	r10, =0x00000c0f		@ Cortex-A15 primary part number
	teq	r0, r10
	bne	4f

#ifdef CONFIG_ARM_ERRATA_773022
	cmp	r6, #0x4			@ only present up to r0p4
	mrcle	p15, 0, r10, c1, c0, 1		@ read aux control register
	orrle	r10, r10, #1 << 1		@ disable loop buffer
	mcrle	p15, 0, r10, c1, c0, 1		@ write aux control register
#endif

4:	mov	r10, #0
	mcr	p15, 0, r10, c7, c5, 0		@ I+BTB cache invalidate
	dsb
#ifdef CONFIG_MMU
	mcr	p15, 0, r10, c8, c7, 0		@ invalidate I + D TLBs
	v7_ttb_setup r10, r4, r8, r5		@ TTBCR, TTBRx setup
	ldr	r5, =PRRR			@ PRRR
	ldr	r6, =NMRR			@ NMRR
	mcr	p15, 0, r5, c10, c2, 0		@ write PRRR
	mcr	p15, 0, r6, c10, c2, 1		@ write NMRR
#endif
#ifndef CONFIG_ARM_THUMBEE
	mrc	p15, 0, r0, c0, c1, 0		@ read ID_PFR0 for ThumbEE
	and	r0, r0, #(0xf << 12)		@ ThumbEE enabled field
	teq	r0, #(1 << 12)			@ check if ThumbEE is present
	bne	1f
	mov	r5, #0
	mcr	p14, 6, r5, c1, c0, 0		@ Initialize TEEHBR to 0
	mrc	p14, 6, r0, c0, c0, 0		@ load TEECR
	orr	r0, r0, #1			@ set the 1st bit in order to
	mcr	p14, 6, r0, c0, c0, 0		@ stop userspace TEEHBR access
1:
#endif
	adr	r5, v7_crval
	ldmia	r5, {r5, r6}
 ARM_BE8(orr	r6, r6, #1 << 25)		@ big-endian page tables
#ifdef CONFIG_SWP_EMULATE
	orr     r5, r5, #(1 << 10)              @ set SW bit in "clear"
	bic     r6, r6, #(1 << 10)              @ clear it in "mmuset"
#endif
   	mrc	p15, 0, r0, c1, c0, 0		@ read control register
	bic	r0, r0, r5			@ clear bits them
	orr	r0, r0, r6			@ set them
 THUMB(	orr	r0, r0, #1 << 30	)	@ Thumb exceptions
	mov	pc, lr				@ return to head.S:__ret
ENDPROC(__v7_setup)

	.align	2
__v7_setup_stack:
	.space	4 * 11				@ 11 registers

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
#ifdef CONFIG_CPU_PJ4B
	define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
#endif

	.section ".rodata"

	string	cpu_arch_name, "armv7"
	string	cpu_elf_name, "v7"
	.align

	.section ".proc.info.init", #alloc, #execinstr

	/*
	 * Standard v7 proc info content
	 */
.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
			PMD_SECT_AF | PMD_FLAGS_UP | \mm_mmuflags)
	.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ | PMD_SECT_AF | \io_mmuflags
	W(b)	\initfunc
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
		HWCAP_EDSP | HWCAP_TLS | \hwcaps
	.long	cpu_v7_name
	.long	\proc_fns
	.long	v7wbi_tlb_fns
	.long	v6_user_fns
	.long	v7_cache_fns
.endm

#ifndef CONFIG_ARM_LPAE
	/*
	 * ARM Ltd. Cortex A5 processor.
	 */
	.type   __v7_ca5mp_proc_info, #object
__v7_ca5mp_proc_info:
	.long	0x410fc050
	.long	0xff0ffff0
	__v7_proc __v7_ca5mp_setup
	.size	__v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info

	/*
	 * ARM Ltd. Cortex A9 processor.
	 */
	.type   __v7_ca9mp_proc_info, #object
__v7_ca9mp_proc_info:
	.long	0x410fc090
	.long	0xff0ffff0
	__v7_proc __v7_ca9mp_setup
	.size	__v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info

#endif	/* CONFIG_ARM_LPAE */

	/*
	 * Marvell PJ4B processor.
	 */
#ifdef CONFIG_CPU_PJ4B
	.type   __v7_pj4b_proc_info, #object
__v7_pj4b_proc_info:
	.long	0x560f5800
	.long	0xff0fff00
	__v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
	.size	__v7_pj4b_proc_info, . - __v7_pj4b_proc_info
#endif

	/*
	 * ARM Ltd. Cortex R7 processor.
	 */
	.type	__v7_cr7mp_proc_info, #object
__v7_cr7mp_proc_info:
	.long	0x410fc170
	.long	0xff0ffff0
	__v7_proc __v7_cr7mp_setup
	.size	__v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info

	/*
	 * ARM Ltd. Cortex A7 processor.
	 */
	.type	__v7_ca7mp_proc_info, #object
__v7_ca7mp_proc_info:
	.long	0x410fc070
	.long	0xff0ffff0
	__v7_proc __v7_ca7mp_setup
	.size	__v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info

	/*
	 * ARM Ltd. Cortex A15 processor.
	 */
	.type	__v7_ca15mp_proc_info, #object
__v7_ca15mp_proc_info:
	.long	0x410fc0f0
	.long	0xff0ffff0
	__v7_proc __v7_ca15mp_setup
	.size	__v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info

	/*
	 * Qualcomm Inc. Krait processors.
	 */
	.type	__krait_proc_info, #object
__krait_proc_info:
	.long	0x510f0400		@ Required ID value
	.long	0xff0ffc00		@ Mask for ID
	/*
	 * Some Krait processors don't indicate support for SDIV and UDIV
	 * instructions in the ARM instruction set, even though they actually
	 * do support them.
	 */
	__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
	.size	__krait_proc_info, . - __krait_proc_info

	/*
	 * Match any ARMv7 processor core.
	 */
	.type	__v7_proc_info, #object
__v7_proc_info:
	.long	0x000f0000		@ Required ID value
	.long	0x000f0000		@ Mask for ID
	__v7_proc __v7_setup
	.size	__v7_proc_info, . - __v7_proc_info
Commit	Line	Data
bbe88886 CM	1	/*
	2	* linux/arch/arm/mm/proc-v7.S
	3	*
	4	* Copyright (C) 2001 Deep Blue Solutions Ltd.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This is the "shell" of the ARMv7 processor support.
	11	*/
991da17e	12	#include <linux/init.h>
bbe88886 CM	13	#include <linux/linkage.h>
	14	#include <asm/assembler.h>
	15	#include <asm/asm-offsets.h>
5ec9407d	16	#include <asm/hwcap.h>
bbe88886 CM	17	#include <asm/pgtable-hwdef.h>
	18	#include <asm/pgtable.h>
	19
	20	#include "proc-macros.S"
	21
1b6ba46b CM	22	#ifdef CONFIG_ARM_LPAE
	23	#include "proc-v7-3level.S"
	24	#else
8d2cd3a3	25	#include "proc-v7-2level.S"
1b6ba46b	26	#endif
73b63efa	27
bbe88886 CM	28	ENTRY(cpu_v7_proc_init)
bbe88886 CM	29	mov pc, lr
93ed3970	30	ENDPROC(cpu_v7_proc_init)
bbe88886 CM	31
bbe88886 CM	32	ENTRY(cpu_v7_proc_fin)
1f667c69 TL	33	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	34	bic r0, r0, #0x1000 @ ...i............
	35	bic r0, r0, #0x0006 @ .............ca.
	36	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	37	mov pc, lr
93ed3970	38	ENDPROC(cpu_v7_proc_fin)
bbe88886 CM	39
	40	/*
	41	* cpu_v7_reset(loc)
	42	*
	43	* Perform a soft reset of the system. Put the CPU into the
	44	* same state as it would be if it had been reset, and branch
	45	* to what would be the reset vector.
	46	*
	47	* - loc - location to jump to for soft reset
f4daf06f WD	48	*
	49	* This code must be executed using a flat identity mapping with
	50	* caches disabled.
bbe88886 CM	51	*/
bbe88886 CM	52	.align 5
1a4baafa	53	.pushsection .idmap.text, "ax"
bbe88886	54	ENTRY(cpu_v7_reset)
f4daf06f WD	55	mrc p15, 0, r1, c1, c0, 0 @ ctrl register
f4daf06f WD	56	bic r1, r1, #0x1 @ ...............m
0f81bb6b	57	THUMB( bic r1, r1, #1 << 30 ) @ SCTLR.TE (Thumb exceptions)
f4daf06f WD	58	mcr p15, 0, r1, c1, c0, 0 @ disable MMU
f4daf06f WD	59	isb
153cd8e8	60	bx r0
93ed3970	61	ENDPROC(cpu_v7_reset)
1a4baafa	62	.popsection
bbe88886 CM	63
	64	/*
	65	* cpu_v7_do_idle()
	66	*
	67	* Idle the processor (eg, wait for interrupt).
	68	*
	69	* IRQs are already disabled.
	70	*/
	71	ENTRY(cpu_v7_do_idle)
8553cb67	72	dsb @ WFI may enter a low-power mode
000b5025	73	wfi
bbe88886	74	mov pc, lr
93ed3970	75	ENDPROC(cpu_v7_do_idle)
bbe88886 CM	76
bbe88886 CM	77	ENTRY(cpu_v7_dcache_clean_area)
bf3f0f33 WD	78	ALT_SMP(W(nop)) @ MP extensions imply L1 PTW
	79	ALT_UP_B(1f)
	80	mov pc, lr
	81	1: dcache_line_size r2, r3
	82	2: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
bbe88886 CM	83	add r0, r0, r2
bbe88886 CM	84	subs r1, r1, r2
bf3f0f33	85	bhi 2b
6abdd491	86	dsb ishst
bbe88886	87	mov pc, lr
93ed3970	88	ENDPROC(cpu_v7_dcache_clean_area)
bbe88886	89
78a8f3c3	90	string cpu_v7_name, "ARMv7 Processor"
bbe88886 CM	91	.align
bbe88886 CM	92
f6b0fa02 RK	93	/* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */
f6b0fa02 RK	94	.globl cpu_v7_suspend_size
1b6ba46b	95	.equ cpu_v7_suspend_size, 4 * 8
15e0d9e3	96	#ifdef CONFIG_ARM_CPU_SUSPEND
f6b0fa02	97	ENTRY(cpu_v7_do_suspend)
de8e71ca	98	stmfd sp!, {r4 - r10, lr}
f6b0fa02	99	mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID
1aede681 RK	100	mrc p15, 0, r5, c13, c0, 3 @ User r/o thread ID
1aede681 RK	101	stmia r0!, {r4 - r5}
aa1aadc3	102	#ifdef CONFIG_MMU
f6b0fa02	103	mrc p15, 0, r6, c3, c0, 0 @ Domain ID
de8e71ca	104	mrc p15, 0, r7, c2, c0, 1 @ TTB 1
1b6ba46b	105	mrc p15, 0, r11, c2, c0, 2 @ TTB control register
aa1aadc3	106	#endif
de8e71ca RK	107	mrc p15, 0, r8, c1, c0, 0 @ Control register
	108	mrc p15, 0, r9, c1, c0, 1 @ Auxiliary control register
	109	mrc p15, 0, r10, c1, c0, 2 @ Co-processor access control
1b6ba46b	110	stmia r0, {r6 - r11}
de8e71ca	111	ldmfd sp!, {r4 - r10, pc}
f6b0fa02 RK	112	ENDPROC(cpu_v7_do_suspend)
	113
	114	ENTRY(cpu_v7_do_resume)
	115	mov ip, #0
f6b0fa02	116	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
1aede681 RK	117	mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID
1aede681 RK	118	ldmia r0!, {r4 - r5}
f6b0fa02	119	mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID
1aede681	120	mcr p15, 0, r5, c13, c0, 3 @ User r/o thread ID
1b6ba46b	121	ldmia r0, {r6 - r11}
aa1aadc3 WD	122	#ifdef CONFIG_MMU
aa1aadc3 WD	123	mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs
f6b0fa02	124	mcr p15, 0, r6, c3, c0, 0 @ Domain ID
1b6ba46b	125	#ifndef CONFIG_ARM_LPAE
de8e71ca RK	126	ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP)
de8e71ca RK	127	ALT_UP(orr r1, r1, #TTB_FLAGS_UP)
1b6ba46b	128	#endif
de8e71ca RK	129	mcr p15, 0, r1, c2, c0, 0 @ TTB 0
de8e71ca RK	130	mcr p15, 0, r7, c2, c0, 1 @ TTB 1
1b6ba46b	131	mcr p15, 0, r11, c2, c0, 2 @ TTB control register
f6b0fa02 RK	132	ldr r4, =PRRR @ PRRR
	133	ldr r5, =NMRR @ NMRR
	134	mcr p15, 0, r4, c10, c2, 0 @ write PRRR
	135	mcr p15, 0, r5, c10, c2, 1 @ write NMRR
aa1aadc3 WD	136	#endif /* CONFIG_MMU */
	137	mrc p15, 0, r4, c1, c0, 1 @ Read Auxiliary control register
	138	teq r4, r9 @ Is it already set?
	139	mcrne p15, 0, r9, c1, c0, 1 @ No, so write it
	140	mcr p15, 0, r10, c1, c0, 2 @ Co-processor access control
f6b0fa02	141	isb
f35235a3	142	dsb
de8e71ca	143	mov r0, r8 @ control register
f6b0fa02 RK	144	b cpu_resume_mmu
f6b0fa02 RK	145	ENDPROC(cpu_v7_do_resume)
3e0a07f8 GC	146	#endif
	147
	148	#ifdef CONFIG_CPU_PJ4B
	149	globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
	150	globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
	151	globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
	152	globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
	153	globl_equ cpu_pj4b_reset, cpu_v7_reset
	154	#ifdef CONFIG_PJ4B_ERRATA_4742
	155	ENTRY(cpu_pj4b_do_idle)
	156	dsb @ WFI may enter a low-power mode
	157	wfi
	158	dsb @barrier
	159	mov pc, lr
	160	ENDPROC(cpu_pj4b_do_idle)
	161	#else
	162	globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
	163	#endif
	164	globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
	165	globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend
	166	globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume
	167	globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size
	168
f6b0fa02 RK	169	#endif
f6b0fa02 RK	170
bbe88886 CM	171	/*
	172	* __v7_setup
	173	*
	174	* Initialise TLB, Caches, and MMU state ready to switch the MMU
	175	* on. Return in r0 the new CP15 C1 control register setting.
	176	*
bbe88886 CM	177	* This should be able to cover all ARMv7 cores.
	178	*
	179	* It is assumed that:
	180	* - cache type register is implemented
	181	*/
15eb169b	182	__v7_ca5mp_setup:
14eff181	183	__v7_ca9mp_setup:
c90ad5c9 JA	184	__v7_cr7mp_setup:
c90ad5c9 JA	185	mov r10, #(1 << 0) @ Cache/TLB ops broadcasting
7665d9d2	186	b 1f
b4244738	187	__v7_ca7mp_setup:
7665d9d2 WD	188	__v7_ca15mp_setup:
	189	mov r10, #0
	190	1:
73b63efa	191	#ifdef CONFIG_SMP
f00ec48f RK	192	ALT_SMP(mrc p15, 0, r0, c1, c0, 1)
f00ec48f RK	193	ALT_UP(mov r0, #(1 << 6)) @ fake it for UP
1b3a02eb	194	tst r0, #(1 << 6) @ SMP/nAMP mode enabled?
7665d9d2 WD	195	orreq r0, r0, #(1 << 6) @ Enable SMP/nAMP mode
	196	orreq r0, r0, r10 @ Enable CPU-specific SMP bits
	197	mcreq p15, 0, r0, c1, c0, 1
73b63efa	198	#endif
d106de38	199	b __v7_setup
de490193 GC	200
	201	__v7_pj4b_setup:
	202	#ifdef CONFIG_CPU_PJ4B
	203
	204	/* Auxiliary Debug Modes Control 1 Register */
	205	#define PJ4B_STATIC_BP (1 << 2) /* Enable Static BP */
	206	#define PJ4B_INTER_PARITY (1 << 8) /* Disable Internal Parity Handling */
	207	#define PJ4B_BCK_OFF_STREX (1 << 5) /* Enable the back off of STREX instr */
	208	#define PJ4B_CLEAN_LINE (1 << 16) /* Disable data transfer for clean line */
	209
	210	/* Auxiliary Debug Modes Control 2 Register */
	211	#define PJ4B_FAST_LDR (1 << 23) /* Disable fast LDR */
	212	#define PJ4B_SNOOP_DATA (1 << 25) /* Do not interleave write and snoop data */
	213	#define PJ4B_CWF (1 << 27) /* Disable Critical Word First feature */
	214	#define PJ4B_OUTSDNG_NC (1 << 29) /* Disable outstanding non cacheable rqst */
	215	#define PJ4B_L1_REP_RR (1 << 30) /* L1 replacement - Strict round robin */
	216	#define PJ4B_AUX_DBG_CTRL2 (PJ4B_SNOOP_DATA \| PJ4B_CWF \|\
	217	PJ4B_OUTSDNG_NC \| PJ4B_L1_REP_RR)
	218
	219	/* Auxiliary Functional Modes Control Register 0 */
	220	#define PJ4B_SMP_CFB (1 << 1) /* Set SMP mode. Join the coherency fabric */
	221	#define PJ4B_L1_PAR_CHK (1 << 2) /* Support L1 parity checking */
	222	#define PJ4B_BROADCAST_CACHE (1 << 8) /* Broadcast Cache and TLB maintenance */
	223
	224	/* Auxiliary Debug Modes Control 0 Register */
	225	#define PJ4B_WFI_WFE (1 << 22) /* WFI/WFE - serve the DVM and back to idle */
	226
	227	/* Auxiliary Debug Modes Control 1 Register */
	228	mrc p15, 1, r0, c15, c1, 1
	229	orr r0, r0, #PJ4B_CLEAN_LINE
	230	orr r0, r0, #PJ4B_BCK_OFF_STREX
	231	orr r0, r0, #PJ4B_INTER_PARITY
	232	bic r0, r0, #PJ4B_STATIC_BP
	233	mcr p15, 1, r0, c15, c1, 1
	234
	235	/* Auxiliary Debug Modes Control 2 Register */
	236	mrc p15, 1, r0, c15, c1, 2
	237	bic r0, r0, #PJ4B_FAST_LDR
	238	orr r0, r0, #PJ4B_AUX_DBG_CTRL2
	239	mcr p15, 1, r0, c15, c1, 2
	240
	241	/* Auxiliary Functional Modes Control Register 0 */
	242	mrc p15, 1, r0, c15, c2, 0
	243	#ifdef CONFIG_SMP
	244	orr r0, r0, #PJ4B_SMP_CFB
	245	#endif
	246	orr r0, r0, #PJ4B_L1_PAR_CHK
	247	orr r0, r0, #PJ4B_BROADCAST_CACHE
	248	mcr p15, 1, r0, c15, c2, 0
	249
	250	/* Auxiliary Debug Modes Control 0 Register */
	251	mrc p15, 1, r0, c15, c1, 0
	252	orr r0, r0, #PJ4B_WFI_WFE
	253	mcr p15, 1, r0, c15, c1, 0
	254
	255	#endif /* CONFIG_CPU_PJ4B */
	256
14eff181	257	__v7_setup:
bbe88886 CM	258	adr r12, __v7_setup_stack @ the local stack
bbe88886 CM	259	stmia r12, {r0-r5, r7, r9, r11, lr}
6323fa22	260	bl v7_flush_dcache_louis
bbe88886	261	ldmia r12, {r0-r5, r7, r9, r11, lr}
1946d6ef RK	262
	263	mrc p15, 0, r0, c0, c0, 0 @ read main ID register
	264	and r10, r0, #0xff000000 @ ARM?
	265	teq r10, #0x41000000
9f05027c	266	bne 3f
1946d6ef RK	267	and r5, r0, #0x00f00000 @ variant
1946d6ef RK	268	and r6, r0, #0x0000000f @ revision
6491848d WD	269	orr r6, r6, r5, lsr #20-4 @ combine variant and revision
6491848d WD	270	ubfx r0, r0, #4, #12 @ primary part number
1946d6ef	271
6491848d WD	272	/* Cortex-A8 Errata */
	273	ldr r10, =0x00000c08 @ Cortex-A8 primary part number
	274	teq r0, r10
	275	bne 2f
62e4d357 RH	276	#if defined(CONFIG_ARM_ERRATA_430973) && !defined(CONFIG_ARCH_MULTIPLATFORM)
62e4d357 RH	277
1946d6ef RK	278	teq r5, #0x00100000 @ only present in r1p*
	279	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	280	orreq r10, r10, #(1 << 6) @ set IBE to 1
	281	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
855c551f CM	282	#endif
855c551f CM	283	#ifdef CONFIG_ARM_ERRATA_458693
6491848d	284	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	285	mrceq p15, 0, r10, c1, c0, 1 @ read aux control register
	286	orreq r10, r10, #(1 << 5) @ set L1NEON to 1
	287	orreq r10, r10, #(1 << 9) @ set PLDNOP to 1
	288	mcreq p15, 0, r10, c1, c0, 1 @ write aux control register
0516e464 CM	289	#endif
0516e464 CM	290	#ifdef CONFIG_ARM_ERRATA_460075
6491848d	291	teq r6, #0x20 @ only present in r2p0
1946d6ef RK	292	mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register
	293	tsteq r10, #1 << 22
	294	orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit
	295	mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register
7ce236fc	296	#endif
9f05027c WD	297	b 3f
	298
	299	/* Cortex-A9 Errata */
	300	2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number
	301	teq r0, r10
	302	bne 3f
	303	#ifdef CONFIG_ARM_ERRATA_742230
	304	cmp r6, #0x22 @ only present up to r2p2
	305	mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register
	306	orrle r10, r10, #1 << 4 @ set bit #4
	307	mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register
	308	#endif
a672e99b WD	309	#ifdef CONFIG_ARM_ERRATA_742231
	310	teq r6, #0x20 @ present in r2p0
	311	teqne r6, #0x21 @ present in r2p1
	312	teqne r6, #0x22 @ present in r2p2
	313	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	314	orreq r10, r10, #1 << 12 @ set bit #12
	315	orreq r10, r10, #1 << 22 @ set bit #22
	316	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	317	#endif
475d92fc	318	#ifdef CONFIG_ARM_ERRATA_743622
efbc74ac	319	teq r5, #0x00200000 @ only present in r2p*
475d92fc WD	320	mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register
	321	orreq r10, r10, #1 << 6 @ set bit #6
	322	mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register
	323	#endif
ba90c516 DM	324	#if defined(CONFIG_ARM_ERRATA_751472) && defined(CONFIG_SMP)
	325	ALT_SMP(cmp r6, #0x30) @ present prior to r3p0
	326	ALT_UP_B(1f)
9a27c27c WD	327	mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register
	328	orrlt r10, r10, #1 << 11 @ set bit #11
	329	mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register
ba90c516	330	1:
9a27c27c	331	#endif
1946d6ef	332
84b6504f WD	333	/* Cortex-A15 Errata */
	334	3: ldr r10, =0x00000c0f @ Cortex-A15 primary part number
	335	teq r0, r10
	336	bne 4f
	337
	338	#ifdef CONFIG_ARM_ERRATA_773022
	339	cmp r6, #0x4 @ only present up to r0p4
	340	mrcle p15, 0, r10, c1, c0, 1 @ read aux control register
	341	orrle r10, r10, #1 << 1 @ disable loop buffer
	342	mcrle p15, 0, r10, c1, c0, 1 @ write aux control register
	343	#endif
	344
	345	4: mov r10, #0
bbe88886	346	mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate
bbe88886	347	dsb
2eb8c82b	348	#ifdef CONFIG_MMU
bbe88886	349	mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs
8d2cd3a3	350	v7_ttb_setup r10, r4, r8, r5 @ TTBCR, TTBRx setup
f6b0fa02 RK	351	ldr r5, =PRRR @ PRRR
f6b0fa02 RK	352	ldr r6, =NMRR @ NMRR
3f69c0c1 RK	353	mcr p15, 0, r5, c10, c2, 0 @ write PRRR
3f69c0c1 RK	354	mcr p15, 0, r6, c10, c2, 1 @ write NMRR
078c0454 JA	355	#endif
	356	#ifndef CONFIG_ARM_THUMBEE
	357	mrc p15, 0, r0, c0, c1, 0 @ read ID_PFR0 for ThumbEE
	358	and r0, r0, #(0xf << 12) @ ThumbEE enabled field
	359	teq r0, #(1 << 12) @ check if ThumbEE is present
	360	bne 1f
	361	mov r5, #0
	362	mcr p14, 6, r5, c1, c0, 0 @ Initialize TEEHBR to 0
	363	mrc p14, 6, r0, c0, c0, 0 @ load TEECR
	364	orr r0, r0, #1 @ set the 1st bit in order to
	365	mcr p14, 6, r0, c0, c0, 0 @ stop userspace TEEHBR access
	366	1:
bdaaaec3	367	#endif
2eb8c82b CM	368	adr r5, v7_crval
2eb8c82b CM	369	ldmia r5, {r5, r6}
457c2403	370	ARM_BE8(orr r6, r6, #1 << 25) @ big-endian page tables
64d2dc38 LL	371	#ifdef CONFIG_SWP_EMULATE
	372	orr r5, r5, #(1 << 10) @ set SW bit in "clear"
	373	bic r6, r6, #(1 << 10) @ clear it in "mmuset"
26584853	374	#endif
2eb8c82b CM	375	mrc p15, 0, r0, c1, c0, 0 @ read control register
	376	bic r0, r0, r5 @ clear bits them
	377	orr r0, r0, r6 @ set them
347c8b70	378	THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions
bbe88886	379	mov pc, lr @ return to head.S:__ret
93ed3970	380	ENDPROC(__v7_setup)
bbe88886	381
8d2cd3a3	382	.align 2
bbe88886 CM	383	__v7_setup_stack:
	384	.space 4 * 11 @ 11 registers
	385
5085f3ff RK	386	__INITDATA
5085f3ff RK	387
78a8f3c3 DM	388	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
78a8f3c3 DM	389	define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
3e0a07f8 GC	390	#ifdef CONFIG_CPU_PJ4B
	391	define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
	392	#endif
bbe88886	393
5085f3ff RK	394	.section ".rodata"
5085f3ff RK	395
78a8f3c3 DM	396	string cpu_arch_name, "armv7"
78a8f3c3 DM	397	string cpu_elf_name, "v7"
bbe88886 CM	398	.align
	399
	400	.section ".proc.info.init", #alloc, #execinstr
	401
dc939cd8 PM	402	/*
	403	* Standard v7 proc info content
	404	*/
3e0a07f8	405	.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
dc939cd8	406	ALT_SMP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_SECT_AP_READ \| \
1b6ba46b	407	PMD_SECT_AF \| PMD_FLAGS_SMP \| \mm_mmuflags)
dc939cd8	408	ALT_UP(.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| PMD_SECT_AP_READ \| \
1b6ba46b CM	409	PMD_SECT_AF \| PMD_FLAGS_UP \| \mm_mmuflags)
	410	.long PMD_TYPE_SECT \| PMD_SECT_AP_WRITE \| \
	411	PMD_SECT_AP_READ \| PMD_SECT_AF \| \io_mmuflags
dc939cd8	412	W(b) \initfunc
14eff181 DW	413	.long cpu_arch_name
14eff181 DW	414	.long cpu_elf_name
dc939cd8 PM	415	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB \| HWCAP_FAST_MULT \| \
dc939cd8 PM	416	HWCAP_EDSP \| HWCAP_TLS \| \hwcaps
14eff181	417	.long cpu_v7_name
3e0a07f8	418	.long \proc_fns
14eff181 DW	419	.long v7wbi_tlb_fns
	420	.long v6_user_fns
	421	.long v7_cache_fns
dc939cd8 PM	422	.endm
dc939cd8 PM	423
1b6ba46b	424	#ifndef CONFIG_ARM_LPAE
15eb169b PM	425	/*
	426	* ARM Ltd. Cortex A5 processor.
	427	*/
	428	.type __v7_ca5mp_proc_info, #object
	429	__v7_ca5mp_proc_info:
	430	.long 0x410fc050
	431	.long 0xff0ffff0
	432	__v7_proc __v7_ca5mp_setup
	433	.size __v7_ca5mp_proc_info, . - __v7_ca5mp_proc_info
	434
dc939cd8 PM	435	/*
	436	* ARM Ltd. Cortex A9 processor.
	437	*/
	438	.type __v7_ca9mp_proc_info, #object
	439	__v7_ca9mp_proc_info:
	440	.long 0x410fc090
	441	.long 0xff0ffff0
	442	__v7_proc __v7_ca9mp_setup
14eff181	443	.size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info
de490193	444
b361d61d GC	445	#endif /* CONFIG_ARM_LPAE */
b361d61d GC	446
de490193 GC	447	/*
	448	* Marvell PJ4B processor.
	449	*/
3e0a07f8	450	#ifdef CONFIG_CPU_PJ4B
de490193 GC	451	.type __v7_pj4b_proc_info, #object
de490193 GC	452	__v7_pj4b_proc_info:
049be070 GC	453	.long 0x560f5800
049be070 GC	454	.long 0xff0fff00
3e0a07f8	455	__v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
de490193	456	.size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
3e0a07f8	457	#endif
14eff181	458
c90ad5c9 JA	459	/*
	460	* ARM Ltd. Cortex R7 processor.
	461	*/
	462	.type __v7_cr7mp_proc_info, #object
	463	__v7_cr7mp_proc_info:
	464	.long 0x410fc170
	465	.long 0xff0ffff0
	466	__v7_proc __v7_cr7mp_setup
	467	.size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
	468
868dbf90 WD	469	/*
	470	* ARM Ltd. Cortex A7 processor.
	471	*/
	472	.type __v7_ca7mp_proc_info, #object
	473	__v7_ca7mp_proc_info:
	474	.long 0x410fc070
	475	.long 0xff0ffff0
8164f7af	476	__v7_proc __v7_ca7mp_setup
868dbf90 WD	477	.size __v7_ca7mp_proc_info, . - __v7_ca7mp_proc_info
868dbf90 WD	478
7665d9d2 WD	479	/*
	480	* ARM Ltd. Cortex A15 processor.
	481	*/
	482	.type __v7_ca15mp_proc_info, #object
	483	__v7_ca15mp_proc_info:
	484	.long 0x410fc0f0
	485	.long 0xff0ffff0
8164f7af	486	__v7_proc __v7_ca15mp_setup
7665d9d2 WD	487	.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
7665d9d2 WD	488
120ecfaf SM	489	/*
	490	* Qualcomm Inc. Krait processors.
	491	*/
	492	.type __krait_proc_info, #object
	493	__krait_proc_info:
	494	.long 0x510f0400 @ Required ID value
	495	.long 0xff0ffc00 @ Mask for ID
	496	/*
	497	* Some Krait processors don't indicate support for SDIV and UDIV
	498	* instructions in the ARM instruction set, even though they actually
	499	* do support them.
	500	*/
	501	__v7_proc __v7_setup, hwcaps = HWCAP_IDIV
	502	.size __krait_proc_info, . - __krait_proc_info
	503
bbe88886 CM	504	/*
	505	* Match any ARMv7 processor core.
	506	*/
	507	.type __v7_proc_info, #object
	508	__v7_proc_info:
	509	.long 0x000f0000 @ Required ID value
	510	.long 0x000f0000 @ Mask for ID
dc939cd8	511	__v7_proc __v7_setup
bbe88886	512	.size __v7_proc_info, . - __v7_proc_info