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bbe88886 CM |
1 | /* |
2 | * linux/arch/arm/mm/proc-v7.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This is the "shell" of the ARMv7 processor support. | |
11 | */ | |
991da17e | 12 | #include <linux/init.h> |
bbe88886 CM |
13 | #include <linux/linkage.h> |
14 | #include <asm/assembler.h> | |
15 | #include <asm/asm-offsets.h> | |
5ec9407d | 16 | #include <asm/hwcap.h> |
bbe88886 CM |
17 | #include <asm/pgtable-hwdef.h> |
18 | #include <asm/pgtable.h> | |
19 | ||
20 | #include "proc-macros.S" | |
21 | ||
bbe88886 | 22 | #define TTB_S (1 << 1) |
73b63efa JC |
23 | #define TTB_RGN_NC (0 << 3) |
24 | #define TTB_RGN_OC_WBWA (1 << 3) | |
bbe88886 CM |
25 | #define TTB_RGN_OC_WT (2 << 3) |
26 | #define TTB_RGN_OC_WB (3 << 3) | |
ba3c0263 TT |
27 | #define TTB_NOS (1 << 5) |
28 | #define TTB_IRGN_NC ((0 << 0) | (0 << 6)) | |
29 | #define TTB_IRGN_WBWA ((0 << 0) | (1 << 6)) | |
30 | #define TTB_IRGN_WT ((1 << 0) | (0 << 6)) | |
31 | #define TTB_IRGN_WB ((1 << 0) | (1 << 6)) | |
bbe88886 | 32 | |
ba3c0263 | 33 | /* PTWs cacheable, inner WB not shareable, outer WB not shareable */ |
f00ec48f RK |
34 | #define TTB_FLAGS_UP TTB_IRGN_WB|TTB_RGN_OC_WB |
35 | #define PMD_FLAGS_UP PMD_SECT_WB | |
36 | ||
ba3c0263 | 37 | /* PTWs cacheable, inner WBWA shareable, outer WBWA not shareable */ |
f00ec48f RK |
38 | #define TTB_FLAGS_SMP TTB_IRGN_WBWA|TTB_S|TTB_NOS|TTB_RGN_OC_WBWA |
39 | #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S | |
73b63efa | 40 | |
bbe88886 CM |
41 | ENTRY(cpu_v7_proc_init) |
42 | mov pc, lr | |
93ed3970 | 43 | ENDPROC(cpu_v7_proc_init) |
bbe88886 CM |
44 | |
45 | ENTRY(cpu_v7_proc_fin) | |
1f667c69 TL |
46 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
47 | bic r0, r0, #0x1000 @ ...i............ | |
48 | bic r0, r0, #0x0006 @ .............ca. | |
49 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
9ca03a21 | 50 | mov pc, lr |
93ed3970 | 51 | ENDPROC(cpu_v7_proc_fin) |
bbe88886 CM |
52 | |
53 | /* | |
54 | * cpu_v7_reset(loc) | |
55 | * | |
56 | * Perform a soft reset of the system. Put the CPU into the | |
57 | * same state as it would be if it had been reset, and branch | |
58 | * to what would be the reset vector. | |
59 | * | |
60 | * - loc - location to jump to for soft reset | |
bbe88886 CM |
61 | */ |
62 | .align 5 | |
63 | ENTRY(cpu_v7_reset) | |
64 | mov pc, r0 | |
93ed3970 | 65 | ENDPROC(cpu_v7_reset) |
bbe88886 CM |
66 | |
67 | /* | |
68 | * cpu_v7_do_idle() | |
69 | * | |
70 | * Idle the processor (eg, wait for interrupt). | |
71 | * | |
72 | * IRQs are already disabled. | |
73 | */ | |
74 | ENTRY(cpu_v7_do_idle) | |
8553cb67 | 75 | dsb @ WFI may enter a low-power mode |
000b5025 | 76 | wfi |
bbe88886 | 77 | mov pc, lr |
93ed3970 | 78 | ENDPROC(cpu_v7_do_idle) |
bbe88886 CM |
79 | |
80 | ENTRY(cpu_v7_dcache_clean_area) | |
81 | #ifndef TLB_CAN_READ_FROM_L1_CACHE | |
82 | dcache_line_size r2, r3 | |
83 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
84 | add r0, r0, r2 | |
85 | subs r1, r1, r2 | |
86 | bhi 1b | |
87 | dsb | |
88 | #endif | |
89 | mov pc, lr | |
93ed3970 | 90 | ENDPROC(cpu_v7_dcache_clean_area) |
bbe88886 CM |
91 | |
92 | /* | |
93 | * cpu_v7_switch_mm(pgd_phys, tsk) | |
94 | * | |
95 | * Set the translation table base pointer to be pgd_phys | |
96 | * | |
97 | * - pgd_phys - physical address of new TTB | |
98 | * | |
99 | * It is assumed that: | |
100 | * - we are not using split page tables | |
101 | */ | |
102 | ENTRY(cpu_v7_switch_mm) | |
2eb8c82b | 103 | #ifdef CONFIG_MMU |
bbe88886 CM |
104 | mov r2, #0 |
105 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | |
f00ec48f RK |
106 | ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) |
107 | ALT_UP(orr r0, r0, #TTB_FLAGS_UP) | |
7ce236fc CM |
108 | #ifdef CONFIG_ARM_ERRATA_430973 |
109 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB | |
fcbdc5fe | 110 | #endif |
07989b7a RK |
111 | #ifdef CONFIG_ARM_ERRATA_754322 |
112 | dsb | |
113 | #endif | |
114 | mcr p15, 0, r2, c13, c0, 1 @ set reserved context ID | |
115 | isb | |
116 | 1: mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | |
bbe88886 | 117 | isb |
fcbdc5fe WD |
118 | #ifdef CONFIG_ARM_ERRATA_754322 |
119 | dsb | |
120 | #endif | |
bbe88886 CM |
121 | mcr p15, 0, r1, c13, c0, 1 @ set context ID |
122 | isb | |
2eb8c82b | 123 | #endif |
bbe88886 | 124 | mov pc, lr |
93ed3970 | 125 | ENDPROC(cpu_v7_switch_mm) |
bbe88886 CM |
126 | |
127 | /* | |
128 | * cpu_v7_set_pte_ext(ptep, pte) | |
129 | * | |
130 | * Set a level 2 translation table entry. | |
131 | * | |
132 | * - ptep - pointer to level 2 translation table entry | |
d30e45ee | 133 | * (hardware version is stored at +2048 bytes) |
bbe88886 CM |
134 | * - pte - PTE value to store |
135 | * - ext - value for extended PTE bits | |
bbe88886 CM |
136 | */ |
137 | ENTRY(cpu_v7_set_pte_ext) | |
2eb8c82b | 138 | #ifdef CONFIG_MMU |
d30e45ee | 139 | str r1, [r0] @ linux version |
bbe88886 CM |
140 | |
141 | bic r3, r1, #0x000003f0 | |
3f69c0c1 | 142 | bic r3, r3, #PTE_TYPE_MASK |
bbe88886 CM |
143 | orr r3, r3, r2 |
144 | orr r3, r3, #PTE_EXT_AP0 | 2 | |
145 | ||
b1cce6b1 | 146 | tst r1, #1 << 4 |
3f69c0c1 RK |
147 | orrne r3, r3, #PTE_EXT_TEX(1) |
148 | ||
36bb94ba RK |
149 | eor r1, r1, #L_PTE_DIRTY |
150 | tst r1, #L_PTE_RDONLY | L_PTE_DIRTY | |
151 | orrne r3, r3, #PTE_EXT_APX | |
bbe88886 CM |
152 | |
153 | tst r1, #L_PTE_USER | |
154 | orrne r3, r3, #PTE_EXT_AP1 | |
247055aa CM |
155 | #ifdef CONFIG_CPU_USE_DOMAINS |
156 | @ allow kernel read/write access to read-only user pages | |
bbe88886 CM |
157 | tstne r3, #PTE_EXT_APX |
158 | bicne r3, r3, #PTE_EXT_APX | PTE_EXT_AP0 | |
247055aa | 159 | #endif |
bbe88886 | 160 | |
9522d7e4 RK |
161 | tst r1, #L_PTE_XN |
162 | orrne r3, r3, #PTE_EXT_XN | |
bbe88886 | 163 | |
3f69c0c1 RK |
164 | tst r1, #L_PTE_YOUNG |
165 | tstne r1, #L_PTE_PRESENT | |
bbe88886 CM |
166 | moveq r3, #0 |
167 | ||
874d5d3c DM |
168 | ARM( str r3, [r0, #2048]! ) |
169 | THUMB( add r0, r0, #2048 ) | |
170 | THUMB( str r3, [r0] ) | |
bbe88886 | 171 | mcr p15, 0, r0, c7, c10, 1 @ flush_pte |
2eb8c82b | 172 | #endif |
bbe88886 | 173 | mov pc, lr |
93ed3970 | 174 | ENDPROC(cpu_v7_set_pte_ext) |
bbe88886 | 175 | |
78a8f3c3 | 176 | string cpu_v7_name, "ARMv7 Processor" |
bbe88886 CM |
177 | .align |
178 | ||
f6b0fa02 RK |
179 | /* |
180 | * Memory region attributes with SCTLR.TRE=1 | |
181 | * | |
182 | * n = TEX[0],C,B | |
183 | * TR = PRRR[2n+1:2n] - memory type | |
184 | * IR = NMRR[2n+1:2n] - inner cacheable property | |
185 | * OR = NMRR[2n+17:2n+16] - outer cacheable property | |
186 | * | |
187 | * n TR IR OR | |
188 | * UNCACHED 000 00 | |
189 | * BUFFERABLE 001 10 00 00 | |
190 | * WRITETHROUGH 010 10 10 10 | |
191 | * WRITEBACK 011 10 11 11 | |
192 | * reserved 110 | |
193 | * WRITEALLOC 111 10 01 01 | |
194 | * DEV_SHARED 100 01 | |
195 | * DEV_NONSHARED 100 01 | |
196 | * DEV_WC 001 10 | |
197 | * DEV_CACHED 011 10 | |
198 | * | |
199 | * Other attributes: | |
200 | * | |
201 | * DS0 = PRRR[16] = 0 - device shareable property | |
202 | * DS1 = PRRR[17] = 1 - device shareable property | |
203 | * NS0 = PRRR[18] = 0 - normal shareable property | |
204 | * NS1 = PRRR[19] = 1 - normal shareable property | |
205 | * NOS = PRRR[24+n] = 1 - not outer shareable | |
206 | */ | |
207 | .equ PRRR, 0xff0a81a8 | |
208 | .equ NMRR, 0x40e040e0 | |
209 | ||
210 | /* Suspend/resume support: derived from arch/arm/mach-s5pv210/sleep.S */ | |
211 | .globl cpu_v7_suspend_size | |
111b20d0 | 212 | .equ cpu_v7_suspend_size, 4 * 9 |
29ea23ff | 213 | #ifdef CONFIG_PM_SLEEP |
f6b0fa02 RK |
214 | ENTRY(cpu_v7_do_suspend) |
215 | stmfd sp!, {r4 - r11, lr} | |
216 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID | |
217 | mrc p15, 0, r5, c13, c0, 1 @ Context ID | |
111b20d0 RK |
218 | mrc p15, 0, r6, c13, c0, 3 @ User r/o thread ID |
219 | stmia r0!, {r4 - r6} | |
f6b0fa02 RK |
220 | mrc p15, 0, r6, c3, c0, 0 @ Domain ID |
221 | mrc p15, 0, r7, c2, c0, 0 @ TTB 0 | |
222 | mrc p15, 0, r8, c2, c0, 1 @ TTB 1 | |
223 | mrc p15, 0, r9, c1, c0, 0 @ Control register | |
224 | mrc p15, 0, r10, c1, c0, 1 @ Auxiliary control register | |
225 | mrc p15, 0, r11, c1, c0, 2 @ Co-processor access control | |
111b20d0 | 226 | stmia r0, {r6 - r11} |
f6b0fa02 RK |
227 | ldmfd sp!, {r4 - r11, pc} |
228 | ENDPROC(cpu_v7_do_suspend) | |
229 | ||
230 | ENTRY(cpu_v7_do_resume) | |
231 | mov ip, #0 | |
232 | mcr p15, 0, ip, c8, c7, 0 @ invalidate TLBs | |
233 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
111b20d0 | 234 | ldmia r0!, {r4 - r6} |
f6b0fa02 RK |
235 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID |
236 | mcr p15, 0, r5, c13, c0, 1 @ Context ID | |
111b20d0 RK |
237 | mcr p15, 0, r6, c13, c0, 3 @ User r/o thread ID |
238 | ldmia r0, {r6 - r11} | |
f6b0fa02 RK |
239 | mcr p15, 0, r6, c3, c0, 0 @ Domain ID |
240 | mcr p15, 0, r7, c2, c0, 0 @ TTB 0 | |
241 | mcr p15, 0, r8, c2, c0, 1 @ TTB 1 | |
242 | mcr p15, 0, ip, c2, c0, 2 @ TTB control register | |
25985edc | 243 | mcr p15, 0, r10, c1, c0, 1 @ Auxiliary control register |
f6b0fa02 RK |
244 | mcr p15, 0, r11, c1, c0, 2 @ Co-processor access control |
245 | ldr r4, =PRRR @ PRRR | |
246 | ldr r5, =NMRR @ NMRR | |
247 | mcr p15, 0, r4, c10, c2, 0 @ write PRRR | |
248 | mcr p15, 0, r5, c10, c2, 1 @ write NMRR | |
249 | isb | |
250 | mov r0, r9 @ control register | |
251 | mov r2, r7, lsr #14 @ get TTB0 base | |
252 | mov r2, r2, lsl #14 | |
253 | ldr r3, cpu_resume_l1_flags | |
254 | b cpu_resume_mmu | |
255 | ENDPROC(cpu_v7_do_resume) | |
256 | cpu_resume_l1_flags: | |
257 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP) | |
258 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP) | |
259 | #else | |
260 | #define cpu_v7_do_suspend 0 | |
261 | #define cpu_v7_do_resume 0 | |
262 | #endif | |
263 | ||
5085f3ff | 264 | __CPUINIT |
bbe88886 CM |
265 | |
266 | /* | |
267 | * __v7_setup | |
268 | * | |
269 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | |
270 | * on. Return in r0 the new CP15 C1 control register setting. | |
271 | * | |
272 | * We automatically detect if we have a Harvard cache, and use the | |
273 | * Harvard cache control instructions insead of the unified cache | |
274 | * control instructions. | |
275 | * | |
276 | * This should be able to cover all ARMv7 cores. | |
277 | * | |
278 | * It is assumed that: | |
279 | * - cache type register is implemented | |
280 | */ | |
14eff181 | 281 | __v7_ca9mp_setup: |
73b63efa | 282 | #ifdef CONFIG_SMP |
f00ec48f RK |
283 | ALT_SMP(mrc p15, 0, r0, c1, c0, 1) |
284 | ALT_UP(mov r0, #(1 << 6)) @ fake it for UP | |
1b3a02eb TT |
285 | tst r0, #(1 << 6) @ SMP/nAMP mode enabled? |
286 | orreq r0, r0, #(1 << 6) | (1 << 0) @ Enable SMP/nAMP mode and | |
287 | mcreq p15, 0, r0, c1, c0, 1 @ TLB ops broadcasting | |
73b63efa | 288 | #endif |
14eff181 | 289 | __v7_setup: |
bbe88886 CM |
290 | adr r12, __v7_setup_stack @ the local stack |
291 | stmia r12, {r0-r5, r7, r9, r11, lr} | |
292 | bl v7_flush_dcache_all | |
293 | ldmia r12, {r0-r5, r7, r9, r11, lr} | |
1946d6ef RK |
294 | |
295 | mrc p15, 0, r0, c0, c0, 0 @ read main ID register | |
296 | and r10, r0, #0xff000000 @ ARM? | |
297 | teq r10, #0x41000000 | |
9f05027c | 298 | bne 3f |
1946d6ef RK |
299 | and r5, r0, #0x00f00000 @ variant |
300 | and r6, r0, #0x0000000f @ revision | |
6491848d WD |
301 | orr r6, r6, r5, lsr #20-4 @ combine variant and revision |
302 | ubfx r0, r0, #4, #12 @ primary part number | |
1946d6ef | 303 | |
6491848d WD |
304 | /* Cortex-A8 Errata */ |
305 | ldr r10, =0x00000c08 @ Cortex-A8 primary part number | |
306 | teq r0, r10 | |
307 | bne 2f | |
7ce236fc | 308 | #ifdef CONFIG_ARM_ERRATA_430973 |
1946d6ef RK |
309 | teq r5, #0x00100000 @ only present in r1p* |
310 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register | |
311 | orreq r10, r10, #(1 << 6) @ set IBE to 1 | |
312 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register | |
855c551f CM |
313 | #endif |
314 | #ifdef CONFIG_ARM_ERRATA_458693 | |
6491848d | 315 | teq r6, #0x20 @ only present in r2p0 |
1946d6ef RK |
316 | mrceq p15, 0, r10, c1, c0, 1 @ read aux control register |
317 | orreq r10, r10, #(1 << 5) @ set L1NEON to 1 | |
318 | orreq r10, r10, #(1 << 9) @ set PLDNOP to 1 | |
319 | mcreq p15, 0, r10, c1, c0, 1 @ write aux control register | |
0516e464 CM |
320 | #endif |
321 | #ifdef CONFIG_ARM_ERRATA_460075 | |
6491848d | 322 | teq r6, #0x20 @ only present in r2p0 |
1946d6ef RK |
323 | mrceq p15, 1, r10, c9, c0, 2 @ read L2 cache aux ctrl register |
324 | tsteq r10, #1 << 22 | |
325 | orreq r10, r10, #(1 << 22) @ set the Write Allocate disable bit | |
326 | mcreq p15, 1, r10, c9, c0, 2 @ write the L2 cache aux ctrl register | |
7ce236fc | 327 | #endif |
9f05027c WD |
328 | b 3f |
329 | ||
330 | /* Cortex-A9 Errata */ | |
331 | 2: ldr r10, =0x00000c09 @ Cortex-A9 primary part number | |
332 | teq r0, r10 | |
333 | bne 3f | |
334 | #ifdef CONFIG_ARM_ERRATA_742230 | |
335 | cmp r6, #0x22 @ only present up to r2p2 | |
336 | mrcle p15, 0, r10, c15, c0, 1 @ read diagnostic register | |
337 | orrle r10, r10, #1 << 4 @ set bit #4 | |
338 | mcrle p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
339 | #endif | |
a672e99b WD |
340 | #ifdef CONFIG_ARM_ERRATA_742231 |
341 | teq r6, #0x20 @ present in r2p0 | |
342 | teqne r6, #0x21 @ present in r2p1 | |
343 | teqne r6, #0x22 @ present in r2p2 | |
344 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register | |
345 | orreq r10, r10, #1 << 12 @ set bit #12 | |
346 | orreq r10, r10, #1 << 22 @ set bit #22 | |
347 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
348 | #endif | |
475d92fc WD |
349 | #ifdef CONFIG_ARM_ERRATA_743622 |
350 | teq r6, #0x20 @ present in r2p0 | |
351 | teqne r6, #0x21 @ present in r2p1 | |
352 | teqne r6, #0x22 @ present in r2p2 | |
353 | mrceq p15, 0, r10, c15, c0, 1 @ read diagnostic register | |
354 | orreq r10, r10, #1 << 6 @ set bit #6 | |
355 | mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
356 | #endif | |
9a27c27c WD |
357 | #ifdef CONFIG_ARM_ERRATA_751472 |
358 | cmp r6, #0x30 @ present prior to r3p0 | |
359 | mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register | |
360 | orrlt r10, r10, #1 << 11 @ set bit #11 | |
361 | mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register | |
362 | #endif | |
1946d6ef | 363 | |
9f05027c | 364 | 3: mov r10, #0 |
bbe88886 CM |
365 | #ifdef HARVARD_CACHE |
366 | mcr p15, 0, r10, c7, c5, 0 @ I+BTB cache invalidate | |
367 | #endif | |
368 | dsb | |
2eb8c82b | 369 | #ifdef CONFIG_MMU |
bbe88886 CM |
370 | mcr p15, 0, r10, c8, c7, 0 @ invalidate I + D TLBs |
371 | mcr p15, 0, r10, c2, c0, 2 @ TTB control register | |
f00ec48f RK |
372 | ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) |
373 | ALT_UP(orr r4, r4, #TTB_FLAGS_UP) | |
d427958a CM |
374 | ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) |
375 | ALT_UP(orr r8, r8, #TTB_FLAGS_UP) | |
376 | mcr p15, 0, r8, c2, c0, 1 @ load TTB1 | |
f6b0fa02 RK |
377 | ldr r5, =PRRR @ PRRR |
378 | ldr r6, =NMRR @ NMRR | |
3f69c0c1 RK |
379 | mcr p15, 0, r5, c10, c2, 0 @ write PRRR |
380 | mcr p15, 0, r6, c10, c2, 1 @ write NMRR | |
bdaaaec3 | 381 | #endif |
2eb8c82b CM |
382 | adr r5, v7_crval |
383 | ldmia r5, {r5, r6} | |
26584853 CM |
384 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
385 | orr r6, r6, #1 << 25 @ big-endian page tables | |
64d2dc38 LL |
386 | #endif |
387 | #ifdef CONFIG_SWP_EMULATE | |
388 | orr r5, r5, #(1 << 10) @ set SW bit in "clear" | |
389 | bic r6, r6, #(1 << 10) @ clear it in "mmuset" | |
26584853 | 390 | #endif |
2eb8c82b CM |
391 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
392 | bic r0, r0, r5 @ clear bits them | |
393 | orr r0, r0, r6 @ set them | |
347c8b70 | 394 | THUMB( orr r0, r0, #1 << 30 ) @ Thumb exceptions |
bbe88886 | 395 | mov pc, lr @ return to head.S:__ret |
93ed3970 | 396 | ENDPROC(__v7_setup) |
bbe88886 | 397 | |
b1cce6b1 | 398 | /* AT |
213fb2a8 CM |
399 | * TFR EV X F I D LR S |
400 | * .EEE ..EE PUI. .T.T 4RVI ZWRS BLDP WCAM | |
b1cce6b1 | 401 | * rxxx rrxx xxx0 0101 xxxx xxxx x111 xxxx < forced |
213fb2a8 | 402 | * 1 0 110 0011 1100 .111 1101 < we want |
bbe88886 | 403 | */ |
2eb8c82b CM |
404 | .type v7_crval, #object |
405 | v7_crval: | |
213fb2a8 | 406 | crval clear=0x0120c302, mmuset=0x10c03c7d, ucset=0x00c01c7c |
bbe88886 CM |
407 | |
408 | __v7_setup_stack: | |
409 | .space 4 * 11 @ 11 registers | |
410 | ||
5085f3ff RK |
411 | __INITDATA |
412 | ||
78a8f3c3 DM |
413 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
414 | define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1 | |
bbe88886 | 415 | |
5085f3ff RK |
416 | .section ".rodata" |
417 | ||
78a8f3c3 DM |
418 | string cpu_arch_name, "armv7" |
419 | string cpu_elf_name, "v7" | |
bbe88886 CM |
420 | .align |
421 | ||
422 | .section ".proc.info.init", #alloc, #execinstr | |
423 | ||
dc939cd8 PM |
424 | /* |
425 | * Standard v7 proc info content | |
426 | */ | |
427 | .macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0 | |
428 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ | |
429 | PMD_FLAGS_SMP | \mm_mmuflags) | |
430 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \ | |
431 | PMD_FLAGS_UP | \mm_mmuflags) | |
432 | .long PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_AP_WRITE | \ | |
433 | PMD_SECT_AP_READ | \io_mmuflags | |
434 | W(b) \initfunc | |
14eff181 DW |
435 | .long cpu_arch_name |
436 | .long cpu_elf_name | |
dc939cd8 PM |
437 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \ |
438 | HWCAP_EDSP | HWCAP_TLS | \hwcaps | |
14eff181 DW |
439 | .long cpu_v7_name |
440 | .long v7_processor_functions | |
441 | .long v7wbi_tlb_fns | |
442 | .long v6_user_fns | |
443 | .long v7_cache_fns | |
dc939cd8 PM |
444 | .endm |
445 | ||
446 | /* | |
447 | * ARM Ltd. Cortex A9 processor. | |
448 | */ | |
449 | .type __v7_ca9mp_proc_info, #object | |
450 | __v7_ca9mp_proc_info: | |
451 | .long 0x410fc090 | |
452 | .long 0xff0ffff0 | |
453 | __v7_proc __v7_ca9mp_setup | |
14eff181 DW |
454 | .size __v7_ca9mp_proc_info, . - __v7_ca9mp_proc_info |
455 | ||
bbe88886 CM |
456 | /* |
457 | * Match any ARMv7 processor core. | |
458 | */ | |
459 | .type __v7_proc_info, #object | |
460 | __v7_proc_info: | |
461 | .long 0x000f0000 @ Required ID value | |
462 | .long 0x000f0000 @ Mask for ID | |
dc939cd8 | 463 | __v7_proc __v7_setup |
bbe88886 | 464 | .size __v7_proc_info, . - __v7_proc_info |