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23bdf86a LB |
1 | /* |
2 | * linux/arch/arm/mm/proc-xsc3.S | |
3 | * | |
4 | * Original Author: Matthew Gilbert | |
57fee39f | 5 | * Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org> |
23bdf86a LB |
6 | * |
7 | * Copyright 2004 (C) Intel Corp. | |
850b4293 | 8 | * Copyright 2005 (C) MontaVista Software, Inc. |
23bdf86a LB |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | * | |
850b4293 LB |
14 | * MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is |
15 | * an extension to Intel's original XScale core that adds the following | |
23bdf86a LB |
16 | * features: |
17 | * | |
18 | * - ARMv6 Supersections | |
19 | * - Low Locality Reference pages (replaces mini-cache) | |
20 | * - 36-bit addressing | |
21 | * - L2 cache | |
850b4293 | 22 | * - Cache coherency if chipset supports it |
23bdf86a | 23 | * |
850b4293 | 24 | * Based on original XScale code by Nicolas Pitre. |
23bdf86a LB |
25 | */ |
26 | ||
27 | #include <linux/linkage.h> | |
28 | #include <linux/init.h> | |
29 | #include <asm/assembler.h> | |
5ec9407d | 30 | #include <asm/hwcap.h> |
a09e64fb | 31 | #include <mach/hardware.h> |
23bdf86a | 32 | #include <asm/pgtable.h> |
b48340af | 33 | #include <asm/pgtable-hwdef.h> |
23bdf86a LB |
34 | #include <asm/page.h> |
35 | #include <asm/ptrace.h> | |
36 | #include "proc-macros.S" | |
37 | ||
38 | /* | |
39 | * This is the maximum size of an area which will be flushed. If the | |
40 | * area is larger than this, then we flush the whole cache. | |
41 | */ | |
42 | #define MAX_AREA_SIZE 32768 | |
43 | ||
44 | /* | |
850b4293 | 45 | * The cache line size of the L1 I, L1 D and unified L2 cache. |
23bdf86a LB |
46 | */ |
47 | #define CACHELINESIZE 32 | |
48 | ||
49 | /* | |
850b4293 | 50 | * The size of the L1 D cache. |
23bdf86a LB |
51 | */ |
52 | #define CACHESIZE 32768 | |
53 | ||
23bdf86a | 54 | /* |
850b4293 LB |
55 | * This macro is used to wait for a CP15 write and is needed when we |
56 | * have to ensure that the last operation to the coprocessor was | |
57 | * completed before continuing with operation. | |
23bdf86a LB |
58 | */ |
59 | .macro cpwait_ret, lr, rd | |
60 | mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15 | |
61 | sub pc, \lr, \rd, LSR #32 @ wait for completion and | |
62 | @ flush instruction pipeline | |
63 | .endm | |
64 | ||
65 | /* | |
850b4293 | 66 | * This macro cleans and invalidates the entire L1 D cache. |
23bdf86a LB |
67 | */ |
68 | ||
69 | .macro clean_d_cache rd, rs | |
70 | mov \rd, #0x1f00 | |
71 | orr \rd, \rd, #0x00e0 | |
850b4293 | 72 | 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line |
23bdf86a LB |
73 | adds \rd, \rd, #0x40000000 |
74 | bcc 1b | |
75 | subs \rd, \rd, #0x20 | |
76 | bpl 1b | |
77 | .endm | |
78 | ||
79 | .text | |
80 | ||
81 | /* | |
82 | * cpu_xsc3_proc_init() | |
83 | * | |
84 | * Nothing too exciting at the moment | |
85 | */ | |
86 | ENTRY(cpu_xsc3_proc_init) | |
87 | mov pc, lr | |
88 | ||
89 | /* | |
90 | * cpu_xsc3_proc_fin() | |
91 | */ | |
92 | ENTRY(cpu_xsc3_proc_fin) | |
93 | str lr, [sp, #-4]! | |
94 | mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE | |
95 | msr cpsr_c, r0 | |
96 | bl xsc3_flush_kern_cache_all @ clean caches | |
97 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | |
98 | bic r0, r0, #0x1800 @ ...IZ........... | |
99 | bic r0, r0, #0x0006 @ .............CA. | |
100 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
101 | ldr pc, [sp], #4 | |
102 | ||
103 | /* | |
104 | * cpu_xsc3_reset(loc) | |
105 | * | |
106 | * Perform a soft reset of the system. Put the CPU into the | |
107 | * same state as it would be if it had been reset, and branch | |
108 | * to what would be the reset vector. | |
109 | * | |
110 | * loc: location to jump to for soft reset | |
111 | */ | |
112 | .align 5 | |
113 | ENTRY(cpu_xsc3_reset) | |
114 | mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE | |
115 | msr cpsr_c, r1 @ reset CPSR | |
116 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register | |
23bdf86a | 117 | bic r1, r1, #0x3900 @ ..VIZ..S........ |
850b4293 | 118 | bic r1, r1, #0x0086 @ ........B....CA. |
23bdf86a | 119 | mcr p15, 0, r1, c1, c0, 0 @ ctrl register |
850b4293 | 120 | mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB |
23bdf86a LB |
121 | bic r1, r1, #0x0001 @ ...............M |
122 | mcr p15, 0, r1, c1, c0, 0 @ ctrl register | |
123 | @ CAUTION: MMU turned off from this point. We count on the pipeline | |
124 | @ already containing those two last instructions to survive. | |
850b4293 | 125 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs |
23bdf86a LB |
126 | mov pc, r0 |
127 | ||
128 | /* | |
129 | * cpu_xsc3_do_idle() | |
130 | * | |
131 | * Cause the processor to idle | |
132 | * | |
133 | * For now we do nothing but go to idle mode for every case | |
134 | * | |
135 | * XScale supports clock switching, but using idle mode support | |
136 | * allows external hardware to react to system state changes. | |
23bdf86a LB |
137 | */ |
138 | .align 5 | |
139 | ||
140 | ENTRY(cpu_xsc3_do_idle) | |
141 | mov r0, #1 | |
850b4293 | 142 | mcr p14, 0, r0, c7, c0, 0 @ go to idle |
23bdf86a LB |
143 | mov pc, lr |
144 | ||
145 | /* ================================= CACHE ================================ */ | |
146 | ||
147 | /* | |
148 | * flush_user_cache_all() | |
149 | * | |
150 | * Invalidate all cache entries in a particular address | |
151 | * space. | |
152 | */ | |
153 | ENTRY(xsc3_flush_user_cache_all) | |
154 | /* FALLTHROUGH */ | |
155 | ||
156 | /* | |
157 | * flush_kern_cache_all() | |
158 | * | |
159 | * Clean and invalidate the entire cache. | |
160 | */ | |
161 | ENTRY(xsc3_flush_kern_cache_all) | |
162 | mov r2, #VM_EXEC | |
163 | mov ip, #0 | |
164 | __flush_whole_cache: | |
165 | clean_d_cache r0, r1 | |
166 | tst r2, #VM_EXEC | |
850b4293 LB |
167 | mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB |
168 | mcrne p15, 0, ip, c7, c10, 4 @ data write barrier | |
169 | mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush | |
23bdf86a LB |
170 | mov pc, lr |
171 | ||
172 | /* | |
173 | * flush_user_cache_range(start, end, vm_flags) | |
174 | * | |
175 | * Invalidate a range of cache entries in the specified | |
176 | * address space. | |
177 | * | |
178 | * - start - start address (may not be aligned) | |
179 | * - end - end address (exclusive, may not be aligned) | |
180 | * - vma - vma_area_struct describing address space | |
181 | */ | |
182 | .align 5 | |
183 | ENTRY(xsc3_flush_user_cache_range) | |
184 | mov ip, #0 | |
185 | sub r3, r1, r0 @ calculate total size | |
186 | cmp r3, #MAX_AREA_SIZE | |
187 | bhs __flush_whole_cache | |
188 | ||
189 | 1: tst r2, #VM_EXEC | |
850b4293 LB |
190 | mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line |
191 | mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line | |
23bdf86a LB |
192 | add r0, r0, #CACHELINESIZE |
193 | cmp r0, r1 | |
194 | blo 1b | |
195 | tst r2, #VM_EXEC | |
850b4293 LB |
196 | mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB |
197 | mcrne p15, 0, ip, c7, c10, 4 @ data write barrier | |
198 | mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush | |
23bdf86a LB |
199 | mov pc, lr |
200 | ||
201 | /* | |
202 | * coherent_kern_range(start, end) | |
203 | * | |
850b4293 | 204 | * Ensure coherency between the I cache and the D cache in the |
23bdf86a LB |
205 | * region described by start. If you have non-snooping |
206 | * Harvard caches, you need to implement this function. | |
207 | * | |
208 | * - start - virtual start address | |
209 | * - end - virtual end address | |
210 | * | |
211 | * Note: single I-cache line invalidation isn't used here since | |
212 | * it also trashes the mini I-cache used by JTAG debuggers. | |
213 | */ | |
214 | ENTRY(xsc3_coherent_kern_range) | |
215 | /* FALLTHROUGH */ | |
216 | ENTRY(xsc3_coherent_user_range) | |
217 | bic r0, r0, #CACHELINESIZE - 1 | |
850b4293 | 218 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line |
23bdf86a LB |
219 | add r0, r0, #CACHELINESIZE |
220 | cmp r0, r1 | |
221 | blo 1b | |
222 | mov r0, #0 | |
850b4293 LB |
223 | mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB |
224 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | |
225 | mcr p15, 0, r0, c7, c5, 4 @ prefetch flush | |
23bdf86a LB |
226 | mov pc, lr |
227 | ||
228 | /* | |
2c9b9c84 | 229 | * flush_kern_dcache_area(void *addr, size_t size) |
23bdf86a LB |
230 | * |
231 | * Ensure no D cache aliasing occurs, either with itself or | |
850b4293 | 232 | * the I cache. |
23bdf86a | 233 | * |
2c9b9c84 RK |
234 | * - addr - kernel address |
235 | * - size - region size | |
23bdf86a | 236 | */ |
2c9b9c84 RK |
237 | ENTRY(xsc3_flush_kern_dcache_area) |
238 | add r1, r0, r1 | |
850b4293 | 239 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line |
23bdf86a LB |
240 | add r0, r0, #CACHELINESIZE |
241 | cmp r0, r1 | |
242 | blo 1b | |
243 | mov r0, #0 | |
850b4293 LB |
244 | mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB |
245 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier | |
246 | mcr p15, 0, r0, c7, c5, 4 @ prefetch flush | |
23bdf86a LB |
247 | mov pc, lr |
248 | ||
249 | /* | |
250 | * dma_inv_range(start, end) | |
251 | * | |
252 | * Invalidate (discard) the specified virtual address range. | |
253 | * May not write back any entries. If 'start' or 'end' | |
254 | * are not cache line aligned, those lines must be written | |
255 | * back. | |
256 | * | |
257 | * - start - virtual start address | |
258 | * - end - virtual end address | |
259 | */ | |
260 | ENTRY(xsc3_dma_inv_range) | |
261 | tst r0, #CACHELINESIZE - 1 | |
262 | bic r0, r0, #CACHELINESIZE - 1 | |
850b4293 | 263 | mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line |
23bdf86a | 264 | tst r1, #CACHELINESIZE - 1 |
850b4293 | 265 | mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line |
850b4293 | 266 | 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line |
23bdf86a LB |
267 | add r0, r0, #CACHELINESIZE |
268 | cmp r0, r1 | |
269 | blo 1b | |
850b4293 | 270 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier |
23bdf86a LB |
271 | mov pc, lr |
272 | ||
273 | /* | |
274 | * dma_clean_range(start, end) | |
275 | * | |
276 | * Clean the specified virtual address range. | |
277 | * | |
278 | * - start - virtual start address | |
279 | * - end - virtual end address | |
280 | */ | |
281 | ENTRY(xsc3_dma_clean_range) | |
282 | bic r0, r0, #CACHELINESIZE - 1 | |
850b4293 | 283 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line |
23bdf86a LB |
284 | add r0, r0, #CACHELINESIZE |
285 | cmp r0, r1 | |
286 | blo 1b | |
850b4293 | 287 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier |
23bdf86a LB |
288 | mov pc, lr |
289 | ||
290 | /* | |
291 | * dma_flush_range(start, end) | |
292 | * | |
293 | * Clean and invalidate the specified virtual address range. | |
294 | * | |
295 | * - start - virtual start address | |
296 | * - end - virtual end address | |
297 | */ | |
298 | ENTRY(xsc3_dma_flush_range) | |
299 | bic r0, r0, #CACHELINESIZE - 1 | |
850b4293 | 300 | 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line |
23bdf86a LB |
301 | add r0, r0, #CACHELINESIZE |
302 | cmp r0, r1 | |
303 | blo 1b | |
850b4293 | 304 | mcr p15, 0, r0, c7, c10, 4 @ data write barrier |
23bdf86a LB |
305 | mov pc, lr |
306 | ||
a9c9147e RK |
307 | /* |
308 | * dma_map_area(start, size, dir) | |
309 | * - start - kernel virtual start address | |
310 | * - size - size of region | |
311 | * - dir - DMA direction | |
312 | */ | |
313 | ENTRY(xsc3_dma_map_area) | |
314 | add r1, r1, r0 | |
315 | cmp r2, #DMA_TO_DEVICE | |
316 | beq xsc3_dma_clean_range | |
317 | bcs xsc3_dma_inv_range | |
318 | b xsc3_dma_flush_range | |
319 | ENDPROC(xsc3_dma_map_area) | |
320 | ||
321 | /* | |
322 | * dma_unmap_area(start, size, dir) | |
323 | * - start - kernel virtual start address | |
324 | * - size - size of region | |
325 | * - dir - DMA direction | |
326 | */ | |
327 | ENTRY(xsc3_dma_unmap_area) | |
328 | mov pc, lr | |
329 | ENDPROC(xsc3_dma_unmap_area) | |
330 | ||
23bdf86a LB |
331 | ENTRY(xsc3_cache_fns) |
332 | .long xsc3_flush_kern_cache_all | |
333 | .long xsc3_flush_user_cache_all | |
334 | .long xsc3_flush_user_cache_range | |
335 | .long xsc3_coherent_kern_range | |
336 | .long xsc3_coherent_user_range | |
2c9b9c84 | 337 | .long xsc3_flush_kern_dcache_area |
a9c9147e RK |
338 | .long xsc3_dma_map_area |
339 | .long xsc3_dma_unmap_area | |
23bdf86a LB |
340 | .long xsc3_dma_inv_range |
341 | .long xsc3_dma_clean_range | |
342 | .long xsc3_dma_flush_range | |
343 | ||
344 | ENTRY(cpu_xsc3_dcache_clean_area) | |
850b4293 | 345 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line |
23bdf86a LB |
346 | add r0, r0, #CACHELINESIZE |
347 | subs r1, r1, #CACHELINESIZE | |
348 | bhi 1b | |
349 | mov pc, lr | |
350 | ||
351 | /* =============================== PageTable ============================== */ | |
352 | ||
353 | /* | |
354 | * cpu_xsc3_switch_mm(pgd) | |
355 | * | |
356 | * Set the translation base pointer to be as described by pgd. | |
357 | * | |
358 | * pgd: new page tables | |
359 | */ | |
360 | .align 5 | |
361 | ENTRY(cpu_xsc3_switch_mm) | |
362 | clean_d_cache r1, r2 | |
850b4293 LB |
363 | mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB |
364 | mcr p15, 0, ip, c7, c10, 4 @ data write barrier | |
365 | mcr p15, 0, ip, c7, c5, 4 @ prefetch flush | |
23bdf86a | 366 | orr r0, r0, #0x18 @ cache the page table in L2 |
23bdf86a | 367 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
850b4293 | 368 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs |
23bdf86a LB |
369 | cpwait_ret lr, ip |
370 | ||
371 | /* | |
ad1ae2fe | 372 | * cpu_xsc3_set_pte_ext(ptep, pte, ext) |
23bdf86a LB |
373 | * |
374 | * Set a PTE and flush it out | |
23bdf86a | 375 | */ |
9e8b5199 RK |
376 | cpu_xsc3_mt_table: |
377 | .long 0x00 @ L_PTE_MT_UNCACHED | |
40df2d1d | 378 | .long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE |
6bee00db | 379 | .long PTE_EXT_TEX(5) | PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH |
40df2d1d RK |
380 | .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK |
381 | .long PTE_EXT_TEX(1) | PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED | |
639b0ae7 | 382 | .long 0x00 @ unused |
9e8b5199 RK |
383 | .long 0x00 @ L_PTE_MT_MINICACHE (not present) |
384 | .long PTE_EXT_TEX(5) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC (not present?) | |
639b0ae7 | 385 | .long 0x00 @ unused |
9e8b5199 RK |
386 | .long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC |
387 | .long 0x00 @ unused | |
40df2d1d RK |
388 | .long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED |
389 | .long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED | |
db5b7169 | 390 | .long 0x00 @ unused |
9e8b5199 RK |
391 | .long 0x00 @ unused |
392 | .long 0x00 @ unused | |
393 | ||
23bdf86a | 394 | .align 5 |
ad1ae2fe | 395 | ENTRY(cpu_xsc3_set_pte_ext) |
da091653 | 396 | xscale_set_pte_ext_prologue |
23bdf86a | 397 | |
da091653 | 398 | tst r1, #L_PTE_SHARED @ shared? |
9e8b5199 RK |
399 | and r1, r1, #L_PTE_MT_MASK |
400 | adr ip, cpu_xsc3_mt_table | |
401 | ldr ip, [ip, r1] | |
402 | orrne r2, r2, #PTE_EXT_COHERENT @ interlock: mask in coherent bit | |
403 | bic r2, r2, #0x0c @ clear old C,B bits | |
404 | orr r2, r2, ip | |
23bdf86a | 405 | |
da091653 | 406 | xscale_set_pte_ext_epilogue |
23bdf86a LB |
407 | mov pc, lr |
408 | ||
409 | .ltorg | |
410 | ||
411 | .align | |
412 | ||
413 | __INIT | |
414 | ||
415 | .type __xsc3_setup, #function | |
416 | __xsc3_setup: | |
417 | mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE | |
418 | msr cpsr_c, r0 | |
850b4293 LB |
419 | mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB |
420 | mcr p15, 0, ip, c7, c10, 4 @ data write barrier | |
421 | mcr p15, 0, ip, c7, c5, 4 @ prefetch flush | |
422 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs | |
23bdf86a | 423 | orr r4, r4, #0x18 @ cache the page table in L2 |
23bdf86a | 424 | mcr p15, 0, r4, c2, c0, 0 @ load page table pointer |
850b4293 | 425 | |
345a3229 | 426 | mov r0, #1 << 6 @ cp6 access for early sched_clock |
850b4293 LB |
427 | mcr p15, 0, r0, c15, c1, 0 @ write CP access register |
428 | ||
23bdf86a LB |
429 | mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg |
430 | and r0, r0, #2 @ preserve bit P bit setting | |
23bdf86a | 431 | orr r0, r0, #(1 << 10) @ enable L2 for LLR cache |
23bdf86a | 432 | mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg |
22b19086 RK |
433 | |
434 | adr r5, xsc3_crval | |
435 | ldmia r5, {r5, r6} | |
23bdf86a | 436 | mrc p15, 0, r0, c1, c0, 0 @ get control register |
850b4293 LB |
437 | bic r0, r0, r5 @ ..V. ..R. .... ..A. |
438 | orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu) | |
439 | @ ...I Z..S .... .... (uc) | |
23bdf86a LB |
440 | mov pc, lr |
441 | ||
442 | .size __xsc3_setup, . - __xsc3_setup | |
443 | ||
22b19086 RK |
444 | .type xsc3_crval, #object |
445 | xsc3_crval: | |
850b4293 | 446 | crval clear=0x04002202, mmuset=0x00003905, ucset=0x00001900 |
22b19086 | 447 | |
23bdf86a LB |
448 | __INITDATA |
449 | ||
450 | /* | |
451 | * Purpose : Function pointers used to access above functions - all calls | |
452 | * come through these | |
453 | */ | |
454 | ||
455 | .type xsc3_processor_functions, #object | |
456 | ENTRY(xsc3_processor_functions) | |
457 | .word v5t_early_abort | |
4fb28474 | 458 | .word legacy_pabort |
23bdf86a LB |
459 | .word cpu_xsc3_proc_init |
460 | .word cpu_xsc3_proc_fin | |
461 | .word cpu_xsc3_reset | |
462 | .word cpu_xsc3_do_idle | |
463 | .word cpu_xsc3_dcache_clean_area | |
464 | .word cpu_xsc3_switch_mm | |
ad1ae2fe | 465 | .word cpu_xsc3_set_pte_ext |
23bdf86a LB |
466 | .size xsc3_processor_functions, . - xsc3_processor_functions |
467 | ||
468 | .section ".rodata" | |
469 | ||
470 | .type cpu_arch_name, #object | |
471 | cpu_arch_name: | |
472 | .asciz "armv5te" | |
473 | .size cpu_arch_name, . - cpu_arch_name | |
474 | ||
475 | .type cpu_elf_name, #object | |
476 | cpu_elf_name: | |
477 | .asciz "v5" | |
478 | .size cpu_elf_name, . - cpu_elf_name | |
479 | ||
480 | .type cpu_xsc3_name, #object | |
481 | cpu_xsc3_name: | |
850b4293 | 482 | .asciz "XScale-V3 based processor" |
23bdf86a LB |
483 | .size cpu_xsc3_name, . - cpu_xsc3_name |
484 | ||
485 | .align | |
486 | ||
487 | .section ".proc.info.init", #alloc, #execinstr | |
488 | ||
489 | .type __xsc3_proc_info,#object | |
490 | __xsc3_proc_info: | |
491 | .long 0x69056000 | |
492 | .long 0xffffe000 | |
8799ee9f RK |
493 | .long PMD_TYPE_SECT | \ |
494 | PMD_SECT_BUFFERABLE | \ | |
495 | PMD_SECT_CACHEABLE | \ | |
496 | PMD_SECT_AP_WRITE | \ | |
497 | PMD_SECT_AP_READ | |
850b4293 | 498 | .long PMD_TYPE_SECT | \ |
8799ee9f RK |
499 | PMD_SECT_AP_WRITE | \ |
500 | PMD_SECT_AP_READ | |
23bdf86a LB |
501 | b __xsc3_setup |
502 | .long cpu_arch_name | |
503 | .long cpu_elf_name | |
504 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP | |
505 | .long cpu_xsc3_name | |
506 | .long xsc3_processor_functions | |
507 | .long v4wbi_tlb_fns | |
508 | .long xsc3_mc_user_fns | |
509 | .long xsc3_cache_fns | |
510 | .size __xsc3_proc_info, . - __xsc3_proc_info | |
59c7bcd4 EM |
511 | |
512 | /* Note: PXA935 changed its implementor ID from Intel to Marvell */ | |
513 | ||
514 | .type __xsc3_pxa935_proc_info,#object | |
515 | __xsc3_pxa935_proc_info: | |
516 | .long 0x56056000 | |
517 | .long 0xffffe000 | |
518 | .long PMD_TYPE_SECT | \ | |
519 | PMD_SECT_BUFFERABLE | \ | |
520 | PMD_SECT_CACHEABLE | \ | |
521 | PMD_SECT_AP_WRITE | \ | |
522 | PMD_SECT_AP_READ | |
523 | .long PMD_TYPE_SECT | \ | |
524 | PMD_SECT_AP_WRITE | \ | |
525 | PMD_SECT_AP_READ | |
526 | b __xsc3_setup | |
527 | .long cpu_arch_name | |
528 | .long cpu_elf_name | |
529 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP | |
530 | .long cpu_xsc3_name | |
531 | .long xsc3_processor_functions | |
532 | .long v4wbi_tlb_fns | |
533 | .long xsc3_mc_user_fns | |
534 | .long xsc3_cache_fns | |
535 | .size __xsc3_pxa935_proc_info, . - __xsc3_pxa935_proc_info |