]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - arch/arm/net/bpf_jit_32.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: net fix emit_udiv() for BPF_ALU | BPF_DIV | BPF_K intruction.
[mirror_ubuntu-artful-kernel.git] / arch / arm / net / bpf_jit_32.c
CommitLineData
ddecdfce
MG		 1/*
2 * Just-In-Time compiler for BPF filters on 32bit ARM
3 *
4 * Copyright (c) 2011 Mircea Gherzan <mgherzan@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/bitops.h>
12#include <linux/compiler.h>
13#include <linux/errno.h>
14#include <linux/filter.h>
ddecdfce
MG		 15#include <linux/netdevice.h>
16#include <linux/string.h>
17#include <linux/slab.h>
bf0098f2 18#include <linux/if_vlan.h>
e8b56d55 19
ddecdfce
MG		 20#include <asm/cacheflush.h>
21#include <asm/hwcap.h>
3460743e 22#include <asm/opcodes.h>
ddecdfce
MG		 23
24#include "bpf_jit_32.h"
25
26/*
27 * ABI:
28 *
29 * r0 scratch register
30 * r4 BPF register A
31 * r5 BPF register X
32 * r6 pointer to the skb
33 * r7 skb->data
34 * r8 skb_headlen(skb)
35 */
36
37#define r_scratch ARM_R0
38/* r1-r3 are (also) used for the unaligned loads on the non-ARMv7 slowpath */
39#define r_off ARM_R1
40#define r_A ARM_R4
41#define r_X ARM_R5
42#define r_skb ARM_R6
43#define r_skb_data ARM_R7
44#define r_skb_hl ARM_R8
45
46#define SCRATCH_SP_OFFSET 0
fe15f3f1 47#define SCRATCH_OFF(k) (SCRATCH_SP_OFFSET + 4 * (k))
ddecdfce
MG		 48
49#define SEEN_MEM ((1 << BPF_MEMWORDS) - 1)
50#define SEEN_MEM_WORD(k) (1 << (k))
51#define SEEN_X (1 << BPF_MEMWORDS)
52#define SEEN_CALL (1 << (BPF_MEMWORDS + 1))
53#define SEEN_SKB (1 << (BPF_MEMWORDS + 2))
54#define SEEN_DATA (1 << (BPF_MEMWORDS + 3))
55
56#define FLAG_NEED_X_RESET (1 << 0)
57
58struct jit_ctx {
7ae457c1 59 const struct bpf_prog *skf;
ddecdfce
MG		 60 unsigned idx;
61 unsigned prologue_bytes;
62 int ret0_fp_idx;
63 u32 seen;
64 u32 flags;
65 u32 *offsets;
66 u32 *target;
67#if __LINUX_ARM_ARCH__ < 7
68 u16 epilogue_bytes;
69 u16 imm_count;
70 u32 *imms;
71#endif
72};
73
74int bpf_jit_enable __read_mostly;
75
76static u64 jit_get_skb_b(struct sk_buff *skb, unsigned offset)
77{
78 u8 ret;
79 int err;
80
81 err = skb_copy_bits(skb, offset, &ret, 1);
82
83 return (u64)err << 32 | ret;
84}
85
86static u64 jit_get_skb_h(struct sk_buff *skb, unsigned offset)
87{
88 u16 ret;
89 int err;
90
91 err = skb_copy_bits(skb, offset, &ret, 2);
92
93 return (u64)err << 32 | ntohs(ret);
94}
95
96static u64 jit_get_skb_w(struct sk_buff *skb, unsigned offset)
97{
98 u32 ret;
99 int err;
100
101 err = skb_copy_bits(skb, offset, &ret, 4);
102
103 return (u64)err << 32 | ntohl(ret);
104}
105
106/*
107 * Wrapper that handles both OABI and EABI and assures Thumb2 interworking
108 * (where the assembly routines like __aeabi_uidiv could cause problems).
109 */
110static u32 jit_udiv(u32 dividend, u32 divisor)
111{
112 return dividend / divisor;
113}
114
115static inline void _emit(int cond, u32 inst, struct jit_ctx *ctx)
116{
3460743e
BD		 117 inst |= (cond << 28);
118 inst = __opcode_to_mem_arm(inst);
119
ddecdfce 120 if (ctx->target != NULL)
3460743e 121 ctx->target[ctx->idx] = inst;
ddecdfce
MG		 122
123 ctx->idx++;
124}
125
126/*
127 * Emit an instruction that will be executed unconditionally.
128 */
129static inline void emit(u32 inst, struct jit_ctx *ctx)
130{
131 _emit(ARM_COND_AL, inst, ctx);
132}
133
134static u16 saved_regs(struct jit_ctx *ctx)
135{
136 u16 ret = 0;
137
138 if ((ctx->skf->len > 1) ||
34805931 139 (ctx->skf->insns[0].code == (BPF_RET | BPF_A)))
ddecdfce
MG		 140 ret |= 1 << r_A;
141
142#ifdef CONFIG_FRAME_POINTER
143 ret |= (1 << ARM_FP) | (1 << ARM_IP) | (1 << ARM_LR) | (1 << ARM_PC);
144#else
145 if (ctx->seen & SEEN_CALL)
146 ret |= 1 << ARM_LR;
147#endif
148 if (ctx->seen & (SEEN_DATA | SEEN_SKB))
149 ret |= 1 << r_skb;
150 if (ctx->seen & SEEN_DATA)
151 ret |= (1 << r_skb_data) | (1 << r_skb_hl);
152 if (ctx->seen & SEEN_X)
153 ret |= 1 << r_X;
154
155 return ret;
156}
157
158static inline int mem_words_used(struct jit_ctx *ctx)
159{
160 /* yes, we do waste some stack space IF there are "holes" in the set" */
161 return fls(ctx->seen & SEEN_MEM);
162}
163
164static inline bool is_load_to_a(u16 inst)
165{
166 switch (inst) {
34805931
DB		 167 case BPF_LD | BPF_W | BPF_LEN:
168 case BPF_LD | BPF_W | BPF_ABS:
169 case BPF_LD | BPF_H | BPF_ABS:
170 case BPF_LD | BPF_B | BPF_ABS:
ddecdfce
MG		 171 return true;
172 default:
173 return false;
174 }
175}
176
55309dd3
DB		 177static void jit_fill_hole(void *area, unsigned int size)
178{
e8b56d55 179 u32 *ptr;
55309dd3
DB		 180 /* We are guaranteed to have aligned memory. */
181 for (ptr = area; size >= sizeof(u32); size -= sizeof(u32))
e8b56d55 182 *ptr++ = __opcode_to_mem_arm(ARM_INST_UDF);
55309dd3
DB		 183}
184
ddecdfce
MG		 185static void build_prologue(struct jit_ctx *ctx)
186{
187 u16 reg_set = saved_regs(ctx);
188 u16 first_inst = ctx->skf->insns[0].code;
189 u16 off;
190
191#ifdef CONFIG_FRAME_POINTER
192 emit(ARM_MOV_R(ARM_IP, ARM_SP), ctx);
193 emit(ARM_PUSH(reg_set), ctx);
194 emit(ARM_SUB_I(ARM_FP, ARM_IP, 4), ctx);
195#else
196 if (reg_set)
197 emit(ARM_PUSH(reg_set), ctx);
198#endif
199
200 if (ctx->seen & (SEEN_DATA | SEEN_SKB))
201 emit(ARM_MOV_R(r_skb, ARM_R0), ctx);
202
203 if (ctx->seen & SEEN_DATA) {
204 off = offsetof(struct sk_buff, data);
205 emit(ARM_LDR_I(r_skb_data, r_skb, off), ctx);
206 /* headlen = len - data_len */
207 off = offsetof(struct sk_buff, len);
208 emit(ARM_LDR_I(r_skb_hl, r_skb, off), ctx);
209 off = offsetof(struct sk_buff, data_len);
210 emit(ARM_LDR_I(r_scratch, r_skb, off), ctx);
211 emit(ARM_SUB_R(r_skb_hl, r_skb_hl, r_scratch), ctx);
212 }
213
214 if (ctx->flags & FLAG_NEED_X_RESET)
215 emit(ARM_MOV_I(r_X, 0), ctx);
216
217 /* do not leak kernel data to userspace */
34805931 218 if ((first_inst != (BPF_RET | BPF_K)) && !(is_load_to_a(first_inst)))
ddecdfce
MG		 219 emit(ARM_MOV_I(r_A, 0), ctx);
220
221 /* stack space for the BPF_MEM words */
222 if (ctx->seen & SEEN_MEM)
223 emit(ARM_SUB_I(ARM_SP, ARM_SP, mem_words_used(ctx) * 4), ctx);
224}
225
226static void build_epilogue(struct jit_ctx *ctx)
227{
228 u16 reg_set = saved_regs(ctx);
229
230 if (ctx->seen & SEEN_MEM)
231 emit(ARM_ADD_I(ARM_SP, ARM_SP, mem_words_used(ctx) * 4), ctx);
232
233 reg_set &= ~(1 << ARM_LR);
234
235#ifdef CONFIG_FRAME_POINTER
236 /* the first instruction of the prologue was: mov ip, sp */
237 reg_set &= ~(1 << ARM_IP);
238 reg_set |= (1 << ARM_SP);
239 emit(ARM_LDM(ARM_SP, reg_set), ctx);
240#else
241 if (reg_set) {
242 if (ctx->seen & SEEN_CALL)
243 reg_set |= 1 << ARM_PC;
244 emit(ARM_POP(reg_set), ctx);
245 }
246
247 if (!(ctx->seen & SEEN_CALL))
248 emit(ARM_BX(ARM_LR), ctx);
249#endif
250}
251
252static int16_t imm8m(u32 x)
253{
254 u32 rot;
255
256 for (rot = 0; rot < 16; rot++)
257 if ((x & ~ror32(0xff, 2 * rot)) == 0)
258 return rol32(x, 2 * rot) | (rot << 8);
259
260 return -1;
261}
262
263#if __LINUX_ARM_ARCH__ < 7
264
265static u16 imm_offset(u32 k, struct jit_ctx *ctx)
266{
267 unsigned i = 0, offset;
268 u16 imm;
269
270 /* on the "fake" run we just count them (duplicates included) */
271 if (ctx->target == NULL) {
272 ctx->imm_count++;
273 return 0;
274 }
275
276 while ((i < ctx->imm_count) && ctx->imms[i]) {
277 if (ctx->imms[i] == k)
278 break;
279 i++;
280 }
281
282 if (ctx->imms[i] == 0)
283 ctx->imms[i] = k;
284
285 /* constants go just after the epilogue */
286 offset = ctx->offsets[ctx->skf->len];
287 offset += ctx->prologue_bytes;
288 offset += ctx->epilogue_bytes;
289 offset += i * 4;
290
291 ctx->target[offset / 4] = k;
292
293 /* PC in ARM mode == address of the instruction + 8 */
294 imm = offset - (8 + ctx->idx * 4);
295
296 return imm;
297}
298
299#endif /* __LINUX_ARM_ARCH__ */
300
301/*
302 * Move an immediate that's not an imm8m to a core register.
303 */
304static inline void emit_mov_i_no8m(int rd, u32 val, struct jit_ctx *ctx)
305{
306#if __LINUX_ARM_ARCH__ < 7
307 emit(ARM_LDR_I(rd, ARM_PC, imm_offset(val, ctx)), ctx);
308#else
309 emit(ARM_MOVW(rd, val & 0xffff), ctx);
310 if (val > 0xffff)
311 emit(ARM_MOVT(rd, val >> 16), ctx);
312#endif
313}
314
315static inline void emit_mov_i(int rd, u32 val, struct jit_ctx *ctx)
316{
317 int imm12 = imm8m(val);
318
319 if (imm12 >= 0)
320 emit(ARM_MOV_I(rd, imm12), ctx);
321 else
322 emit_mov_i_no8m(rd, val, ctx);
323}
324
325#if __LINUX_ARM_ARCH__ < 6
326
327static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
328{
329 _emit(cond, ARM_LDRB_I(ARM_R3, r_addr, 1), ctx);
330 _emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx);
331 _emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 3), ctx);
332 _emit(cond, ARM_LSL_I(ARM_R3, ARM_R3, 16), ctx);
333 _emit(cond, ARM_LDRB_I(ARM_R0, r_addr, 2), ctx);
334 _emit(cond, ARM_ORR_S(ARM_R3, ARM_R3, ARM_R1, SRTYPE_LSL, 24), ctx);
335 _emit(cond, ARM_ORR_R(ARM_R3, ARM_R3, ARM_R2), ctx);
336 _emit(cond, ARM_ORR_S(r_res, ARM_R3, ARM_R0, SRTYPE_LSL, 8), ctx);
337}
338
339static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
340{
341 _emit(cond, ARM_LDRB_I(ARM_R1, r_addr, 0), ctx);
342 _emit(cond, ARM_LDRB_I(ARM_R2, r_addr, 1), ctx);
343 _emit(cond, ARM_ORR_S(r_res, ARM_R2, ARM_R1, SRTYPE_LSL, 8), ctx);
344}
345
346static inline void emit_swap16(u8 r_dst, u8 r_src, struct jit_ctx *ctx)
347{
462738f4
NS		 348 /* r_dst = (r_src << 8) | (r_src >> 8) */
349 emit(ARM_LSL_I(ARM_R1, r_src, 8), ctx);
350 emit(ARM_ORR_S(r_dst, ARM_R1, r_src, SRTYPE_LSR, 8), ctx);
351
352 /*
353 * we need to mask out the bits set in r_dst[23:16] due to
354 * the first shift instruction.
355 *
356 * note that 0x8ff is the encoded immediate 0x00ff0000.
357 */
358 emit(ARM_BIC_I(r_dst, r_dst, 0x8ff), ctx);
ddecdfce
MG		 359}
360
361#else /* ARMv6+ */
362
363static void emit_load_be32(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
364{
365 _emit(cond, ARM_LDR_I(r_res, r_addr, 0), ctx);
366#ifdef __LITTLE_ENDIAN
367 _emit(cond, ARM_REV(r_res, r_res), ctx);
368#endif
369}
370
371static void emit_load_be16(u8 cond, u8 r_res, u8 r_addr, struct jit_ctx *ctx)
372{
373 _emit(cond, ARM_LDRH_I(r_res, r_addr, 0), ctx);
374#ifdef __LITTLE_ENDIAN
375 _emit(cond, ARM_REV16(r_res, r_res), ctx);
376#endif
377}
378
379static inline void emit_swap16(u8 r_dst __maybe_unused,
380 u8 r_src __maybe_unused,
381 struct jit_ctx *ctx __maybe_unused)
382{
383#ifdef __LITTLE_ENDIAN
384 emit(ARM_REV16(r_dst, r_src), ctx);
385#endif
386}
387
388#endif /* __LINUX_ARM_ARCH__ < 6 */
389
390
391/* Compute the immediate value for a PC-relative branch. */
392static inline u32 b_imm(unsigned tgt, struct jit_ctx *ctx)
393{
394 u32 imm;
395
396 if (ctx->target == NULL)
397 return 0;
398 /*
399 * BPF allows only forward jumps and the offset of the target is
400 * still the one computed during the first pass.
401 */
402 imm = ctx->offsets[tgt] + ctx->prologue_bytes - (ctx->idx * 4 + 8);
403
404 return imm >> 2;
405}
406
407#define OP_IMM3(op, r1, r2, imm_val, ctx) \
408 do { \
409 imm12 = imm8m(imm_val); \
410 if (imm12 < 0) { \
411 emit_mov_i_no8m(r_scratch, imm_val, ctx); \
412 emit(op ## _R((r1), (r2), r_scratch), ctx); \
413 } else { \
414 emit(op ## _I((r1), (r2), imm12), ctx); \
415 } \
416 } while (0)
417
418static inline void emit_err_ret(u8 cond, struct jit_ctx *ctx)
419{
420 if (ctx->ret0_fp_idx >= 0) {
421 _emit(cond, ARM_B(b_imm(ctx->ret0_fp_idx, ctx)), ctx);
422 /* NOP to keep the size constant between passes */
423 emit(ARM_MOV_R(ARM_R0, ARM_R0), ctx);
424 } else {
425 _emit(cond, ARM_MOV_I(ARM_R0, 0), ctx);
426 _emit(cond, ARM_B(b_imm(ctx->skf->len, ctx)), ctx);
427 }
428}
429
430static inline void emit_blx_r(u8 tgt_reg, struct jit_ctx *ctx)
431{
432#if __LINUX_ARM_ARCH__ < 5
433 emit(ARM_MOV_R(ARM_LR, ARM_PC), ctx);
434
435 if (elf_hwcap & HWCAP_THUMB)
436 emit(ARM_BX(tgt_reg), ctx);
437 else
438 emit(ARM_MOV_R(ARM_PC, tgt_reg), ctx);
439#else
440 emit(ARM_BLX_R(tgt_reg), ctx);
441#endif
442}
443
444static inline void emit_udiv(u8 rd, u8 rm, u8 rn, struct jit_ctx *ctx)
445{
446#if __LINUX_ARM_ARCH__ == 7
447 if (elf_hwcap & HWCAP_IDIVA) {
448 emit(ARM_UDIV(rd, rm, rn), ctx);
449 return;
450 }
451#endif
19fc99d0
NS		 452
453 /*
454 * For BPF_ALU | BPF_DIV | BPF_K instructions, rm is ARM_R4
455 * (r_A) and rn is ARM_R0 (r_scratch) so load rn first into
456 * ARM_R1 to avoid accidentally overwriting ARM_R0 with rm
457 * before using it as a source for ARM_R1.
458 *
459 * For BPF_ALU | BPF_DIV | BPF_X rm is ARM_R4 (r_A) and rn is
460 * ARM_R5 (r_X) so there is no particular register overlap
461 * issues.
462 */
ddecdfce
MG		 463 if (rn != ARM_R1)
464 emit(ARM_MOV_R(ARM_R1, rn), ctx);
19fc99d0
NS		 465 if (rm != ARM_R0)
466 emit(ARM_MOV_R(ARM_R0, rm), ctx);
ddecdfce
MG		 467
468 ctx->seen |= SEEN_CALL;
469 emit_mov_i(ARM_R3, (u32)jit_udiv, ctx);
470 emit_blx_r(ARM_R3, ctx);
471
472 if (rd != ARM_R0)
473 emit(ARM_MOV_R(rd, ARM_R0), ctx);
474}
475
476static inline void update_on_xread(struct jit_ctx *ctx)
477{
478 if (!(ctx->seen & SEEN_X))
479 ctx->flags |= FLAG_NEED_X_RESET;
480
481 ctx->seen |= SEEN_X;
482}
483
484static int build_body(struct jit_ctx *ctx)
485{
486 void *load_func[] = {jit_get_skb_b, jit_get_skb_h, jit_get_skb_w};
7ae457c1 487 const struct bpf_prog *prog = ctx->skf;
ddecdfce
MG		 488 const struct sock_filter *inst;
489 unsigned i, load_order, off, condt;
490 int imm12;
491 u32 k;
492
493 for (i = 0; i < prog->len; i++) {
34805931
DB		 494 u16 code;
495
ddecdfce
MG		 496 inst = &(prog->insns[i]);
497 /* K as an immediate value operand */
498 k = inst->k;
34805931 499 code = bpf_anc_helper(inst);
ddecdfce
MG		 500
501 /* compute offsets only in the fake pass */
502 if (ctx->target == NULL)
503 ctx->offsets[i] = ctx->idx * 4;
504
34805931
DB		 505 switch (code) {
506 case BPF_LD | BPF_IMM:
ddecdfce
MG		 507 emit_mov_i(r_A, k, ctx);
508 break;
34805931 509 case BPF_LD | BPF_W | BPF_LEN:
ddecdfce
MG		 510 ctx->seen |= SEEN_SKB;
511 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, len) != 4);
512 emit(ARM_LDR_I(r_A, r_skb,
513 offsetof(struct sk_buff, len)), ctx);
514 break;
34805931 515 case BPF_LD | BPF_MEM:
ddecdfce
MG		 516 /* A = scratch[k] */
517 ctx->seen |= SEEN_MEM_WORD(k);
518 emit(ARM_LDR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
519 break;
34805931 520 case BPF_LD | BPF_W | BPF_ABS:
ddecdfce
MG		 521 load_order = 2;
522 goto load;
34805931 523 case BPF_LD | BPF_H | BPF_ABS:
ddecdfce
MG		 524 load_order = 1;
525 goto load;
34805931 526 case BPF_LD | BPF_B | BPF_ABS:
ddecdfce
MG		 527 load_order = 0;
528load:
529 /* the interpreter will deal with the negative K */
530 if ((int)k < 0)
531 return -ENOTSUPP;
532 emit_mov_i(r_off, k, ctx);
533load_common:
534 ctx->seen |= SEEN_DATA | SEEN_CALL;
535
536 if (load_order > 0) {
537 emit(ARM_SUB_I(r_scratch, r_skb_hl,
538 1 << load_order), ctx);
539 emit(ARM_CMP_R(r_scratch, r_off), ctx);
540 condt = ARM_COND_HS;
541 } else {
542 emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
543 condt = ARM_COND_HI;
544 }
545
546 _emit(condt, ARM_ADD_R(r_scratch, r_off, r_skb_data),
547 ctx);
548
549 if (load_order == 0)
550 _emit(condt, ARM_LDRB_I(r_A, r_scratch, 0),
551 ctx);
552 else if (load_order == 1)
553 emit_load_be16(condt, r_A, r_scratch, ctx);
554 else if (load_order == 2)
555 emit_load_be32(condt, r_A, r_scratch, ctx);
556
557 _emit(condt, ARM_B(b_imm(i + 1, ctx)), ctx);
558
559 /* the slowpath */
560 emit_mov_i(ARM_R3, (u32)load_func[load_order], ctx);
561 emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
562 /* the offset is already in R1 */
563 emit_blx_r(ARM_R3, ctx);
564 /* check the result of skb_copy_bits */
565 emit(ARM_CMP_I(ARM_R1, 0), ctx);
566 emit_err_ret(ARM_COND_NE, ctx);
567 emit(ARM_MOV_R(r_A, ARM_R0), ctx);
568 break;
34805931 569 case BPF_LD | BPF_W | BPF_IND:
ddecdfce
MG		 570 load_order = 2;
571 goto load_ind;
34805931 572 case BPF_LD | BPF_H | BPF_IND:
ddecdfce
MG		 573 load_order = 1;
574 goto load_ind;
34805931 575 case BPF_LD | BPF_B | BPF_IND:
ddecdfce
MG		 576 load_order = 0;
577load_ind:
578 OP_IMM3(ARM_ADD, r_off, r_X, k, ctx);
579 goto load_common;
34805931 580 case BPF_LDX | BPF_IMM:
ddecdfce
MG		 581 ctx->seen |= SEEN_X;
582 emit_mov_i(r_X, k, ctx);
583 break;
34805931 584 case BPF_LDX | BPF_W | BPF_LEN:
ddecdfce
MG		 585 ctx->seen |= SEEN_X | SEEN_SKB;
586 emit(ARM_LDR_I(r_X, r_skb,
587 offsetof(struct sk_buff, len)), ctx);
588 break;
34805931 589 case BPF_LDX | BPF_MEM:
ddecdfce
MG		 590 ctx->seen |= SEEN_X | SEEN_MEM_WORD(k);
591 emit(ARM_LDR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
592 break;
34805931 593 case BPF_LDX | BPF_B | BPF_MSH:
ddecdfce
MG		 594 /* x = ((*(frame + k)) & 0xf) << 2; */
595 ctx->seen |= SEEN_X | SEEN_DATA | SEEN_CALL;
596 /* the interpreter should deal with the negative K */
45549a68 597 if ((int)k < 0)
ddecdfce
MG		 598 return -1;
599 /* offset in r1: we might have to take the slow path */
600 emit_mov_i(r_off, k, ctx);
601 emit(ARM_CMP_R(r_skb_hl, r_off), ctx);
602
603 /* load in r0: common with the slowpath */
604 _emit(ARM_COND_HI, ARM_LDRB_R(ARM_R0, r_skb_data,
605 ARM_R1), ctx);
606 /*
607 * emit_mov_i() might generate one or two instructions,
608 * the same holds for emit_blx_r()
609 */
610 _emit(ARM_COND_HI, ARM_B(b_imm(i + 1, ctx) - 2), ctx);
611
612 emit(ARM_MOV_R(ARM_R0, r_skb), ctx);
613 /* r_off is r1 */
614 emit_mov_i(ARM_R3, (u32)jit_get_skb_b, ctx);
615 emit_blx_r(ARM_R3, ctx);
616 /* check the return value of skb_copy_bits */
617 emit(ARM_CMP_I(ARM_R1, 0), ctx);
618 emit_err_ret(ARM_COND_NE, ctx);
619
620 emit(ARM_AND_I(r_X, ARM_R0, 0x00f), ctx);
621 emit(ARM_LSL_I(r_X, r_X, 2), ctx);
622 break;
34805931 623 case BPF_ST:
ddecdfce
MG		 624 ctx->seen |= SEEN_MEM_WORD(k);
625 emit(ARM_STR_I(r_A, ARM_SP, SCRATCH_OFF(k)), ctx);
626 break;
34805931 627 case BPF_STX:
ddecdfce
MG		 628 update_on_xread(ctx);
629 ctx->seen |= SEEN_MEM_WORD(k);
630 emit(ARM_STR_I(r_X, ARM_SP, SCRATCH_OFF(k)), ctx);
631 break;
34805931 632 case BPF_ALU | BPF_ADD | BPF_K:
ddecdfce
MG		 633 /* A += K */
634 OP_IMM3(ARM_ADD, r_A, r_A, k, ctx);
635 break;
34805931 636 case BPF_ALU | BPF_ADD | BPF_X:
ddecdfce
MG		 637 update_on_xread(ctx);
638 emit(ARM_ADD_R(r_A, r_A, r_X), ctx);
639 break;
34805931 640 case BPF_ALU | BPF_SUB | BPF_K:
ddecdfce
MG		 641 /* A -= K */
642 OP_IMM3(ARM_SUB, r_A, r_A, k, ctx);
643 break;
34805931 644 case BPF_ALU | BPF_SUB | BPF_X:
ddecdfce
MG		 645 update_on_xread(ctx);
646 emit(ARM_SUB_R(r_A, r_A, r_X), ctx);
647 break;
34805931 648 case BPF_ALU | BPF_MUL | BPF_K:
ddecdfce
MG		 649 /* A *= K */
650 emit_mov_i(r_scratch, k, ctx);
651 emit(ARM_MUL(r_A, r_A, r_scratch), ctx);
652 break;
34805931 653 case BPF_ALU | BPF_MUL | BPF_X:
ddecdfce
MG		 654 update_on_xread(ctx);
655 emit(ARM_MUL(r_A, r_A, r_X), ctx);
656 break;
34805931 657 case BPF_ALU | BPF_DIV | BPF_K:
aee636c4
ED		 658 if (k == 1)
659 break;
ddecdfce 660 emit_mov_i(r_scratch, k, ctx);
aee636c4 661 emit_udiv(r_A, r_A, r_scratch, ctx);
ddecdfce 662 break;
34805931 663 case BPF_ALU | BPF_DIV | BPF_X:
ddecdfce
MG		 664 update_on_xread(ctx);
665 emit(ARM_CMP_I(r_X, 0), ctx);
666 emit_err_ret(ARM_COND_EQ, ctx);
667 emit_udiv(r_A, r_A, r_X, ctx);
668 break;
34805931 669 case BPF_ALU | BPF_OR | BPF_K:
ddecdfce
MG		 670 /* A |= K */
671 OP_IMM3(ARM_ORR, r_A, r_A, k, ctx);
672 break;
34805931 673 case BPF_ALU | BPF_OR | BPF_X:
ddecdfce
MG		 674 update_on_xread(ctx);
675 emit(ARM_ORR_R(r_A, r_A, r_X), ctx);
676 break;
34805931 677 case BPF_ALU | BPF_XOR | BPF_K:
3cbe2041
DB		 678 /* A ^= K; */
679 OP_IMM3(ARM_EOR, r_A, r_A, k, ctx);
680 break;
34805931
DB		 681 case BPF_ANC | SKF_AD_ALU_XOR_X:
682 case BPF_ALU | BPF_XOR | BPF_X:
3cbe2041
DB		 683 /* A ^= X */
684 update_on_xread(ctx);
685 emit(ARM_EOR_R(r_A, r_A, r_X), ctx);
686 break;
34805931 687 case BPF_ALU | BPF_AND | BPF_K:
ddecdfce
MG		 688 /* A &= K */
689 OP_IMM3(ARM_AND, r_A, r_A, k, ctx);
690 break;
34805931 691 case BPF_ALU | BPF_AND | BPF_X:
ddecdfce
MG		 692 update_on_xread(ctx);
693 emit(ARM_AND_R(r_A, r_A, r_X), ctx);
694 break;
34805931 695 case BPF_ALU | BPF_LSH | BPF_K:
ddecdfce
MG		 696 if (unlikely(k > 31))
697 return -1;
698 emit(ARM_LSL_I(r_A, r_A, k), ctx);
699 break;
34805931 700 case BPF_ALU | BPF_LSH | BPF_X:
ddecdfce
MG		 701 update_on_xread(ctx);
702 emit(ARM_LSL_R(r_A, r_A, r_X), ctx);
703 break;
34805931 704 case BPF_ALU | BPF_RSH | BPF_K:
ddecdfce
MG		 705 if (unlikely(k > 31))
706 return -1;
707 emit(ARM_LSR_I(r_A, r_A, k), ctx);
708 break;
34805931 709 case BPF_ALU | BPF_RSH | BPF_X:
ddecdfce
MG		 710 update_on_xread(ctx);
711 emit(ARM_LSR_R(r_A, r_A, r_X), ctx);
712 break;
34805931 713 case BPF_ALU | BPF_NEG:
ddecdfce
MG		 714 /* A = -A */
715 emit(ARM_RSB_I(r_A, r_A, 0), ctx);
716 break;
34805931 717 case BPF_JMP | BPF_JA:
ddecdfce
MG		 718 /* pc += K */
719 emit(ARM_B(b_imm(i + k + 1, ctx)), ctx);
720 break;
34805931 721 case BPF_JMP | BPF_JEQ | BPF_K:
ddecdfce
MG		 722 /* pc += (A == K) ? pc->jt : pc->jf */
723 condt = ARM_COND_EQ;
724 goto cmp_imm;
34805931 725 case BPF_JMP | BPF_JGT | BPF_K:
ddecdfce
MG		 726 /* pc += (A > K) ? pc->jt : pc->jf */
727 condt = ARM_COND_HI;
728 goto cmp_imm;
34805931 729 case BPF_JMP | BPF_JGE | BPF_K:
ddecdfce
MG		 730 /* pc += (A >= K) ? pc->jt : pc->jf */
731 condt = ARM_COND_HS;
732cmp_imm:
733 imm12 = imm8m(k);
734 if (imm12 < 0) {
735 emit_mov_i_no8m(r_scratch, k, ctx);
736 emit(ARM_CMP_R(r_A, r_scratch), ctx);
737 } else {
738 emit(ARM_CMP_I(r_A, imm12), ctx);
739 }
740cond_jump:
741 if (inst->jt)
742 _emit(condt, ARM_B(b_imm(i + inst->jt + 1,
743 ctx)), ctx);
744 if (inst->jf)
745 _emit(condt ^ 1, ARM_B(b_imm(i + inst->jf + 1,
746 ctx)), ctx);
747 break;
34805931 748 case BPF_JMP | BPF_JEQ | BPF_X:
ddecdfce
MG		 749 /* pc += (A == X) ? pc->jt : pc->jf */
750 condt = ARM_COND_EQ;
751 goto cmp_x;
34805931 752 case BPF_JMP | BPF_JGT | BPF_X:
ddecdfce
MG		 753 /* pc += (A > X) ? pc->jt : pc->jf */
754 condt = ARM_COND_HI;
755 goto cmp_x;
34805931 756 case BPF_JMP | BPF_JGE | BPF_X:
ddecdfce
MG		 757 /* pc += (A >= X) ? pc->jt : pc->jf */
758 condt = ARM_COND_CS;
759cmp_x:
760 update_on_xread(ctx);
761 emit(ARM_CMP_R(r_A, r_X), ctx);
762 goto cond_jump;
34805931 763 case BPF_JMP | BPF_JSET | BPF_K:
ddecdfce
MG		 764 /* pc += (A & K) ? pc->jt : pc->jf */
765 condt = ARM_COND_NE;
766 /* not set iff all zeroes iff Z==1 iff EQ */
767
768 imm12 = imm8m(k);
769 if (imm12 < 0) {
770 emit_mov_i_no8m(r_scratch, k, ctx);
771 emit(ARM_TST_R(r_A, r_scratch), ctx);
772 } else {
773 emit(ARM_TST_I(r_A, imm12), ctx);
774 }
775 goto cond_jump;
34805931 776 case BPF_JMP | BPF_JSET | BPF_X:
ddecdfce
MG		 777 /* pc += (A & X) ? pc->jt : pc->jf */
778 update_on_xread(ctx);
779 condt = ARM_COND_NE;
780 emit(ARM_TST_R(r_A, r_X), ctx);
781 goto cond_jump;
34805931 782 case BPF_RET | BPF_A:
ddecdfce
MG		 783 emit(ARM_MOV_R(ARM_R0, r_A), ctx);
784 goto b_epilogue;
34805931 785 case BPF_RET | BPF_K:
ddecdfce
MG		 786 if ((k == 0) && (ctx->ret0_fp_idx < 0))
787 ctx->ret0_fp_idx = i;
788 emit_mov_i(ARM_R0, k, ctx);
789b_epilogue:
790 if (i != ctx->skf->len - 1)
791 emit(ARM_B(b_imm(prog->len, ctx)), ctx);
792 break;
34805931 793 case BPF_MISC | BPF_TAX:
ddecdfce
MG		 794 /* X = A */
795 ctx->seen |= SEEN_X;
796 emit(ARM_MOV_R(r_X, r_A), ctx);
797 break;
34805931 798 case BPF_MISC | BPF_TXA:
ddecdfce
MG		 799 /* A = X */
800 update_on_xread(ctx);
801 emit(ARM_MOV_R(r_A, r_X), ctx);
802 break;
34805931 803 case BPF_ANC | SKF_AD_PROTOCOL:
ddecdfce
MG		 804 /* A = ntohs(skb->protocol) */
805 ctx->seen |= SEEN_SKB;
806 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
807 protocol) != 2);
808 off = offsetof(struct sk_buff, protocol);
809 emit(ARM_LDRH_I(r_scratch, r_skb, off), ctx);
810 emit_swap16(r_A, r_scratch, ctx);
811 break;
34805931 812 case BPF_ANC | SKF_AD_CPU:
ddecdfce
MG		 813 /* r_scratch = current_thread_info() */
814 OP_IMM3(ARM_BIC, r_scratch, ARM_SP, THREAD_SIZE - 1, ctx);
815 /* A = current_thread_info()->cpu */
816 BUILD_BUG_ON(FIELD_SIZEOF(struct thread_info, cpu) != 4);
817 off = offsetof(struct thread_info, cpu);
818 emit(ARM_LDR_I(r_A, r_scratch, off), ctx);
819 break;
34805931 820 case BPF_ANC | SKF_AD_IFINDEX:
ddecdfce
MG		 821 /* A = skb->dev->ifindex */
822 ctx->seen |= SEEN_SKB;
823 off = offsetof(struct sk_buff, dev);
824 emit(ARM_LDR_I(r_scratch, r_skb, off), ctx);
825
826 emit(ARM_CMP_I(r_scratch, 0), ctx);
827 emit_err_ret(ARM_COND_EQ, ctx);
828
829 BUILD_BUG_ON(FIELD_SIZEOF(struct net_device,
830 ifindex) != 4);
831 off = offsetof(struct net_device, ifindex);
832 emit(ARM_LDR_I(r_A, r_scratch, off), ctx);
833 break;
34805931 834 case BPF_ANC | SKF_AD_MARK:
ddecdfce
MG		 835 ctx->seen |= SEEN_SKB;
836 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, mark) != 4);
837 off = offsetof(struct sk_buff, mark);
838 emit(ARM_LDR_I(r_A, r_skb, off), ctx);
839 break;
34805931 840 case BPF_ANC | SKF_AD_RXHASH:
ddecdfce 841 ctx->seen |= SEEN_SKB;
61b905da
TH		 842 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, hash) != 4);
843 off = offsetof(struct sk_buff, hash);
ddecdfce
MG		 844 emit(ARM_LDR_I(r_A, r_skb, off), ctx);
845 break;
34805931
DB		 846 case BPF_ANC | SKF_AD_VLAN_TAG:
847 case BPF_ANC | SKF_AD_VLAN_TAG_PRESENT:
bf0098f2
DB		 848 ctx->seen |= SEEN_SKB;
849 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff, vlan_tci) != 2);
850 off = offsetof(struct sk_buff, vlan_tci);
851 emit(ARM_LDRH_I(r_A, r_skb, off), ctx);
34805931 852 if (code == (BPF_ANC | SKF_AD_VLAN_TAG))
bf0098f2
DB		 853 OP_IMM3(ARM_AND, r_A, r_A, VLAN_VID_MASK, ctx);
854 else
855 OP_IMM3(ARM_AND, r_A, r_A, VLAN_TAG_PRESENT, ctx);
856 break;
34805931 857 case BPF_ANC | SKF_AD_QUEUE:
ddecdfce
MG		 858 ctx->seen |= SEEN_SKB;
859 BUILD_BUG_ON(FIELD_SIZEOF(struct sk_buff,
860 queue_mapping) != 2);
861 BUILD_BUG_ON(offsetof(struct sk_buff,
862 queue_mapping) > 0xff);
863 off = offsetof(struct sk_buff, queue_mapping);
864 emit(ARM_LDRH_I(r_A, r_skb, off), ctx);
865 break;
866 default:
867 return -1;
868 }
869 }
870
871 /* compute offsets only during the first pass */
872 if (ctx->target == NULL)
873 ctx->offsets[i] = ctx->idx * 4;
874
875 return 0;
876}
877
878
7ae457c1 879void bpf_jit_compile(struct bpf_prog *fp)
ddecdfce 880{
55309dd3 881 struct bpf_binary_header *header;
ddecdfce
MG		 882 struct jit_ctx ctx;
883 unsigned tmp_idx;
884 unsigned alloc_size;
55309dd3 885 u8 *target_ptr;
ddecdfce
MG		 886
887 if (!bpf_jit_enable)
888 return;
889
890 memset(&ctx, 0, sizeof(ctx));
891 ctx.skf = fp;
892 ctx.ret0_fp_idx = -1;
893
89c2e009 894 ctx.offsets = kzalloc(4 * (ctx.skf->len + 1), GFP_KERNEL);
ddecdfce
MG		 895 if (ctx.offsets == NULL)
896 return;
897
898 /* fake pass to fill in the ctx->seen */
899 if (unlikely(build_body(&ctx)))
900 goto out;
901
902 tmp_idx = ctx.idx;
903 build_prologue(&ctx);
904 ctx.prologue_bytes = (ctx.idx - tmp_idx) * 4;
905
906#if __LINUX_ARM_ARCH__ < 7
907 tmp_idx = ctx.idx;
908 build_epilogue(&ctx);
909 ctx.epilogue_bytes = (ctx.idx - tmp_idx) * 4;
910
911 ctx.idx += ctx.imm_count;
912 if (ctx.imm_count) {
89c2e009 913 ctx.imms = kzalloc(4 * ctx.imm_count, GFP_KERNEL);
ddecdfce
MG		 914 if (ctx.imms == NULL)
915 goto out;
916 }
917#else
918 /* there's nothing after the epilogue on ARMv7 */
919 build_epilogue(&ctx);
920#endif
ddecdfce 921 alloc_size = 4 * ctx.idx;
55309dd3
DB		 922 header = bpf_jit_binary_alloc(alloc_size, &target_ptr,
923 4, jit_fill_hole);
924 if (header == NULL)
ddecdfce
MG		 925 goto out;
926
55309dd3 927 ctx.target = (u32 *) target_ptr;
ddecdfce 928 ctx.idx = 0;
55309dd3 929
ddecdfce
MG		 930 build_prologue(&ctx);
931 build_body(&ctx);
932 build_epilogue(&ctx);
933
934 flush_icache_range((u32)ctx.target, (u32)(ctx.target + ctx.idx));
935
936#if __LINUX_ARM_ARCH__ < 7
937 if (ctx.imm_count)
938 kfree(ctx.imms);
939#endif
940
941 if (bpf_jit_enable > 1)
79617801
DB		 942 /* there are 2 passes here */
943 bpf_jit_dump(fp->len, alloc_size, 2, ctx.target);
ddecdfce 944
55309dd3 945 set_memory_ro((unsigned long)header, header->pages);
ddecdfce 946 fp->bpf_func = (void *)ctx.target;
286aad3c 947 fp->jited = true;
ddecdfce
MG		 948out:
949 kfree(ctx.offsets);
950 return;
951}
952
7ae457c1 953void bpf_jit_free(struct bpf_prog *fp)
ddecdfce 954{
55309dd3
DB		 955 unsigned long addr = (unsigned long)fp->bpf_func & PAGE_MASK;
956 struct bpf_binary_header *header = (void *)addr;
957
958 if (!fp->jited)
959 goto free_filter;
960
961 set_memory_rw(addr, header->pages);
962 bpf_jit_binary_free(header);
60a3b225 963
55309dd3 964free_filter:
60a3b225 965 bpf_prog_unlock_free(fp);
ddecdfce 966}
Ubuntu Artful kernel mirror