[mirror_ubuntu-hirsute-kernel.git] / arch / arm / plat-iop / time.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * arch/arm/plat-iop/time.c
 *
 * Timer code for IOP32x and IOP33x based systems
 *
 * Author: Deepak Saxena <dsaxena@mvista.com>
 *
 * Copyright 2002-2003 MontaVista Software Inc.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/init.h>
#include <linux/timex.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/export.h>
#include <linux/sched_clock.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <linux/uaccess.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <mach/time.h>

/*
 * Minimum clocksource/clockevent timer range in seconds
 */
#define IOP_MIN_RANGE 4

/*
 * IOP clocksource (free-running timer 1).
 */
static u64 notrace iop_clocksource_read(struct clocksource *unused)
{
	return 0xffffffffu - read_tcr1();
}

static struct clocksource iop_clocksource = {
	.name 		= "iop_timer1",
	.rating		= 300,
	.read		= iop_clocksource_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

/*
 * IOP sched_clock() implementation via its clocksource.
 */
static u64 notrace iop_read_sched_clock(void)
{
	return 0xffffffffu - read_tcr1();
}

/*
 * IOP clockevents (interrupting timer 0).
 */
static int iop_set_next_event(unsigned long delta,
			      struct clock_event_device *unused)
{
	u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;

	BUG_ON(delta == 0);
	write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
	write_tcr0(delta);
	write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);

	return 0;
}

static unsigned long ticks_per_jiffy;

static int iop_set_periodic(struct clock_event_device *evt)
{
	u32 tmr = read_tmr0();

	write_tmr0(tmr & ~IOP_TMR_EN);
	write_tcr0(ticks_per_jiffy - 1);
	write_trr0(ticks_per_jiffy - 1);
	tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);

	write_tmr0(tmr);
	return 0;
}

static int iop_set_oneshot(struct clock_event_device *evt)
{
	u32 tmr = read_tmr0();

	/* ->set_next_event sets period and enables timer */
	tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
	write_tmr0(tmr);
	return 0;
}

static int iop_shutdown(struct clock_event_device *evt)
{
	u32 tmr = read_tmr0();

	tmr &= ~IOP_TMR_EN;
	write_tmr0(tmr);
	return 0;
}

static int iop_resume(struct clock_event_device *evt)
{
	u32 tmr = read_tmr0();

	tmr |= IOP_TMR_EN;
	write_tmr0(tmr);
	return 0;
}

static struct clock_event_device iop_clockevent = {
	.name			= "iop_timer0",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.rating			= 300,
	.set_next_event		= iop_set_next_event,
	.set_state_shutdown	= iop_shutdown,
	.set_state_periodic	= iop_set_periodic,
	.tick_resume		= iop_resume,
	.set_state_oneshot	= iop_set_oneshot,
};

static irqreturn_t
iop_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	write_tisr(1);
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction iop_timer_irq = {
	.name		= "IOP Timer Tick",
	.handler	= iop_timer_interrupt,
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.dev_id		= &iop_clockevent,
};

static unsigned long iop_tick_rate;
unsigned long get_iop_tick_rate(void)
{
	return iop_tick_rate;
}
EXPORT_SYMBOL(get_iop_tick_rate);

void __init iop_init_time(unsigned long tick_rate)
{
	u32 timer_ctl;

	sched_clock_register(iop_read_sched_clock, 32, tick_rate);

	ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
	iop_tick_rate = tick_rate;

	timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
			IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;

	/*
	 * Set up interrupting clockevent timer 0.
	 */
	write_tmr0(timer_ctl & ~IOP_TMR_EN);
	write_tisr(1);
	setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
	iop_clockevent.cpumask = cpumask_of(0);
	clockevents_config_and_register(&iop_clockevent, tick_rate,
					0xf, 0xfffffffe);

	/*
	 * Set up free-running clocksource timer 1.
	 */
	write_trr1(0xffffffff);
	write_tcr1(0xffffffff);
	write_tmr1(timer_ctl);
	clocksource_register_hz(&iop_clocksource, tick_rate);
}
Commit	Line	Data
2874c5fd	1	// SPDX-License-Identifier: GPL-2.0-or-later
48388b2a LB	2	/*
	3	* arch/arm/plat-iop/time.c
	4	*
	5	* Timer code for IOP32x and IOP33x based systems
	6	*
	7	* Author: Deepak Saxena <dsaxena@mvista.com>
	8	*
	9	* Copyright 2002-2003 MontaVista Software Inc.
48388b2a LB	10	*/
	11
	12	#include <linux/kernel.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/time.h>
	15	#include <linux/init.h>
	16	#include <linux/timex.h>
fced80c7	17	#include <linux/io.h>
a91549a8	18	#include <linux/clocksource.h>
469d3044	19	#include <linux/clockchips.h>
dc28094b	20	#include <linux/export.h>
38ff87f7	21	#include <linux/sched_clock.h>
a09e64fb	22	#include <mach/hardware.h>
48388b2a	23	#include <asm/irq.h>
7c0f6ba6	24	#include <linux/uaccess.h>
48388b2a LB	25	#include <asm/mach/irq.h>
48388b2a LB	26	#include <asm/mach/time.h>
a09e64fb	27	#include <mach/time.h>
48388b2a	28
7d633975 LW	29	/*
	30	* Minimum clocksource/clockevent timer range in seconds
	31	*/
	32	#define IOP_MIN_RANGE 4
	33
a91549a8 MP	34	/*
	35	* IOP clocksource (free-running timer 1).
	36	*/
a5a1d1c2	37	static u64 notrace iop_clocksource_read(struct clocksource *unused)
a91549a8 MP	38	{
	39	return 0xffffffffu - read_tcr1();
	40	}
	41
	42	static struct clocksource iop_clocksource = {
	43	.name = "iop_timer1",
	44	.rating = 300,
	45	.read = iop_clocksource_read,
	46	.mask = CLOCKSOURCE_MASK(32),
	47	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	48	};
	49
345a3229 MP	50	/*
	51	* IOP sched_clock() implementation via its clocksource.
	52	*/
c66af541	53	static u64 notrace iop_read_sched_clock(void)
345a3229	54	{
2f0778af	55	return 0xffffffffu - read_tcr1();
345a3229 MP	56	}
345a3229 MP	57
469d3044 MP	58	/*
	59	* IOP clockevents (interrupting timer 0).
	60	*/
	61	static int iop_set_next_event(unsigned long delta,
	62	struct clock_event_device *unused)
	63	{
	64	u32 tmr = IOP_TMR_PRIVILEGED \| IOP_TMR_RATIO_1_1;
	65
	66	BUG_ON(delta == 0);
	67	write_tmr0(tmr & ~(IOP_TMR_EN \| IOP_TMR_RELOAD));
	68	write_tcr0(delta);
	69	write_tmr0((tmr & ~IOP_TMR_RELOAD) \| IOP_TMR_EN);
	70
	71	return 0;
	72	}
	73
48388b2a	74	static unsigned long ticks_per_jiffy;
469d3044	75
8d778377	76	static int iop_set_periodic(struct clock_event_device *evt)
469d3044 MP	77	{
	78	u32 tmr = read_tmr0();
	79
8d778377 VK	80	write_tmr0(tmr & ~IOP_TMR_EN);
	81	write_tcr0(ticks_per_jiffy - 1);
	82	write_trr0(ticks_per_jiffy - 1);
	83	tmr \|= (IOP_TMR_RELOAD \| IOP_TMR_EN);
469d3044 MP	84
469d3044 MP	85	write_tmr0(tmr);
8d778377 VK	86	return 0;
	87	}
	88
	89	static int iop_set_oneshot(struct clock_event_device *evt)
	90	{
	91	u32 tmr = read_tmr0();
	92
	93	/* ->set_next_event sets period and enables timer */
	94	tmr &= ~(IOP_TMR_RELOAD \| IOP_TMR_EN);
	95	write_tmr0(tmr);
	96	return 0;
	97	}
	98
	99	static int iop_shutdown(struct clock_event_device *evt)
	100	{
	101	u32 tmr = read_tmr0();
	102
	103	tmr &= ~IOP_TMR_EN;
	104	write_tmr0(tmr);
	105	return 0;
	106	}
	107
	108	static int iop_resume(struct clock_event_device *evt)
	109	{
	110	u32 tmr = read_tmr0();
	111
	112	tmr \|= IOP_TMR_EN;
	113	write_tmr0(tmr);
	114	return 0;
469d3044 MP	115	}
	116
	117	static struct clock_event_device iop_clockevent = {
8d778377 VK	118	.name = "iop_timer0",
	119	.features = CLOCK_EVT_FEAT_PERIODIC \|
	120	CLOCK_EVT_FEAT_ONESHOT,
	121	.rating = 300,
	122	.set_next_event = iop_set_next_event,
	123	.set_state_shutdown = iop_shutdown,
	124	.set_state_periodic = iop_set_periodic,
	125	.tick_resume = iop_resume,
	126	.set_state_oneshot = iop_set_oneshot,
469d3044 MP	127	};
469d3044 MP	128
48388b2a	129	static irqreturn_t
3668b45d	130	iop_timer_interrupt(int irq, void *dev_id)
48388b2a	131	{
469d3044	132	struct clock_event_device *evt = dev_id;
48388b2a	133
469d3044 MP	134	write_tisr(1);
469d3044 MP	135	evt->event_handler(evt);
48388b2a LB	136	return IRQ_HANDLED;
	137	}
	138
3668b45d DW	139	static struct irqaction iop_timer_irq = {
	140	.name = "IOP Timer Tick",
	141	.handler = iop_timer_interrupt,
78f6db99	142	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
469d3044	143	.dev_id = &iop_clockevent,
48388b2a LB	144	};
48388b2a LB	145
70c14ff0 DW	146	static unsigned long iop_tick_rate;
	147	unsigned long get_iop_tick_rate(void)
	148	{
	149	return iop_tick_rate;
	150	}
	151	EXPORT_SYMBOL(get_iop_tick_rate);
	152
3668b45d	153	void __init iop_init_time(unsigned long tick_rate)
48388b2a LB	154	{
	155	u32 timer_ctl;
	156
c66af541	157	sched_clock_register(iop_read_sched_clock, 32, tick_rate);
08f26b1e	158
a692838d	159	ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
70c14ff0	160	iop_tick_rate = tick_rate;
48388b2a	161
3668b45d DW	162	timer_ctl = IOP_TMR_EN \| IOP_TMR_PRIVILEGED \|
3668b45d DW	163	IOP_TMR_RELOAD \| IOP_TMR_RATIO_1_1;
48388b2a LB	164
48388b2a LB	165	/*
469d3044	166	* Set up interrupting clockevent timer 0.
48388b2a	167	*/
469d3044	168	write_tmr0(timer_ctl & ~IOP_TMR_EN);
40cc5244	169	write_tisr(1);
469d3044	170	setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
469d3044	171	iop_clockevent.cpumask = cpumask_of(0);
838a2ae8 SG	172	clockevents_config_and_register(&iop_clockevent, tick_rate,
838a2ae8 SG	173	0xf, 0xfffffffe);
a91549a8 MP	174
	175	/*
	176	* Set up free-running clocksource timer 1.
	177	*/
3668b45d	178	write_trr1(0xffffffff);
a91549a8	179	write_tcr1(0xffffffff);
3668b45d	180	write_tmr1(timer_ctl);
d28b116b	181	clocksource_register_hz(&iop_clocksource, tick_rate);
48388b2a	182	}