[mirror_ubuntu-bionic-kernel.git] / arch / arm / plat-iop / time.c

/*
 * arch/arm/plat-iop/time.c
 *
 * Timer code for IOP32x and IOP33x based systems
 *
 * Author: Deepak Saxena <dsaxena@mvista.com>
 *
 * Copyright 2002-2003 MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/init.h>
#include <linux/timex.h>
#include <linux/sched.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/sched_clock.h>
#include <asm/uaccess.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <mach/time.h>

/*
 * Minimum clocksource/clockevent timer range in seconds
 */
#define IOP_MIN_RANGE 4

/*
 * IOP clocksource (free-running timer 1).
 */
static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
{
	return 0xffffffffu - read_tcr1();
}

static struct clocksource iop_clocksource = {
	.name 		= "iop_timer1",
	.rating		= 300,
	.read		= iop_clocksource_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

static DEFINE_CLOCK_DATA(cd);

/*
 * IOP sched_clock() implementation via its clocksource.
 */
unsigned long long notrace sched_clock(void)
{
	u32 cyc = 0xffffffffu - read_tcr1();
	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
}

static void notrace iop_update_sched_clock(void)
{
	u32 cyc = 0xffffffffu - read_tcr1();
	update_sched_clock(&cd, cyc, (u32)~0);
}

/*
 * IOP clockevents (interrupting timer 0).
 */
static int iop_set_next_event(unsigned long delta,
			      struct clock_event_device *unused)
{
	u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;

	BUG_ON(delta == 0);
	write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
	write_tcr0(delta);
	write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);

	return 0;
}

static unsigned long ticks_per_jiffy;

static void iop_set_mode(enum clock_event_mode mode,
			 struct clock_event_device *unused)
{
	u32 tmr = read_tmr0();

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		write_tmr0(tmr & ~IOP_TMR_EN);
		write_tcr0(ticks_per_jiffy - 1);
		write_trr0(ticks_per_jiffy - 1);
		tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* ->set_next_event sets period and enables timer */
		tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
		break;
	case CLOCK_EVT_MODE_RESUME:
		tmr |= IOP_TMR_EN;
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	default:
		tmr &= ~IOP_TMR_EN;
		break;
	}

	write_tmr0(tmr);
}

static struct clock_event_device iop_clockevent = {
	.name		= "iop_timer0",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating         = 300,
	.set_next_event	= iop_set_next_event,
	.set_mode	= iop_set_mode,
};

static irqreturn_t
iop_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	write_tisr(1);
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction iop_timer_irq = {
	.name		= "IOP Timer Tick",
	.handler	= iop_timer_interrupt,
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.dev_id		= &iop_clockevent,
};

static unsigned long iop_tick_rate;
unsigned long get_iop_tick_rate(void)
{
	return iop_tick_rate;
}
EXPORT_SYMBOL(get_iop_tick_rate);

void __init iop_init_time(unsigned long tick_rate)
{
	u32 timer_ctl;

	init_sched_clock(&cd, iop_update_sched_clock, 32, tick_rate);

	ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
	iop_tick_rate = tick_rate;

	timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
			IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;

	/*
	 * Set up interrupting clockevent timer 0.
	 */
	write_tmr0(timer_ctl & ~IOP_TMR_EN);
	write_tisr(1);
	setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
	clockevents_calc_mult_shift(&iop_clockevent,
				    tick_rate, IOP_MIN_RANGE);
	iop_clockevent.max_delta_ns =
		clockevent_delta2ns(0xfffffffe, &iop_clockevent);
	iop_clockevent.min_delta_ns =
		clockevent_delta2ns(0xf, &iop_clockevent);
	iop_clockevent.cpumask = cpumask_of(0);
	clockevents_register_device(&iop_clockevent);

	/*
	 * Set up free-running clocksource timer 1.
	 */
	write_trr1(0xffffffff);
	write_tcr1(0xffffffff);
	write_tmr1(timer_ctl);
	clocksource_register_hz(&iop_clocksource, tick_rate);
}
Commit	Line	Data
48388b2a LB	1	/*
	2	* arch/arm/plat-iop/time.c
	3	*
	4	* Timer code for IOP32x and IOP33x based systems
	5	*
	6	* Author: Deepak Saxena <dsaxena@mvista.com>
	7	*
	8	* Copyright 2002-2003 MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/time.h>
	19	#include <linux/init.h>
	20	#include <linux/timex.h>
a5542a0f	21	#include <linux/sched.h>
fced80c7	22	#include <linux/io.h>
a91549a8	23	#include <linux/clocksource.h>
469d3044	24	#include <linux/clockchips.h>
a09e64fb	25	#include <mach/hardware.h>
48388b2a	26	#include <asm/irq.h>
08f26b1e	27	#include <asm/sched_clock.h>
48388b2a LB	28	#include <asm/uaccess.h>
	29	#include <asm/mach/irq.h>
	30	#include <asm/mach/time.h>
a09e64fb	31	#include <mach/time.h>
48388b2a	32
7d633975 LW	33	/*
	34	* Minimum clocksource/clockevent timer range in seconds
	35	*/
	36	#define IOP_MIN_RANGE 4
	37
a91549a8 MP	38	/*
	39	* IOP clocksource (free-running timer 1).
	40	*/
a5542a0f	41	static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
a91549a8 MP	42	{
	43	return 0xffffffffu - read_tcr1();
	44	}
	45
	46	static struct clocksource iop_clocksource = {
	47	.name = "iop_timer1",
	48	.rating = 300,
	49	.read = iop_clocksource_read,
	50	.mask = CLOCKSOURCE_MASK(32),
	51	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	52	};
	53
08f26b1e RK	54	static DEFINE_CLOCK_DATA(cd);
08f26b1e RK	55
345a3229 MP	56	/*
	57	* IOP sched_clock() implementation via its clocksource.
	58	*/
5e06b649	59	unsigned long long notrace sched_clock(void)
345a3229	60	{
08f26b1e RK	61	u32 cyc = 0xffffffffu - read_tcr1();
	62	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
	63	}
345a3229	64
08f26b1e RK	65	static void notrace iop_update_sched_clock(void)
	66	{
	67	u32 cyc = 0xffffffffu - read_tcr1();
	68	update_sched_clock(&cd, cyc, (u32)~0);
345a3229 MP	69	}
345a3229 MP	70
469d3044 MP	71	/*
	72	* IOP clockevents (interrupting timer 0).
	73	*/
	74	static int iop_set_next_event(unsigned long delta,
	75	struct clock_event_device *unused)
	76	{
	77	u32 tmr = IOP_TMR_PRIVILEGED \| IOP_TMR_RATIO_1_1;
	78
	79	BUG_ON(delta == 0);
	80	write_tmr0(tmr & ~(IOP_TMR_EN \| IOP_TMR_RELOAD));
	81	write_tcr0(delta);
	82	write_tmr0((tmr & ~IOP_TMR_RELOAD) \| IOP_TMR_EN);
	83
	84	return 0;
	85	}
	86
48388b2a	87	static unsigned long ticks_per_jiffy;
469d3044 MP	88
	89	static void iop_set_mode(enum clock_event_mode mode,
	90	struct clock_event_device *unused)
	91	{
	92	u32 tmr = read_tmr0();
	93
	94	switch (mode) {
	95	case CLOCK_EVT_MODE_PERIODIC:
	96	write_tmr0(tmr & ~IOP_TMR_EN);
	97	write_tcr0(ticks_per_jiffy - 1);
40cc5244	98	write_trr0(ticks_per_jiffy - 1);
469d3044 MP	99	tmr \|= (IOP_TMR_RELOAD \| IOP_TMR_EN);
	100	break;
	101	case CLOCK_EVT_MODE_ONESHOT:
	102	/* ->set_next_event sets period and enables timer */
	103	tmr &= ~(IOP_TMR_RELOAD \| IOP_TMR_EN);
	104	break;
	105	case CLOCK_EVT_MODE_RESUME:
	106	tmr \|= IOP_TMR_EN;
	107	break;
	108	case CLOCK_EVT_MODE_SHUTDOWN:
	109	case CLOCK_EVT_MODE_UNUSED:
	110	default:
	111	tmr &= ~IOP_TMR_EN;
	112	break;
	113	}
	114
	115	write_tmr0(tmr);
	116	}
	117
	118	static struct clock_event_device iop_clockevent = {
	119	.name = "iop_timer0",
	120	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	121	.rating = 300,
	122	.set_next_event = iop_set_next_event,
	123	.set_mode = iop_set_mode,
	124	};
	125
48388b2a	126	static irqreturn_t
3668b45d	127	iop_timer_interrupt(int irq, void *dev_id)
48388b2a	128	{
469d3044	129	struct clock_event_device *evt = dev_id;
48388b2a	130
469d3044 MP	131	write_tisr(1);
469d3044 MP	132	evt->event_handler(evt);
48388b2a LB	133	return IRQ_HANDLED;
	134	}
	135
3668b45d DW	136	static struct irqaction iop_timer_irq = {
	137	.name = "IOP Timer Tick",
	138	.handler = iop_timer_interrupt,
b30fabad	139	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
469d3044	140	.dev_id = &iop_clockevent,
48388b2a LB	141	};
48388b2a LB	142
70c14ff0 DW	143	static unsigned long iop_tick_rate;
	144	unsigned long get_iop_tick_rate(void)
	145	{
	146	return iop_tick_rate;
	147	}
	148	EXPORT_SYMBOL(get_iop_tick_rate);
	149
3668b45d	150	void __init iop_init_time(unsigned long tick_rate)
48388b2a LB	151	{
	152	u32 timer_ctl;
	153
08f26b1e RK	154	init_sched_clock(&cd, iop_update_sched_clock, 32, tick_rate);
08f26b1e RK	155
a692838d	156	ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
70c14ff0	157	iop_tick_rate = tick_rate;
48388b2a	158
3668b45d DW	159	timer_ctl = IOP_TMR_EN \| IOP_TMR_PRIVILEGED \|
3668b45d DW	160	IOP_TMR_RELOAD \| IOP_TMR_RATIO_1_1;
48388b2a LB	161
48388b2a LB	162	/*
469d3044	163	* Set up interrupting clockevent timer 0.
48388b2a	164	*/
469d3044	165	write_tmr0(timer_ctl & ~IOP_TMR_EN);
40cc5244	166	write_tisr(1);
469d3044	167	setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
7d633975 LW	168	clockevents_calc_mult_shift(&iop_clockevent,
7d633975 LW	169	tick_rate, IOP_MIN_RANGE);
469d3044 MP	170	iop_clockevent.max_delta_ns =
	171	clockevent_delta2ns(0xfffffffe, &iop_clockevent);
	172	iop_clockevent.min_delta_ns =
	173	clockevent_delta2ns(0xf, &iop_clockevent);
	174	iop_clockevent.cpumask = cpumask_of(0);
	175	clockevents_register_device(&iop_clockevent);
a91549a8 MP	176
	177	/*
	178	* Set up free-running clocksource timer 1.
	179	*/
3668b45d	180	write_trr1(0xffffffff);
a91549a8	181	write_tcr1(0xffffffff);
3668b45d	182	write_tmr1(timer_ctl);
d28b116b	183	clocksource_register_hz(&iop_clocksource, tick_rate);
48388b2a	184	}