[mirror_ubuntu-artful-kernel.git] / arch / arm / plat-mxc / include / mach / hardware.h

/*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA  02110-1301, USA.
 */

#ifndef __ASM_ARCH_MXC_HARDWARE_H__
#define __ASM_ARCH_MXC_HARDWARE_H__

#include <asm/sizes.h>

#ifdef __ASSEMBLER__
#define IOMEM(addr)	(addr)
#else
#define IOMEM(addr)	((void __force __iomem *)(addr))
#endif

#define addr_in_module(addr, mod) \
	((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)

#define IMX_IO_P2V_MODULE(addr, module)					\
	(((addr) - module ## _BASE_ADDR) < module ## _SIZE ?		\
	 (addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)

/*
 * This is rather complicated for humans and ugly to verify, but for a machine
 * it's OK.  Still more as it is usually only applied to constants.  The upsides
 * on using this approach are:
 *
 *  - same mapping on all i.MX machines
 *  - works for assembler, too
 *  - no need to nurture #defines for virtual addresses
 *
 * The downside it, it's hard to verify (but I have a script for that).
 *
 * Obviously this needs to be injective for each SoC.  In general it maps the
 * whole address space to [0xf4000000, 0xf5ffffff].  So [0xf6000000,0xfeffffff]
 * is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
 *
 * It applies the following mappings for the different SoCs:
 *
 * mx1:
 *	IO	0x00200000+0x100000	->	0xf4000000+0x100000
 * mx21:
 *	AIPI	0x10000000+0x100000	->	0xf4400000+0x100000
 *	SAHB1	0x80000000+0x100000	->	0xf4000000+0x100000
 *	X_MEMC	0xdf000000+0x004000	->	0xf5f00000+0x004000
 * mx25:
 *	AIPS1	0x43f00000+0x100000	->	0xf5300000+0x100000
 *	AIPS2	0x53f00000+0x100000	->	0xf5700000+0x100000
 *	AVIC	0x68000000+0x100000	->	0xf5800000+0x100000
 * mx27:
 *	AIPI	0x10000000+0x100000	->	0xf4400000+0x100000
 *	SAHB1	0x80000000+0x100000	->	0xf4000000+0x100000
 *	X_MEMC	0xd8000000+0x100000	->	0xf5c00000+0x100000
 * mx31:
 *	AIPS1	0x43f00000+0x100000	->	0xf5300000+0x100000
 *	AIPS2	0x53f00000+0x100000	->	0xf5700000+0x100000
 *	AVIC	0x68000000+0x100000	->	0xf5800000+0x100000
 *	X_MEMC	0xb8000000+0x010000	->	0xf4c00000+0x010000
 *	SPBA0	0x50000000+0x100000	->	0xf5400000+0x100000
 * mx35:
 *	AIPS1	0x43f00000+0x100000	->	0xf5300000+0x100000
 *	AIPS2	0x53f00000+0x100000	->	0xf5700000+0x100000
 *	AVIC	0x68000000+0x100000	->	0xf5800000+0x100000
 *	X_MEMC	0xb8000000+0x010000	->	0xf4c00000+0x010000
 *	SPBA0	0x50000000+0x100000	->	0xf5400000+0x100000
 * mx50:
 *	TZIC	0x0fffc000+0x004000	->	0xf4bfc000+0x004000
 *	SPBA0	0x50000000+0x100000	->	0xf5400000+0x100000
 *	AIPS1	0x53f00000+0x100000	->	0xf5700000+0x100000
 *	AIPS2	0x63f00000+0x100000	->	0xf5300000+0x100000
 * mx51:
 *	TZIC	0xe0000000+0x004000	->	0xf5000000+0x004000
 *	IRAM	0x1ffe0000+0x020000	->	0xf4fe0000+0x020000
 *	SPBA0	0x70000000+0x100000	->	0xf5400000+0x100000
 *	AIPS1	0x73f00000+0x100000	->	0xf5700000+0x100000
 *	AIPS2	0x83f00000+0x100000	->	0xf4300000+0x100000
 * mx53:
 *	TZIC	0x0fffc000+0x004000	->	0xf4bfc000+0x004000
 *	SPBA0	0x50000000+0x100000	->	0xf5400000+0x100000
 *	AIPS1	0x53f00000+0x100000	->	0xf5700000+0x100000
 *	AIPS2	0x63f00000+0x100000	->	0xf5300000+0x100000
 * mx6q:
 *	SCU	0x00a00000+0x001000	->	0xf4000000+0x001000
 *	CCM	0x020c4000+0x004000	->	0xf42c4000+0x004000
 *	ANATOP	0x020c8000+0x001000	->	0xf42c8000+0x001000
 *	UART4	0x021f0000+0x004000	->	0xf42f0000+0x004000
 */
#define IMX_IO_P2V(x)	(						\
			0xf4000000 +					\
			(((x) & 0x50000000) >> 6) +			\
			(((x) & 0x0b000000) >> 4) +			\
			(((x) & 0x000fffff)))

#define IMX_IO_ADDRESS(x)	IOMEM(IMX_IO_P2V(x))

#include <mach/mxc.h>

#include <mach/mx6q.h>
#include <mach/mx50.h>
#include <mach/mx51.h>
#include <mach/mx53.h>
#include <mach/mx3x.h>
#include <mach/mx31.h>
#include <mach/mx35.h>
#include <mach/mx2x.h>
#include <mach/mx21.h>
#include <mach/mx27.h>
#include <mach/mx1.h>
#include <mach/mx25.h>

#define imx_map_entry(soc, name, _type)	{				\
	.virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),	\
	.pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR),		\
	.length = soc ## _ ## name ## _SIZE,				\
	.type = _type,							\
}

/* There's a off-by-one betweem the gpio bank number and the gpiochip */
/* range e.g. GPIO_1_5 is gpio 5 under linux */
#define IMX_GPIO_NR(bank, nr)		(((bank) - 1) * 32 + (nr))

#define IMX_GPIO_TO_IRQ(gpio)	(MXC_GPIO_IRQ_START + (gpio))

#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */
Commit	Line	Data
52c543f9	1	/*
63dd1084 SH	2	* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	* MA 02110-1301, USA.
52c543f9 QJ	18	*/
52c543f9 QJ	19
52c543f9 QJ	20	#ifndef __ASM_ARCH_MXC_HARDWARE_H__
	21	#define __ASM_ARCH_MXC_HARDWARE_H__
	22
	23	#include <asm/sizes.h>
	24
f5d7a13b UKK	25	#ifdef __ASSEMBLER__
	26	#define IOMEM(addr) (addr)
	27	#else
	28	#define IOMEM(addr) ((void __force __iomem *)(addr))
	29	#endif
	30
c177aa98 RH	31	#define addr_in_module(addr, mod) \
	32	((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
	33
f5d7a13b UKK	34	#define IMX_IO_P2V_MODULE(addr, module) \
	35	(((addr) - module ## _BASE_ADDR) < module ## _SIZE ? \
	36	(addr) - (module ## _BASE_ADDR) + (module ## _BASE_ADDR_VIRT) : 0)
1f2ddd64	37
a9963148 UKK	38	/*
	39	* This is rather complicated for humans and ugly to verify, but for a machine
	40	* it's OK. Still more as it is usually only applied to constants. The upsides
	41	* on using this approach are:
	42	*
	43	* - same mapping on all i.MX machines
	44	* - works for assembler, too
	45	* - no need to nurture #defines for virtual addresses
	46	*
	47	* The downside it, it's hard to verify (but I have a script for that).
	48	*
	49	* Obviously this needs to be injective for each SoC. In general it maps the
	50	* whole address space to [0xf4000000, 0xf5ffffff]. So [0xf6000000,0xfeffffff]
	51	* is free for per-machine use (e.g. KZM_ARM11_01 uses 64MiB there).
	52	*
	53	* It applies the following mappings for the different SoCs:
	54	*
	55	* mx1:
	56	* IO 0x00200000+0x100000 -> 0xf4000000+0x100000
	57	* mx21:
	58	* AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
	59	* SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
	60	* X_MEMC 0xdf000000+0x004000 -> 0xf5f00000+0x004000
	61	* mx25:
	62	* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
	63	* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
	64	* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
	65	* mx27:
	66	* AIPI 0x10000000+0x100000 -> 0xf4400000+0x100000
	67	* SAHB1 0x80000000+0x100000 -> 0xf4000000+0x100000
	68	* X_MEMC 0xd8000000+0x100000 -> 0xf5c00000+0x100000
	69	* mx31:
	70	* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
	71	* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
	72	* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
	73	* X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
	74	* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
	75	* mx35:
	76	* AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
	77	* AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
	78	* AVIC 0x68000000+0x100000 -> 0xf5800000+0x100000
	79	* X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
	80	* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
3d5a44be RZ	81	* mx50:
	82	* TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
	83	* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
	84	* AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
	85	* AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
a9963148	86	* mx51:
4c542390	87	* TZIC 0xe0000000+0x004000 -> 0xf5000000+0x004000
a9963148	88	* IRAM 0x1ffe0000+0x020000 -> 0xf4fe0000+0x020000
a9963148 UKK	89	* SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
	90	* AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
	91	* AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
4c542390 JL	92	* mx53:
	93	* TZIC 0x0fffc000+0x004000 -> 0xf4bfc000+0x004000
	94	* SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
	95	* AIPS1 0x53f00000+0x100000 -> 0xf5700000+0x100000
	96	* AIPS2 0x63f00000+0x100000 -> 0xf5300000+0x100000
bac89d75 SG	97	* mx6q:
	98	* SCU 0x00a00000+0x001000 -> 0xf4000000+0x001000
	99	* CCM 0x020c4000+0x004000 -> 0xf42c4000+0x004000
	100	* ANATOP 0x020c8000+0x001000 -> 0xf42c8000+0x001000
	101	* UART4 0x021f0000+0x004000 -> 0xf42f0000+0x004000
a9963148 UKK	102	*/
	103	#define IMX_IO_P2V(x) ( \
	104	0xf4000000 + \
	105	(((x) & 0x50000000) >> 6) + \
	106	(((x) & 0x0b000000) >> 4) + \
	107	(((x) & 0x000fffff)))
	108
	109	#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
	110
d286a43a UKK	111	#include <mach/mxc.h>
d286a43a UKK	112
bac89d75	113	#include <mach/mx6q.h>
3d5a44be	114	#include <mach/mx50.h>
438caa3f	115	#include <mach/mx51.h>
c0abefd3	116	#include <mach/mx53.h>
c0a5f855 SH	117	#include <mach/mx3x.h>
	118	#include <mach/mx31.h>
	119	#include <mach/mx35.h>
db279c1b SH	120	#include <mach/mx2x.h>
	121	#include <mach/mx21.h>
	122	#include <mach/mx27.h>
	123	#include <mach/mx1.h>
	124	#include <mach/mx25.h>
8c25c36f	125
08ff97b5 UKK	126	#define imx_map_entry(soc, name, _type) { \
	127	.virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
	128	.pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
	129	.length = soc ## _ ## name ## _SIZE, \
	130	.type = _type, \
	131	}
	132
1dfa86bb SG	133	/* There's a off-by-one betweem the gpio bank number and the gpiochip */
	134	/* range e.g. GPIO_1_5 is gpio 5 under linux */
	135	#define IMX_GPIO_NR(bank, nr) (((bank) - 1) * 32 + (nr))
	136
e309fb18 SG	137	#define IMX_GPIO_TO_IRQ(gpio) (MXC_GPIO_IRQ_START + (gpio))
e309fb18 SG	138
f304fc42	139	#endif /* __ASM_ARCH_MXC_HARDWARE_H__ */