[mirror_ubuntu-eoan-kernel.git] / arch / arm / plat-mxc / include / mach / mx21.h

/*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 * Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
 *
 * This contains i.MX21-specific hardware definitions. For those
 * hardware pieces that are common between i.MX21 and i.MX27, have a
 * look at mx2x.h.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA  02110-1301, USA.
 */

#ifndef __ASM_ARCH_MXC_MX21_H__
#define __ASM_ARCH_MXC_MX21_H__

#define MX21_AIPI_BASE_ADDR		0x10000000
#define MX21_AIPI_BASE_ADDR_VIRT	0xf4000000
#define MX21_AIPI_SIZE			SZ_1M
#define MX21_DMA_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x01000)
#define MX21_WDOG_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x02000)
#define MX21_GPT1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x03000)
#define MX21_GPT2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x04000)
#define MX21_GPT3_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x05000)
#define MX21_PWM_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x06000)
#define MX21_RTC_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x07000)
#define MX21_KPP_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x08000)
#define MX21_OWIRE_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x09000)
#define MX21_UART1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0a000)
#define MX21_UART2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0b000)
#define MX21_UART3_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0c000)
#define MX21_UART4_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0d000)
#define MX21_CSPI1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0e000)
#define MX21_CSPI2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x0f000)
#define MX21_SSI1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x10000)
#define MX21_SSI2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x11000)
#define MX21_I2C_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x12000)
#define MX21_SDHC1_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x13000)
#define MX21_SDHC2_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x14000)
#define MX21_GPIO_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x15000)
#define MX21_AUDMUX_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x16000)
#define MX21_CSPI3_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x17000)
#define MX21_LCDC_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x21000)
#define MX21_SLCDC_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x22000)
#define MX21_USBOTG_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x24000)
#define MX21_EMMA_PP_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x26000)
#define MX21_EMMA_PRP_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x26400)
#define MX21_CCM_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x27000)
#define MX21_SYSCTRL_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x27800)
#define MX21_JAM_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x3e000)
#define MX21_MAX_BASE_ADDR			(MX21_AIPI_BASE_ADDR + 0x3f000)

#define MX21_AVIC_BASE_ADDR		0x10040000

#define MX21_SAHB1_BASE_ADDR		0x80000000
#define MX21_SAHB1_BASE_ADDR_VIRT	0xf4100000
#define MX21_SAHB1_SIZE			SZ_1M
#define MX21_CSI_BASE_ADDR			(MX2x_SAHB1_BASE_ADDR + 0x0000)

/* Memory regions and CS */
#define MX21_SDRAM_BASE_ADDR		0xc0000000
#define MX21_CSD1_BASE_ADDR		0xc4000000

#define MX21_CS0_BASE_ADDR		0xc8000000
#define MX21_CS1_BASE_ADDR		0xcc000000
#define MX21_CS2_BASE_ADDR		0xd0000000
#define MX21_CS3_BASE_ADDR		0xd1000000
#define MX21_CS4_BASE_ADDR		0xd2000000
#define MX21_PCMCIA_MEM_BASE_ADDR	0xd4000000
#define MX21_CS5_BASE_ADDR		0xdd000000

/* NAND, SDRAM, WEIM etc controllers */
#define MX21_X_MEMC_BASE_ADDR		0xdf000000
#define MX21_X_MEMC_BASE_ADDR_VIRT	0xf4200000
#define MX21_X_MEMC_SIZE		SZ_256K

#define MX21_SDRAMC_BASE_ADDR		(MX21_X_MEMC_BASE_ADDR + 0x0000)
#define MX21_EIM_BASE_ADDR		(MX21_X_MEMC_BASE_ADDR + 0x1000)
#define MX21_PCMCIA_CTL_BASE_ADDR	(MX21_X_MEMC_BASE_ADDR + 0x2000)
#define MX21_NFC_BASE_ADDR		(MX21_X_MEMC_BASE_ADDR + 0x3000)

#define MX21_IRAM_BASE_ADDR		0xffffe800	/* internal ram */

/* fixed interrupt numbers */
#define MX21_INT_CSPI3		6
#define MX21_INT_GPIO		8
#define MX21_INT_FIRI		9
#define MX21_INT_SDHC2		10
#define MX21_INT_SDHC1		11
#define MX21_INT_I2C		12
#define MX21_INT_SSI2		13
#define MX21_INT_SSI1		14
#define MX21_INT_CSPI2		15
#define MX21_INT_CSPI1		16
#define MX21_INT_UART4		17
#define MX21_INT_UART3		18
#define MX21_INT_UART2		19
#define MX21_INT_UART1		20
#define MX21_INT_KPP		21
#define MX21_INT_RTC		22
#define MX21_INT_PWM		23
#define MX21_INT_GPT3		24
#define MX21_INT_GPT2		25
#define MX21_INT_GPT1		26
#define MX21_INT_WDOG		27
#define MX21_INT_PCMCIA		28
#define MX21_INT_NANDFC		29
#define MX21_INT_BMI		30
#define MX21_INT_CSI		31
#define MX21_INT_DMACH0		32
#define MX21_INT_DMACH1		33
#define MX21_INT_DMACH2		34
#define MX21_INT_DMACH3		35
#define MX21_INT_DMACH4		36
#define MX21_INT_DMACH5		37
#define MX21_INT_DMACH6		38
#define MX21_INT_DMACH7		39
#define MX21_INT_DMACH8		40
#define MX21_INT_DMACH9		41
#define MX21_INT_DMACH10	42
#define MX21_INT_DMACH11	43
#define MX21_INT_DMACH12	44
#define MX21_INT_DMACH13	45
#define MX21_INT_DMACH14	46
#define MX21_INT_DMACH15	47
#define MX21_INT_EMMAENC	49
#define MX21_INT_EMMADEC	50
#define MX21_INT_EMMAPRP	51
#define MX21_INT_EMMAPP		52
#define MX21_INT_USBWKUP	53
#define MX21_INT_USBDMA		54
#define MX21_INT_USBHOST	55
#define MX21_INT_USBFUNC	56
#define MX21_INT_USBMNP		57
#define MX21_INT_USBCTRL	58
#define MX21_INT_SLCDC		60
#define MX21_INT_LCDC		61

/* fixed DMA request numbers */
#define MX21_DMA_REQ_CSPI3_RX	1
#define MX21_DMA_REQ_CSPI3_TX	2
#define MX21_DMA_REQ_EXT	3
#define MX21_DMA_REQ_FIRI_RX	4
#define MX21_DMA_REQ_SDHC2	6
#define MX21_DMA_REQ_SDHC1	7
#define MX21_DMA_REQ_SSI2_RX0	8
#define MX21_DMA_REQ_SSI2_TX0	9
#define MX21_DMA_REQ_SSI2_RX1	10
#define MX21_DMA_REQ_SSI2_TX1	11
#define MX21_DMA_REQ_SSI1_RX0	12
#define MX21_DMA_REQ_SSI1_TX0	13
#define MX21_DMA_REQ_SSI1_RX1	14
#define MX21_DMA_REQ_SSI1_TX1	15
#define MX21_DMA_REQ_CSPI2_RX	16
#define MX21_DMA_REQ_CSPI2_TX	17
#define MX21_DMA_REQ_CSPI1_RX	18
#define MX21_DMA_REQ_CSPI1_TX	19
#define MX21_DMA_REQ_UART4_RX	20
#define MX21_DMA_REQ_UART4_TX	21
#define MX21_DMA_REQ_UART3_RX	22
#define MX21_DMA_REQ_UART3_TX	23
#define MX21_DMA_REQ_UART2_RX	24
#define MX21_DMA_REQ_UART2_TX	25
#define MX21_DMA_REQ_UART1_RX	26
#define MX21_DMA_REQ_UART1_TX	27
#define MX21_DMA_REQ_BMI_TX	28
#define MX21_DMA_REQ_BMI_RX	29
#define MX21_DMA_REQ_CSI_STAT	30
#define MX21_DMA_REQ_CSI_RX	31

/* these should go away */
#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
#define X_MEMC_SIZE MX21_X_MEMC_SIZE
#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
#define MXC_INT_FIRI MX21_INT_FIRI
#define MXC_INT_BMI MX21_INT_BMI
#define MXC_INT_EMMAENC MX21_INT_EMMAENC
#define MXC_INT_EMMADEC MX21_INT_EMMADEC
#define MXC_INT_USBWKUP MX21_INT_USBWKUP
#define MXC_INT_USBDMA MX21_INT_USBDMA
#define MXC_INT_USBHOST MX21_INT_USBHOST
#define MXC_INT_USBFUNC MX21_INT_USBFUNC
#define MXC_INT_USBMNP MX21_INT_USBMNP
#define MXC_INT_USBCTRL MX21_INT_USBCTRL
#define MXC_INT_USBCTRL MX21_INT_USBCTRL
#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX

#endif /* __ASM_ARCH_MXC_MX21_H__ */
Commit	Line	Data
260a1fd2 HS	1	/*
	2	* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	* Copyright 2009 Holger Schurig, hs4233@mail.mn-solutions.de
	5	*
	6	* This contains i.MX21-specific hardware definitions. For those
	7	* hardware pieces that are common between i.MX21 and i.MX27, have a
	8	* look at mx2x.h.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License
	12	* as published by the Free Software Foundation; either version 2
	13	* of the License, or (at your option) any later version.
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	22	* MA 02110-1301, USA.
	23	*/
	24
	25	#ifndef __ASM_ARCH_MXC_MX21_H__
	26	#define __ASM_ARCH_MXC_MX21_H__
	27
4c12b3c2 UKK	28	#define MX21_AIPI_BASE_ADDR 0x10000000
	29	#define MX21_AIPI_BASE_ADDR_VIRT 0xf4000000
	30	#define MX21_AIPI_SIZE SZ_1M
	31	#define MX21_DMA_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x01000)
	32	#define MX21_WDOG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x02000)
	33	#define MX21_GPT1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x03000)
	34	#define MX21_GPT2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x04000)
	35	#define MX21_GPT3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x05000)
	36	#define MX21_PWM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x06000)
	37	#define MX21_RTC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x07000)
	38	#define MX21_KPP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x08000)
	39	#define MX21_OWIRE_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x09000)
	40	#define MX21_UART1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0a000)
	41	#define MX21_UART2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0b000)
	42	#define MX21_UART3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0c000)
	43	#define MX21_UART4_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0d000)
	44	#define MX21_CSPI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0e000)
	45	#define MX21_CSPI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x0f000)
	46	#define MX21_SSI1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x10000)
	47	#define MX21_SSI2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x11000)
	48	#define MX21_I2C_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x12000)
	49	#define MX21_SDHC1_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x13000)
	50	#define MX21_SDHC2_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x14000)
	51	#define MX21_GPIO_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x15000)
	52	#define MX21_AUDMUX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x16000)
	53	#define MX21_CSPI3_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x17000)
	54	#define MX21_LCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x21000)
	55	#define MX21_SLCDC_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x22000)
	56	#define MX21_USBOTG_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x24000)
	57	#define MX21_EMMA_PP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26000)
	58	#define MX21_EMMA_PRP_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x26400)
	59	#define MX21_CCM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27000)
	60	#define MX21_SYSCTRL_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x27800)
	61	#define MX21_JAM_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3e000)
	62	#define MX21_MAX_BASE_ADDR (MX21_AIPI_BASE_ADDR + 0x3f000)
	63
	64	#define MX21_AVIC_BASE_ADDR 0x10040000
	65
	66	#define MX21_SAHB1_BASE_ADDR 0x80000000
	67	#define MX21_SAHB1_BASE_ADDR_VIRT 0xf4100000
	68	#define MX21_SAHB1_SIZE SZ_1M
	69	#define MX21_CSI_BASE_ADDR (MX2x_SAHB1_BASE_ADDR + 0x0000)
	70
260a1fd2	71	/* Memory regions and CS */
c1129313 UKK	72	#define MX21_SDRAM_BASE_ADDR 0xc0000000
c1129313 UKK	73	#define MX21_CSD1_BASE_ADDR 0xc4000000
260a1fd2	74
c1129313 UKK	75	#define MX21_CS0_BASE_ADDR 0xc8000000
	76	#define MX21_CS1_BASE_ADDR 0xcc000000
	77	#define MX21_CS2_BASE_ADDR 0xd0000000
	78	#define MX21_CS3_BASE_ADDR 0xd1000000
	79	#define MX21_CS4_BASE_ADDR 0xd2000000
	80	#define MX21_PCMCIA_MEM_BASE_ADDR 0xd4000000
	81	#define MX21_CS5_BASE_ADDR 0xdd000000
260a1fd2 HS	82
260a1fd2 HS	83	/* NAND, SDRAM, WEIM etc controllers */
c1129313 UKK	84	#define MX21_X_MEMC_BASE_ADDR 0xdf000000
	85	#define MX21_X_MEMC_BASE_ADDR_VIRT 0xf4200000
	86	#define MX21_X_MEMC_SIZE SZ_256K
260a1fd2	87
c1129313 UKK	88	#define MX21_SDRAMC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x0000)
	89	#define MX21_EIM_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x1000)
	90	#define MX21_PCMCIA_CTL_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x2000)
	91	#define MX21_NFC_BASE_ADDR (MX21_X_MEMC_BASE_ADDR + 0x3000)
260a1fd2	92
c1129313	93	#define MX21_IRAM_BASE_ADDR 0xffffe800 /* internal ram */
260a1fd2	94
260a1fd2	95	/* fixed interrupt numbers */
4c12b3c2 UKK	96	#define MX21_INT_CSPI3 6
4c12b3c2 UKK	97	#define MX21_INT_GPIO 8
c1129313	98	#define MX21_INT_FIRI 9
4c12b3c2 UKK	99	#define MX21_INT_SDHC2 10
	100	#define MX21_INT_SDHC1 11
	101	#define MX21_INT_I2C 12
	102	#define MX21_INT_SSI2 13
	103	#define MX21_INT_SSI1 14
	104	#define MX21_INT_CSPI2 15
	105	#define MX21_INT_CSPI1 16
	106	#define MX21_INT_UART4 17
	107	#define MX21_INT_UART3 18
	108	#define MX21_INT_UART2 19
	109	#define MX21_INT_UART1 20
	110	#define MX21_INT_KPP 21
	111	#define MX21_INT_RTC 22
	112	#define MX21_INT_PWM 23
	113	#define MX21_INT_GPT3 24
	114	#define MX21_INT_GPT2 25
	115	#define MX21_INT_GPT1 26
	116	#define MX21_INT_WDOG 27
	117	#define MX21_INT_PCMCIA 28
	118	#define MX21_INT_NANDFC 29
c1129313	119	#define MX21_INT_BMI 30
4c12b3c2 UKK	120	#define MX21_INT_CSI 31
	121	#define MX21_INT_DMACH0 32
	122	#define MX21_INT_DMACH1 33
	123	#define MX21_INT_DMACH2 34
	124	#define MX21_INT_DMACH3 35
	125	#define MX21_INT_DMACH4 36
	126	#define MX21_INT_DMACH5 37
	127	#define MX21_INT_DMACH6 38
	128	#define MX21_INT_DMACH7 39
	129	#define MX21_INT_DMACH8 40
	130	#define MX21_INT_DMACH9 41
	131	#define MX21_INT_DMACH10 42
	132	#define MX21_INT_DMACH11 43
	133	#define MX21_INT_DMACH12 44
	134	#define MX21_INT_DMACH13 45
	135	#define MX21_INT_DMACH14 46
	136	#define MX21_INT_DMACH15 47
c1129313 UKK	137	#define MX21_INT_EMMAENC 49
c1129313 UKK	138	#define MX21_INT_EMMADEC 50
4c12b3c2 UKK	139	#define MX21_INT_EMMAPRP 51
4c12b3c2 UKK	140	#define MX21_INT_EMMAPP 52
c1129313 UKK	141	#define MX21_INT_USBWKUP 53
	142	#define MX21_INT_USBDMA 54
	143	#define MX21_INT_USBHOST 55
	144	#define MX21_INT_USBFUNC 56
	145	#define MX21_INT_USBMNP 57
	146	#define MX21_INT_USBCTRL 58
4c12b3c2 UKK	147	#define MX21_INT_SLCDC 60
4c12b3c2 UKK	148	#define MX21_INT_LCDC 61
260a1fd2 HS	149
260a1fd2 HS	150	/* fixed DMA request numbers */
4c12b3c2 UKK	151	#define MX21_DMA_REQ_CSPI3_RX 1
	152	#define MX21_DMA_REQ_CSPI3_TX 2
	153	#define MX21_DMA_REQ_EXT 3
c1129313	154	#define MX21_DMA_REQ_FIRI_RX 4
4c12b3c2 UKK	155	#define MX21_DMA_REQ_SDHC2 6
	156	#define MX21_DMA_REQ_SDHC1 7
	157	#define MX21_DMA_REQ_SSI2_RX0 8
	158	#define MX21_DMA_REQ_SSI2_TX0 9
	159	#define MX21_DMA_REQ_SSI2_RX1 10
	160	#define MX21_DMA_REQ_SSI2_TX1 11
	161	#define MX21_DMA_REQ_SSI1_RX0 12
	162	#define MX21_DMA_REQ_SSI1_TX0 13
	163	#define MX21_DMA_REQ_SSI1_RX1 14
	164	#define MX21_DMA_REQ_SSI1_TX1 15
	165	#define MX21_DMA_REQ_CSPI2_RX 16
	166	#define MX21_DMA_REQ_CSPI2_TX 17
	167	#define MX21_DMA_REQ_CSPI1_RX 18
	168	#define MX21_DMA_REQ_CSPI1_TX 19
	169	#define MX21_DMA_REQ_UART4_RX 20
	170	#define MX21_DMA_REQ_UART4_TX 21
	171	#define MX21_DMA_REQ_UART3_RX 22
	172	#define MX21_DMA_REQ_UART3_TX 23
	173	#define MX21_DMA_REQ_UART2_RX 24
	174	#define MX21_DMA_REQ_UART2_TX 25
	175	#define MX21_DMA_REQ_UART1_RX 26
	176	#define MX21_DMA_REQ_UART1_TX 27
c1129313 UKK	177	#define MX21_DMA_REQ_BMI_TX 28
c1129313 UKK	178	#define MX21_DMA_REQ_BMI_RX 29
4c12b3c2 UKK	179	#define MX21_DMA_REQ_CSI_STAT 30
4c12b3c2 UKK	180	#define MX21_DMA_REQ_CSI_RX 31
c1129313 UKK	181
	182	/* these should go away */
	183	#define SDRAM_BASE_ADDR MX21_SDRAM_BASE_ADDR
	184	#define CSD1_BASE_ADDR MX21_CSD1_BASE_ADDR
	185	#define CS0_BASE_ADDR MX21_CS0_BASE_ADDR
	186	#define CS1_BASE_ADDR MX21_CS1_BASE_ADDR
	187	#define CS2_BASE_ADDR MX21_CS2_BASE_ADDR
	188	#define CS3_BASE_ADDR MX21_CS3_BASE_ADDR
	189	#define CS4_BASE_ADDR MX21_CS4_BASE_ADDR
	190	#define PCMCIA_MEM_BASE_ADDR MX21_PCMCIA_MEM_BASE_ADDR
	191	#define CS5_BASE_ADDR MX21_CS5_BASE_ADDR
	192	#define X_MEMC_BASE_ADDR MX21_X_MEMC_BASE_ADDR
	193	#define X_MEMC_BASE_ADDR_VIRT MX21_X_MEMC_BASE_ADDR_VIRT
	194	#define X_MEMC_SIZE MX21_X_MEMC_SIZE
	195	#define SDRAMC_BASE_ADDR MX21_SDRAMC_BASE_ADDR
	196	#define EIM_BASE_ADDR MX21_EIM_BASE_ADDR
	197	#define PCMCIA_CTL_BASE_ADDR MX21_PCMCIA_CTL_BASE_ADDR
	198	#define NFC_BASE_ADDR MX21_NFC_BASE_ADDR
	199	#define IRAM_BASE_ADDR MX21_IRAM_BASE_ADDR
	200	#define MXC_INT_FIRI MX21_INT_FIRI
	201	#define MXC_INT_BMI MX21_INT_BMI
	202	#define MXC_INT_EMMAENC MX21_INT_EMMAENC
	203	#define MXC_INT_EMMADEC MX21_INT_EMMADEC
	204	#define MXC_INT_USBWKUP MX21_INT_USBWKUP
	205	#define MXC_INT_USBDMA MX21_INT_USBDMA
	206	#define MXC_INT_USBHOST MX21_INT_USBHOST
	207	#define MXC_INT_USBFUNC MX21_INT_USBFUNC
	208	#define MXC_INT_USBMNP MX21_INT_USBMNP
	209	#define MXC_INT_USBCTRL MX21_INT_USBCTRL
	210	#define MXC_INT_USBCTRL MX21_INT_USBCTRL
	211	#define DMA_REQ_FIRI_RX MX21_DMA_REQ_FIRI_RX
	212	#define DMA_REQ_BMI_TX MX21_DMA_REQ_BMI_TX
	213	#define DMA_REQ_BMI_RX MX21_DMA_REQ_BMI_RX
260a1fd2 HS	214
260a1fd2 HS	215	#endif /* __ASM_ARCH_MXC_MX21_H__ */