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Commit | Line | Data |
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8c25c36f SH |
1 | #ifndef __MACH_MX25_H__ |
2 | #define __MACH_MX25_H__ | |
3 | ||
c8e5db08 | 4 | #define MX25_AIPS1_BASE_ADDR 0x43f00000 |
8c25c36f | 5 | #define MX25_AIPS1_SIZE SZ_1M |
c8e5db08 | 6 | #define MX25_AIPS2_BASE_ADDR 0x53f00000 |
8c25c36f SH |
7 | #define MX25_AIPS2_SIZE SZ_1M |
8 | #define MX25_AVIC_BASE_ADDR 0x68000000 | |
8c25c36f SH |
9 | #define MX25_AVIC_SIZE SZ_1M |
10 | ||
a8ff0456 UKK |
11 | #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) |
12 | #define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) | |
c3f6a346 MKB |
13 | #define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) |
14 | #define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) | |
a8ff0456 | 15 | #define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) |
63ddc5b0 | 16 | #define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) |
8c25c36f SH |
17 | #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) |
18 | ||
19 | #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) | |
20 | #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) | |
cf3a6aba | 21 | #define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) |
5f3d1092 | 22 | #define MX25_PWM2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa0000) |
cf3a6aba | 23 | #define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) |
5f3d1092 UKK |
24 | #define MX25_PWM3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa8000) |
25 | #define MX25_PWM4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xc8000) | |
cf3a6aba UKK |
26 | #define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) |
27 | #define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) | |
8c25c36f | 28 | #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) |
5f3d1092 | 29 | #define MX25_PWM1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xe0000) |
8c25c36f | 30 | |
66ac2f28 UKK |
31 | #define MX25_UART1_BASE_ADDR 0x43f90000 |
32 | #define MX25_UART2_BASE_ADDR 0x43f94000 | |
8402ed30 | 33 | #define MX25_AUDMUX_BASE_ADDR 0x43fb0000 |
7cc3c846 UKK |
34 | #define MX25_UART3_BASE_ADDR 0x5000c000 |
35 | #define MX25_UART4_BASE_ADDR 0x50008000 | |
36 | #define MX25_UART5_BASE_ADDR 0x5002c000 | |
8c25c36f | 37 | |
63ddc5b0 UKK |
38 | #define MX25_CSPI3_BASE_ADDR 0x50004000 |
39 | #define MX25_CSPI2_BASE_ADDR 0x50010000 | |
a759544f | 40 | #define MX25_FEC_BASE_ADDR 0x50038000 |
8402ed30 EB |
41 | #define MX25_SSI2_BASE_ADDR 0x50014000 |
42 | #define MX25_SSI1_BASE_ADDR 0x50034000 | |
27f59025 | 43 | #define MX25_NFC_BASE_ADDR 0xbb000000 |
dcbabbc1 | 44 | #define MX25_DRYICE_BASE_ADDR 0x53ffc000 |
f5e40c28 EB |
45 | #define MX25_ESDHC1_BASE_ADDR 0x53fb4000 |
46 | #define MX25_ESDHC2_BASE_ADDR 0x53fb8000 | |
04a03e5f | 47 | #define MX25_LCDC_BASE_ADDR 0x53fbc000 |
49535a95 | 48 | #define MX25_KPP_BASE_ADDR 0x43fa8000 |
ec4aac20 | 49 | #define MX25_SDMA_BASE_ADDR 0x53fd4000 |
2c20b9f1 UKK |
50 | #define MX25_USB_BASE_ADDR 0x53ff4000 |
51 | #define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) | |
4c6c32b3 UKK |
52 | /* |
53 | * The reference manual (IMX25RM, Rev. 1, 06/2009) specifies an offset of 0x200 | |
54 | * for the host controller. Early documentation drafts specified 0x400 and | |
55 | * Freescale internal sources confirm only the latter value to work. | |
56 | */ | |
57 | #define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0400) | |
f747847e | 58 | #define MX25_CSI_BASE_ADDR 0x53ff8000 |
a759544f | 59 | |
a9963148 UKK |
60 | #define MX25_IO_P2V(x) IMX_IO_P2V(x) |
61 | #define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) | |
62 | ||
63ddc5b0 | 63 | #define MX25_INT_CSPI3 0 |
a8ff0456 UKK |
64 | #define MX25_INT_I2C1 3 |
65 | #define MX25_INT_I2C2 4 | |
7cc3c846 | 66 | #define MX25_INT_UART4 5 |
c0745129 EB |
67 | #define MX25_INT_ESDHC2 8 |
68 | #define MX25_INT_ESDHC1 9 | |
a8ff0456 | 69 | #define MX25_INT_I2C3 10 |
2dcf78c0 UKK |
70 | #define MX25_INT_SSI2 11 |
71 | #define MX25_INT_SSI1 12 | |
63ddc5b0 UKK |
72 | #define MX25_INT_CSPI2 13 |
73 | #define MX25_INT_CSPI1 14 | |
d485c7e7 | 74 | #define MX25_INT_GPIO3 16 |
2dcf78c0 | 75 | #define MX25_INT_CSI 17 |
7cc3c846 | 76 | #define MX25_INT_UART3 18 |
d485c7e7 | 77 | #define MX25_INT_GPIO4 23 |
2dcf78c0 | 78 | #define MX25_INT_KPP 24 |
a8ff0456 | 79 | #define MX25_INT_DRYICE 25 |
5f3d1092 | 80 | #define MX25_INT_PWM1 26 |
7cc3c846 | 81 | #define MX25_INT_UART2 32 |
00b57bf9 | 82 | #define MX25_INT_NFC 33 |
ec4aac20 | 83 | #define MX25_INT_SDMA 34 |
2c20b9f1 | 84 | #define MX25_INT_USB_HS 35 |
5f3d1092 | 85 | #define MX25_INT_PWM2 36 |
2c20b9f1 | 86 | #define MX25_INT_USB_OTG 37 |
a8ff0456 | 87 | #define MX25_INT_LCDC 39 |
7cc3c846 | 88 | #define MX25_INT_UART5 40 |
5f3d1092 UKK |
89 | #define MX25_INT_PWM3 41 |
90 | #define MX25_INT_PWM4 42 | |
c3f6a346 MKB |
91 | #define MX25_INT_CAN1 43 |
92 | #define MX25_INT_CAN2 44 | |
7cc3c846 | 93 | #define MX25_INT_UART1 45 |
d485c7e7 UKK |
94 | #define MX25_INT_GPIO2 51 |
95 | #define MX25_INT_GPIO1 52 | |
63ddc5b0 | 96 | #define MX25_INT_FEC 57 |
a759544f | 97 | |
4697bb92 UKK |
98 | #define MX25_DMA_REQ_SSI2_RX1 22 |
99 | #define MX25_DMA_REQ_SSI2_TX1 23 | |
100 | #define MX25_DMA_REQ_SSI2_RX0 24 | |
101 | #define MX25_DMA_REQ_SSI2_TX0 25 | |
102 | #define MX25_DMA_REQ_SSI1_RX1 26 | |
103 | #define MX25_DMA_REQ_SSI1_TX1 27 | |
104 | #define MX25_DMA_REQ_SSI1_RX0 28 | |
105 | #define MX25_DMA_REQ_SSI1_TX0 29 | |
106 | ||
3cdd5441 | 107 | #endif /* ifndef __MACH_MX25_H__ */ |