projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 8c25c36f SH |
1 | #ifndef __MACH_MX25_H__ |
| 2 | #define __MACH_MX25_H__ | |
| 3 | ||
| c8e5db08 | 4 | #define MX25_AIPS1_BASE_ADDR 0x43f00000 |
| 8c25c36f | 5 | #define MX25_AIPS1_SIZE SZ_1M |
| c8e5db08 | 6 | #define MX25_AIPS2_BASE_ADDR 0x53f00000 |
| 8c25c36f SH |
7 | #define MX25_AIPS2_SIZE SZ_1M |
| 8 | #define MX25_AVIC_BASE_ADDR 0x68000000 | |
| 8c25c36f SH |
9 | #define MX25_AVIC_SIZE SZ_1M |
| 10 | ||
| a8ff0456 UKK |
11 | #define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000) |
| 12 | #define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000) | |
| c3f6a346 MKB |
13 | #define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000) |
| 14 | #define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000) | |
| a8ff0456 | 15 | #define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000) |
| 63ddc5b0 | 16 | #define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000) |
| 8c25c36f SH |
17 | #define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000) |
| 18 | ||
| 19 | #define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000) | |
| 20 | #define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000) | |
| cf3a6aba UKK |
21 | #define MX25_GPIO4_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x9c000) |
| 22 | #define MX25_GPIO3_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xa4000) | |
| 23 | #define MX25_GPIO1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xcc000) | |
| 24 | #define MX25_GPIO2_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xd0000) | |
| 8c25c36f SH |
25 | #define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000) |
| 26 | ||
| 66ac2f28 UKK |
27 | #define MX25_UART1_BASE_ADDR 0x43f90000 |
| 28 | #define MX25_UART2_BASE_ADDR 0x43f94000 | |
| 8402ed30 | 29 | #define MX25_AUDMUX_BASE_ADDR 0x43fb0000 |
| 7cc3c846 UKK |
30 | #define MX25_UART3_BASE_ADDR 0x5000c000 |
| 31 | #define MX25_UART4_BASE_ADDR 0x50008000 | |
| 32 | #define MX25_UART5_BASE_ADDR 0x5002c000 | |
| 8c25c36f | 33 | |
| 63ddc5b0 UKK |
34 | #define MX25_CSPI3_BASE_ADDR 0x50004000 |
| 35 | #define MX25_CSPI2_BASE_ADDR 0x50010000 | |
| a759544f | 36 | #define MX25_FEC_BASE_ADDR 0x50038000 |
| 8402ed30 EB |
37 | #define MX25_SSI2_BASE_ADDR 0x50014000 |
| 38 | #define MX25_SSI1_BASE_ADDR 0x50034000 | |
| 27f59025 | 39 | #define MX25_NFC_BASE_ADDR 0xbb000000 |
| dcbabbc1 | 40 | #define MX25_DRYICE_BASE_ADDR 0x53ffc000 |
| f5e40c28 EB |
41 | #define MX25_ESDHC1_BASE_ADDR 0x53fb4000 |
| 42 | #define MX25_ESDHC2_BASE_ADDR 0x53fb8000 | |
| 04a03e5f | 43 | #define MX25_LCDC_BASE_ADDR 0x53fbc000 |
| 49535a95 | 44 | #define MX25_KPP_BASE_ADDR 0x43fa8000 |
| ec4aac20 | 45 | #define MX25_SDMA_BASE_ADDR 0x53fd4000 |
| 2c20b9f1 UKK |
46 | #define MX25_USB_BASE_ADDR 0x53ff4000 |
| 47 | #define MX25_USB_OTG_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0000) | |
| 48 | #define MX25_USB_HS_BASE_ADDR (MX25_USB_BASE_ADDR + 0x0200) | |
| f747847e | 49 | #define MX25_CSI_BASE_ADDR 0x53ff8000 |
| a759544f | 50 | |
| a9963148 UKK |
51 | #define MX25_IO_P2V(x) IMX_IO_P2V(x) |
| 52 | #define MX25_IO_ADDRESS(x) IOMEM(MX25_IO_P2V(x)) | |
| 53 | ||
| 63ddc5b0 | 54 | #define MX25_INT_CSPI3 0 |
| a8ff0456 UKK |
55 | #define MX25_INT_I2C1 3 |
| 56 | #define MX25_INT_I2C2 4 | |
| 7cc3c846 | 57 | #define MX25_INT_UART4 5 |
| c0745129 EB |
58 | #define MX25_INT_ESDHC2 8 |
| 59 | #define MX25_INT_ESDHC1 9 | |
| a8ff0456 | 60 | #define MX25_INT_I2C3 10 |
| 2dcf78c0 UKK |
61 | #define MX25_INT_SSI2 11 |
| 62 | #define MX25_INT_SSI1 12 | |
| 63ddc5b0 UKK |
63 | #define MX25_INT_CSPI2 13 |
| 64 | #define MX25_INT_CSPI1 14 | |
| 2dcf78c0 | 65 | #define MX25_INT_CSI 17 |
| 7cc3c846 | 66 | #define MX25_INT_UART3 18 |
| 2dcf78c0 | 67 | #define MX25_INT_KPP 24 |
| a8ff0456 | 68 | #define MX25_INT_DRYICE 25 |
| 7cc3c846 | 69 | #define MX25_INT_UART2 32 |
| 00b57bf9 | 70 | #define MX25_INT_NFC 33 |
| ec4aac20 | 71 | #define MX25_INT_SDMA 34 |
| 2c20b9f1 UKK |
72 | #define MX25_INT_USB_HS 35 |
| 73 | #define MX25_INT_USB_OTG 37 | |
| a8ff0456 | 74 | #define MX25_INT_LCDC 39 |
| 7cc3c846 | 75 | #define MX25_INT_UART5 40 |
| c3f6a346 MKB |
76 | #define MX25_INT_CAN1 43 |
| 77 | #define MX25_INT_CAN2 44 | |
| 7cc3c846 | 78 | #define MX25_INT_UART1 45 |
| 63ddc5b0 | 79 | #define MX25_INT_FEC 57 |
| a759544f | 80 | |
| 4697bb92 UKK |
81 | #define MX25_DMA_REQ_SSI2_RX1 22 |
| 82 | #define MX25_DMA_REQ_SSI2_TX1 23 | |
| 83 | #define MX25_DMA_REQ_SSI2_RX0 24 | |
| 84 | #define MX25_DMA_REQ_SSI2_TX0 25 | |
| 85 | #define MX25_DMA_REQ_SSI1_RX1 26 | |
| 86 | #define MX25_DMA_REQ_SSI1_TX1 27 | |
| 87 | #define MX25_DMA_REQ_SSI1_RX0 28 | |
| 88 | #define MX25_DMA_REQ_SSI1_TX0 29 | |
| 89 | ||
| 3cdd5441 | 90 | #endif /* ifndef __MACH_MX25_H__ */ |