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mx51: add resources for SD/MMC on i.MX51
[mirror_ubuntu-eoan-kernel.git] / arch / arm / plat-mxc / include / mach / mx25.h
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1#ifndef __MACH_MX25_H__
2#define __MACH_MX25_H__
3
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4#define MX25_AIPS1_BASE_ADDR 0x43f00000
5#define MX25_AIPS1_BASE_ADDR_VIRT 0xfc000000
8c25c36f 6#define MX25_AIPS1_SIZE SZ_1M
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7#define MX25_AIPS2_BASE_ADDR 0x53f00000
8#define MX25_AIPS2_BASE_ADDR_VIRT 0xfc200000
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9#define MX25_AIPS2_SIZE SZ_1M
10#define MX25_AVIC_BASE_ADDR 0x68000000
c8e5db08 11#define MX25_AVIC_BASE_ADDR_VIRT 0xfc400000
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12#define MX25_AVIC_SIZE SZ_1M
13
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14#define MX25_I2C1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x80000)
15#define MX25_I2C3_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x84000)
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16#define MX25_CAN1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x88000)
17#define MX25_CAN2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x8c000)
a8ff0456 18#define MX25_I2C2_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0x98000)
63ddc5b0 19#define MX25_CSPI1_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xa4000)
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20#define MX25_IOMUXC_BASE_ADDR (MX25_AIPS1_BASE_ADDR + 0xac000)
21
22#define MX25_CRM_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x80000)
23#define MX25_GPT1_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0x90000)
24#define MX25_WDOG_BASE_ADDR (MX25_AIPS2_BASE_ADDR + 0xdc000)
25
26#define MX25_GPIO1_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xcc000)
27#define MX25_GPIO2_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xd0000)
28#define MX25_GPIO3_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0xa4000)
29#define MX25_GPIO4_BASE_ADDR_VIRT (MX25_AIPS2_BASE_ADDR_VIRT + 0x9c000)
30
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31#define MX25_IO_ADDRESS(x) ( \
32 IMX_IO_ADDRESS(x, MX25_AIPS1) ?: \
33 IMX_IO_ADDRESS(x, MX25_AIPS2) ?: \
34 IMX_IO_ADDRESS(x, MX25_AVIC))
8c25c36f 35
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36#define MX25_AIPS1_IO_ADDRESS(x) \
37 (((x) - MX25_AIPS1_BASE_ADDR) + MX25_AIPS1_BASE_ADDR_VIRT)
38
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39#define MX25_UART1_BASE_ADDR 0x43f90000
40#define MX25_UART2_BASE_ADDR 0x43f94000
8402ed30 41#define MX25_AUDMUX_BASE_ADDR 0x43fb0000
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42#define MX25_UART3_BASE_ADDR 0x5000c000
43#define MX25_UART4_BASE_ADDR 0x50008000
44#define MX25_UART5_BASE_ADDR 0x5002c000
8c25c36f 45
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46#define MX25_CSPI3_BASE_ADDR 0x50004000
47#define MX25_CSPI2_BASE_ADDR 0x50010000
a759544f 48#define MX25_FEC_BASE_ADDR 0x50038000
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49#define MX25_SSI2_BASE_ADDR 0x50014000
50#define MX25_SSI1_BASE_ADDR 0x50034000
27f59025 51#define MX25_NFC_BASE_ADDR 0xbb000000
dcbabbc1 52#define MX25_DRYICE_BASE_ADDR 0x53ffc000
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53#define MX25_ESDHC1_BASE_ADDR 0x53fb4000
54#define MX25_ESDHC2_BASE_ADDR 0x53fb8000
04a03e5f 55#define MX25_LCDC_BASE_ADDR 0x53fbc000
49535a95 56#define MX25_KPP_BASE_ADDR 0x43fa8000
ec4aac20 57#define MX25_SDMA_BASE_ADDR 0x53fd4000
5a36c399 58#define MX25_OTG_BASE_ADDR 0x53ff4000
f747847e 59#define MX25_CSI_BASE_ADDR 0x53ff8000
a759544f 60
63ddc5b0 61#define MX25_INT_CSPI3 0
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62#define MX25_INT_I2C1 3
63#define MX25_INT_I2C2 4
7cc3c846 64#define MX25_INT_UART4 5
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65#define MX25_INT_MMC_SDHC2 8
66#define MX25_INT_MMC_SDHC1 9
a8ff0456 67#define MX25_INT_I2C3 10
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68#define MX25_INT_SSI2 11
69#define MX25_INT_SSI1 12
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70#define MX25_INT_CSPI2 13
71#define MX25_INT_CSPI1 14
2dcf78c0 72#define MX25_INT_CSI 17
7cc3c846 73#define MX25_INT_UART3 18
2dcf78c0 74#define MX25_INT_KPP 24
a8ff0456 75#define MX25_INT_DRYICE 25
7cc3c846 76#define MX25_INT_UART2 32
00b57bf9 77#define MX25_INT_NFC 33
ec4aac20 78#define MX25_INT_SDMA 34
a8ff0456 79#define MX25_INT_LCDC 39
7cc3c846 80#define MX25_INT_UART5 40
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81#define MX25_INT_CAN1 43
82#define MX25_INT_CAN2 44
7cc3c846 83#define MX25_INT_UART1 45
63ddc5b0 84#define MX25_INT_FEC 57
a759544f 85
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86#define MX25_DMA_REQ_SSI2_RX1 22
87#define MX25_DMA_REQ_SSI2_TX1 23
88#define MX25_DMA_REQ_SSI2_RX0 24
89#define MX25_DMA_REQ_SSI2_TX0 25
90#define MX25_DMA_REQ_SSI1_RX1 26
91#define MX25_DMA_REQ_SSI1_TX1 27
92#define MX25_DMA_REQ_SSI1_RX0 28
93#define MX25_DMA_REQ_SSI1_TX0 29
94
3cdd5441 95#endif /* ifndef __MACH_MX25_H__ */