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f31405cc JB |
1 | /* |
2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
3 | * Copyright 2008 Juergen Beisert, kernel@pengutronix.de | |
4 | * | |
260a1fd2 HS |
5 | * This contains i.MX27-specific hardware definitions. For those |
6 | * hardware pieces that are common between i.MX21 and i.MX27, have a | |
7 | * look at mx2x.h. | |
8 | * | |
f31405cc JB |
9 | * This program is free software; you can redistribute it and/or |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version 2 | |
12 | * of the License, or (at your option) any later version. | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
21 | * MA 02110-1301, USA. | |
22 | */ | |
23 | ||
3cdd5441 UKK |
24 | #ifndef __MACH_MX27_H__ |
25 | #define __MACH_MX27_H__ | |
f31405cc | 26 | |
2ae959f4 UKK |
27 | #define MX27_AIPI_BASE_ADDR 0x10000000 |
28 | #define MX27_AIPI_BASE_ADDR_VIRT 0xf4000000 | |
29 | #define MX27_AIPI_SIZE SZ_1M | |
30 | #define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000) | |
31 | #define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000) | |
32 | #define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000) | |
33 | #define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000) | |
34 | #define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000) | |
35 | #define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000) | |
36 | #define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000) | |
37 | #define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000) | |
38 | #define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000) | |
39 | #define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000) | |
40 | #define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000) | |
41 | #define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000) | |
42 | #define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000) | |
43 | #define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000) | |
44 | #define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000) | |
45 | #define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000) | |
46 | #define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000) | |
47 | #define MX27_I2C_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000) | |
48 | #define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000) | |
49 | #define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000) | |
50 | #define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000) | |
51 | #define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000) | |
52 | #define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000) | |
53 | #define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000) | |
54 | #define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000) | |
55 | #define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000) | |
56 | #define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000) | |
57 | #define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000) | |
58 | #define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000) | |
59 | #define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000) | |
60 | #define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000) | |
61 | #define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000) | |
62 | #define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000) | |
63 | #define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000) | |
64 | #define MX27_USBOTG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000) | |
65 | #define MX27_OTG_BASE_ADDR MX27_USBOTG_BASE_ADDR | |
66 | #define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000) | |
67 | #define MX27_EMMA_PP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000) | |
68 | #define MX27_EMMA_PRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400) | |
69 | #define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000) | |
70 | #define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800) | |
71 | #define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000) | |
72 | #define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000) | |
73 | #define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000) | |
74 | #define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000) | |
75 | #define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000) | |
76 | #define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000) | |
77 | #define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000) | |
78 | #define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000) | |
79 | ||
80 | #define MX27_AVIC_BASE_ADDR 0x10040000 | |
f31405cc | 81 | |
260a1fd2 | 82 | /* ROM patch */ |
26b10e74 | 83 | #define MX27_ROMP_BASE_ADDR 0x10041000 |
f31405cc | 84 | |
2ae959f4 UKK |
85 | #define MX27_SAHB1_BASE_ADDR 0x80000000 |
86 | #define MX27_SAHB1_BASE_ADDR_VIRT 0xf4100000 | |
87 | #define MX27_SAHB1_SIZE SZ_1M | |
88 | #define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000) | |
89 | #define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000) | |
f31405cc | 90 | |
f31405cc | 91 | /* Memory regions and CS */ |
26b10e74 UKK |
92 | #define MX27_SDRAM_BASE_ADDR 0xa0000000 |
93 | #define MX27_CSD1_BASE_ADDR 0xb0000000 | |
f31405cc | 94 | |
26b10e74 UKK |
95 | #define MX27_CS0_BASE_ADDR 0xc0000000 |
96 | #define MX27_CS1_BASE_ADDR 0xc8000000 | |
97 | #define MX27_CS2_BASE_ADDR 0xd0000000 | |
98 | #define MX27_CS3_BASE_ADDR 0xd2000000 | |
99 | #define MX27_CS4_BASE_ADDR 0xd4000000 | |
100 | #define MX27_CS5_BASE_ADDR 0xd6000000 | |
f31405cc | 101 | |
260a1fd2 | 102 | /* NAND, SDRAM, WEIM, M3IF, EMI controllers */ |
26b10e74 UKK |
103 | #define MX27_X_MEMC_BASE_ADDR 0xd8000000 |
104 | #define MX27_X_MEMC_BASE_ADDR_VIRT 0xf4200000 | |
105 | #define MX27_X_MEMC_SIZE SZ_1M | |
106 | #define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR) | |
107 | #define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000) | |
108 | #define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000) | |
109 | #define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000) | |
110 | #define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000) | |
f31405cc | 111 | |
26b10e74 | 112 | #define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000 |
f73a42f7 UKK |
113 | |
114 | /* IRAM */ | |
26b10e74 | 115 | #define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */ |
f73a42f7 | 116 | |
bc9ea6c7 UKK |
117 | #define MX27_IO_ADDRESS(x) ( \ |
118 | IMX_IO_ADDRESS(x, MX27_AIPI) ?: \ | |
119 | IMX_IO_ADDRESS(x, MX27_SAHB1) ?: \ | |
120 | IMX_IO_ADDRESS(x, MX27_X_MEMC)) | |
121 | ||
260a1fd2 | 122 | /* fixed interrupt numbers */ |
26b10e74 UKK |
123 | #define MX27_INT_I2C2 1 |
124 | #define MX27_INT_GPT6 2 | |
125 | #define MX27_INT_GPT5 3 | |
126 | #define MX27_INT_GPT4 4 | |
127 | #define MX27_INT_RTIC 5 | |
2ae959f4 | 128 | #define MX27_INT_CSPI3 6 |
26b10e74 | 129 | #define MX27_INT_SDHC 7 |
2ae959f4 | 130 | #define MX27_INT_GPIO 8 |
26b10e74 | 131 | #define MX27_INT_SDHC3 9 |
2ae959f4 UKK |
132 | #define MX27_INT_SDHC2 10 |
133 | #define MX27_INT_SDHC1 11 | |
134 | #define MX27_INT_I2C 12 | |
135 | #define MX27_INT_SSI2 13 | |
136 | #define MX27_INT_SSI1 14 | |
137 | #define MX27_INT_CSPI2 15 | |
138 | #define MX27_INT_CSPI1 16 | |
139 | #define MX27_INT_UART4 17 | |
140 | #define MX27_INT_UART3 18 | |
141 | #define MX27_INT_UART2 19 | |
142 | #define MX27_INT_UART1 20 | |
143 | #define MX27_INT_KPP 21 | |
144 | #define MX27_INT_RTC 22 | |
145 | #define MX27_INT_PWM 23 | |
146 | #define MX27_INT_GPT3 24 | |
147 | #define MX27_INT_GPT2 25 | |
148 | #define MX27_INT_GPT1 26 | |
149 | #define MX27_INT_WDOG 27 | |
150 | #define MX27_INT_PCMCIA 28 | |
151 | #define MX27_INT_NANDFC 29 | |
26b10e74 | 152 | #define MX27_INT_ATA 30 |
2ae959f4 UKK |
153 | #define MX27_INT_CSI 31 |
154 | #define MX27_INT_DMACH0 32 | |
155 | #define MX27_INT_DMACH1 33 | |
156 | #define MX27_INT_DMACH2 34 | |
157 | #define MX27_INT_DMACH3 35 | |
158 | #define MX27_INT_DMACH4 36 | |
159 | #define MX27_INT_DMACH5 37 | |
160 | #define MX27_INT_DMACH6 38 | |
161 | #define MX27_INT_DMACH7 39 | |
162 | #define MX27_INT_DMACH8 40 | |
163 | #define MX27_INT_DMACH9 41 | |
164 | #define MX27_INT_DMACH10 42 | |
165 | #define MX27_INT_DMACH11 43 | |
166 | #define MX27_INT_DMACH12 44 | |
167 | #define MX27_INT_DMACH13 45 | |
168 | #define MX27_INT_DMACH14 46 | |
169 | #define MX27_INT_DMACH15 47 | |
26b10e74 UKK |
170 | #define MX27_INT_UART6 48 |
171 | #define MX27_INT_UART5 49 | |
172 | #define MX27_INT_FEC 50 | |
2ae959f4 UKK |
173 | #define MX27_INT_EMMAPRP 51 |
174 | #define MX27_INT_EMMAPP 52 | |
26b10e74 UKK |
175 | #define MX27_INT_VPU 53 |
176 | #define MX27_INT_USB1 54 | |
177 | #define MX27_INT_USB2 55 | |
178 | #define MX27_INT_USB3 56 | |
179 | #define MX27_INT_SCC_SMN 57 | |
180 | #define MX27_INT_SCC_SCM 58 | |
181 | #define MX27_INT_SAHARA 59 | |
2ae959f4 UKK |
182 | #define MX27_INT_SLCDC 60 |
183 | #define MX27_INT_LCDC 61 | |
26b10e74 UKK |
184 | #define MX27_INT_IIM 62 |
185 | #define MX27_INT_CCM 63 | |
f31405cc JB |
186 | |
187 | /* fixed DMA request numbers */ | |
2ae959f4 UKK |
188 | #define MX27_DMA_REQ_CSPI3_RX 1 |
189 | #define MX27_DMA_REQ_CSPI3_TX 2 | |
190 | #define MX27_DMA_REQ_EXT 3 | |
26b10e74 | 191 | #define MX27_DMA_REQ_MSHC 4 |
2ae959f4 UKK |
192 | #define MX27_DMA_REQ_SDHC2 6 |
193 | #define MX27_DMA_REQ_SDHC1 7 | |
194 | #define MX27_DMA_REQ_SSI2_RX0 8 | |
195 | #define MX27_DMA_REQ_SSI2_TX0 9 | |
196 | #define MX27_DMA_REQ_SSI2_RX1 10 | |
197 | #define MX27_DMA_REQ_SSI2_TX1 11 | |
198 | #define MX27_DMA_REQ_SSI1_RX0 12 | |
199 | #define MX27_DMA_REQ_SSI1_TX0 13 | |
200 | #define MX27_DMA_REQ_SSI1_RX1 14 | |
201 | #define MX27_DMA_REQ_SSI1_TX1 15 | |
202 | #define MX27_DMA_REQ_CSPI2_RX 16 | |
203 | #define MX27_DMA_REQ_CSPI2_TX 17 | |
204 | #define MX27_DMA_REQ_CSPI1_RX 18 | |
205 | #define MX27_DMA_REQ_CSPI1_TX 19 | |
206 | #define MX27_DMA_REQ_UART4_RX 20 | |
207 | #define MX27_DMA_REQ_UART4_TX 21 | |
208 | #define MX27_DMA_REQ_UART3_RX 22 | |
209 | #define MX27_DMA_REQ_UART3_TX 23 | |
210 | #define MX27_DMA_REQ_UART2_RX 24 | |
211 | #define MX27_DMA_REQ_UART2_TX 25 | |
212 | #define MX27_DMA_REQ_UART1_RX 26 | |
213 | #define MX27_DMA_REQ_UART1_TX 27 | |
26b10e74 UKK |
214 | #define MX27_DMA_REQ_ATA_TX 28 |
215 | #define MX27_DMA_REQ_ATA_RCV 29 | |
2ae959f4 UKK |
216 | #define MX27_DMA_REQ_CSI_STAT 30 |
217 | #define MX27_DMA_REQ_CSI_RX 31 | |
26b10e74 UKK |
218 | #define MX27_DMA_REQ_UART5_TX 32 |
219 | #define MX27_DMA_REQ_UART5_RX 33 | |
220 | #define MX27_DMA_REQ_UART6_TX 34 | |
221 | #define MX27_DMA_REQ_UART6_RX 35 | |
222 | #define MX27_DMA_REQ_SDHC3 36 | |
223 | #define MX27_DMA_REQ_NFC 37 | |
f31405cc JB |
224 | |
225 | /* silicon revisions specific to i.MX27 */ | |
226 | #define CHIP_REV_1_0 0x00 | |
227 | #define CHIP_REV_2_0 0x01 | |
228 | ||
229 | #ifndef __ASSEMBLY__ | |
230 | extern int mx27_revision(void); | |
231 | #endif | |
232 | ||
aae70193 | 233 | #ifdef IMX_NEEDS_DEPRECATED_SYMBOLS |
26b10e74 UKK |
234 | /* these should go away */ |
235 | #define MSHC_BASE_ADDR MX27_MSHC_BASE_ADDR | |
236 | #define GPT5_BASE_ADDR MX27_GPT5_BASE_ADDR | |
237 | #define GPT4_BASE_ADDR MX27_GPT4_BASE_ADDR | |
238 | #define UART5_BASE_ADDR MX27_UART5_BASE_ADDR | |
239 | #define UART6_BASE_ADDR MX27_UART6_BASE_ADDR | |
240 | #define I2C2_BASE_ADDR MX27_I2C2_BASE_ADDR | |
241 | #define SDHC3_BASE_ADDR MX27_SDHC3_BASE_ADDR | |
242 | #define GPT6_BASE_ADDR MX27_GPT6_BASE_ADDR | |
243 | #define VPU_BASE_ADDR MX27_VPU_BASE_ADDR | |
244 | #define OTG_BASE_ADDR MX27_OTG_BASE_ADDR | |
245 | #define SAHARA_BASE_ADDR MX27_SAHARA_BASE_ADDR | |
246 | #define IIM_BASE_ADDR MX27_IIM_BASE_ADDR | |
247 | #define RTIC_BASE_ADDR MX27_RTIC_BASE_ADDR | |
248 | #define FEC_BASE_ADDR MX27_FEC_BASE_ADDR | |
249 | #define SCC_BASE_ADDR MX27_SCC_BASE_ADDR | |
250 | #define ETB_BASE_ADDR MX27_ETB_BASE_ADDR | |
251 | #define ETB_RAM_BASE_ADDR MX27_ETB_RAM_BASE_ADDR | |
252 | #define ROMP_BASE_ADDR MX27_ROMP_BASE_ADDR | |
253 | #define ATA_BASE_ADDR MX27_ATA_BASE_ADDR | |
254 | #define SDRAM_BASE_ADDR MX27_SDRAM_BASE_ADDR | |
255 | #define CSD1_BASE_ADDR MX27_CSD1_BASE_ADDR | |
256 | #define CS0_BASE_ADDR MX27_CS0_BASE_ADDR | |
257 | #define CS1_BASE_ADDR MX27_CS1_BASE_ADDR | |
258 | #define CS2_BASE_ADDR MX27_CS2_BASE_ADDR | |
259 | #define CS3_BASE_ADDR MX27_CS3_BASE_ADDR | |
260 | #define CS4_BASE_ADDR MX27_CS4_BASE_ADDR | |
261 | #define CS5_BASE_ADDR MX27_CS5_BASE_ADDR | |
262 | #define X_MEMC_BASE_ADDR MX27_X_MEMC_BASE_ADDR | |
263 | #define X_MEMC_BASE_ADDR_VIRT MX27_X_MEMC_BASE_ADDR_VIRT | |
264 | #define X_MEMC_SIZE MX27_X_MEMC_SIZE | |
265 | #define NFC_BASE_ADDR MX27_NFC_BASE_ADDR | |
266 | #define SDRAMC_BASE_ADDR MX27_SDRAMC_BASE_ADDR | |
267 | #define WEIM_BASE_ADDR MX27_WEIM_BASE_ADDR | |
268 | #define M3IF_BASE_ADDR MX27_M3IF_BASE_ADDR | |
269 | #define PCMCIA_CTL_BASE_ADDR MX27_PCMCIA_CTL_BASE_ADDR | |
270 | #define PCMCIA_MEM_BASE_ADDR MX27_PCMCIA_MEM_BASE_ADDR | |
271 | #define IRAM_BASE_ADDR MX27_IRAM_BASE_ADDR | |
272 | #define MXC_INT_I2C2 MX27_INT_I2C2 | |
273 | #define MXC_INT_GPT6 MX27_INT_GPT6 | |
274 | #define MXC_INT_GPT5 MX27_INT_GPT5 | |
275 | #define MXC_INT_GPT4 MX27_INT_GPT4 | |
276 | #define MXC_INT_RTIC MX27_INT_RTIC | |
277 | #define MXC_INT_SDHC MX27_INT_SDHC | |
278 | #define MXC_INT_SDHC3 MX27_INT_SDHC3 | |
279 | #define MXC_INT_ATA MX27_INT_ATA | |
280 | #define MXC_INT_UART6 MX27_INT_UART6 | |
281 | #define MXC_INT_UART5 MX27_INT_UART5 | |
282 | #define MXC_INT_FEC MX27_INT_FEC | |
283 | #define MXC_INT_VPU MX27_INT_VPU | |
284 | #define MXC_INT_USB1 MX27_INT_USB1 | |
285 | #define MXC_INT_USB2 MX27_INT_USB2 | |
286 | #define MXC_INT_USB3 MX27_INT_USB3 | |
287 | #define MXC_INT_SCC_SMN MX27_INT_SCC_SMN | |
288 | #define MXC_INT_SCC_SCM MX27_INT_SCC_SCM | |
289 | #define MXC_INT_SAHARA MX27_INT_SAHARA | |
290 | #define MXC_INT_IIM MX27_INT_IIM | |
291 | #define MXC_INT_CCM MX27_INT_CCM | |
292 | #define DMA_REQ_MSHC MX27_DMA_REQ_MSHC | |
293 | #define DMA_REQ_ATA_TX MX27_DMA_REQ_ATA_TX | |
294 | #define DMA_REQ_ATA_RCV MX27_DMA_REQ_ATA_RCV | |
295 | #define DMA_REQ_UART5_TX MX27_DMA_REQ_UART5_TX | |
296 | #define DMA_REQ_UART5_RX MX27_DMA_REQ_UART5_RX | |
297 | #define DMA_REQ_UART6_TX MX27_DMA_REQ_UART6_TX | |
298 | #define DMA_REQ_UART6_RX MX27_DMA_REQ_UART6_RX | |
299 | #define DMA_REQ_SDHC3 MX27_DMA_REQ_SDHC3 | |
300 | #define DMA_REQ_NFC MX27_DMA_REQ_NFC | |
aae70193 | 301 | #endif |
f31405cc | 302 | |
3cdd5441 | 303 | #endif /* ifndef __MACH_MX27_H__ */ |