[mirror_ubuntu-eoan-kernel.git] / arch / arm / plat-mxc / irq.c

/*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA  02110-1301, USA.
 */

#include <linux/module.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <mach/common.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>

#define AVIC_BASE		IO_ADDRESS(AVIC_BASE_ADDR)
#define AVIC_INTCNTL		(AVIC_BASE + 0x00)	/* int control reg */
#define AVIC_NIMASK		(AVIC_BASE + 0x04)	/* int mask reg */
#define AVIC_INTENNUM		(AVIC_BASE + 0x08)	/* int enable number reg */
#define AVIC_INTDISNUM		(AVIC_BASE + 0x0C)	/* int disable number reg */
#define AVIC_INTENABLEH		(AVIC_BASE + 0x10)	/* int enable reg high */
#define AVIC_INTENABLEL		(AVIC_BASE + 0x14)	/* int enable reg low */
#define AVIC_INTTYPEH		(AVIC_BASE + 0x18)	/* int type reg high */
#define AVIC_INTTYPEL		(AVIC_BASE + 0x1C)	/* int type reg low */
#define AVIC_NIPRIORITY(x)	(AVIC_BASE + (0x20 + 4 * (7 - (x)))) /* int priority */
#define AVIC_NIVECSR		(AVIC_BASE + 0x40)	/* norm int vector/status */
#define AVIC_FIVECSR		(AVIC_BASE + 0x44)	/* fast int vector/status */
#define AVIC_INTSRCH		(AVIC_BASE + 0x48)	/* int source reg high */
#define AVIC_INTSRCL		(AVIC_BASE + 0x4C)	/* int source reg low */
#define AVIC_INTFRCH		(AVIC_BASE + 0x50)	/* int force reg high */
#define AVIC_INTFRCL		(AVIC_BASE + 0x54)	/* int force reg low */
#define AVIC_NIPNDH		(AVIC_BASE + 0x58)	/* norm int pending high */
#define AVIC_NIPNDL		(AVIC_BASE + 0x5C)	/* norm int pending low */
#define AVIC_FIPNDH		(AVIC_BASE + 0x60)	/* fast int pending high */
#define AVIC_FIPNDL		(AVIC_BASE + 0x64)	/* fast int pending low */

int imx_irq_set_priority(unsigned char irq, unsigned char prio)
{
#ifdef CONFIG_MXC_IRQ_PRIOR
	unsigned int temp;
	unsigned int mask = 0x0F << irq % 8 * 4;

	if (irq >= MXC_INTERNAL_IRQS)
		return -EINVAL;;

	temp = __raw_readl(AVIC_NIPRIORITY(irq / 8));
	temp &= ~mask;
	temp |= prio & mask;

	__raw_writel(temp, AVIC_NIPRIORITY(irq / 8));

	return 0;
#else
	return -ENOSYS;
#endif
}
EXPORT_SYMBOL(imx_irq_set_priority);

#ifdef CONFIG_FIQ
int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
{
	unsigned int irqt;

	if (irq >= MXC_INTERNAL_IRQS)
		return -EINVAL;

	if (irq < MXC_INTERNAL_IRQS / 2) {
		irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq);
		__raw_writel(irqt | (!!type << irq), AVIC_INTTYPEL);
	} else {
		irq -= MXC_INTERNAL_IRQS / 2;
		irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq);
		__raw_writel(irqt | (!!type << irq), AVIC_INTTYPEH);
	}

	return 0;
}
EXPORT_SYMBOL(mxc_set_irq_fiq);
#endif /* CONFIG_FIQ */

/* Disable interrupt number "irq" in the AVIC */
static void mxc_mask_irq(unsigned int irq)
{
	__raw_writel(irq, AVIC_INTDISNUM);
}

/* Enable interrupt number "irq" in the AVIC */
static void mxc_unmask_irq(unsigned int irq)
{
	__raw_writel(irq, AVIC_INTENNUM);
}

static struct irq_chip mxc_avic_chip = {
	.ack = mxc_mask_irq,
	.mask = mxc_mask_irq,
	.unmask = mxc_unmask_irq,
};

/*
 * This function initializes the AVIC hardware and disables all the
 * interrupts. It registers the interrupt enable and disable functions
 * to the kernel for each interrupt source.
 */
void __init mxc_init_irq(void)
{
	int i;

	/* put the AVIC into the reset value with
	 * all interrupts disabled
	 */
	__raw_writel(0, AVIC_INTCNTL);
	__raw_writel(0x1f, AVIC_NIMASK);

	/* disable all interrupts */
	__raw_writel(0, AVIC_INTENABLEH);
	__raw_writel(0, AVIC_INTENABLEL);

	/* all IRQ no FIQ */
	__raw_writel(0, AVIC_INTTYPEH);
	__raw_writel(0, AVIC_INTTYPEL);
	for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
		set_irq_chip(i, &mxc_avic_chip);
		set_irq_handler(i, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}

	/* Set default priority value (0) for all IRQ's */
	for (i = 0; i < 8; i++)
		__raw_writel(0, AVIC_NIPRIORITY(i));

	/* init architectures chained interrupt handler */
	mxc_register_gpios();

#ifdef CONFIG_FIQ
	/* Initialize FIQ */
	init_FIQ();
#endif

	printk(KERN_INFO "MXC IRQ initialized\n");
}
Commit	Line	Data
52c543f9	1	/*
259bcaae JB	2	* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	*
	5	* This program is free software; you can redistribute it and/or
	6	* modify it under the terms of the GNU General Public License
	7	* as published by the Free Software Foundation; either version 2
	8	* of the License, or (at your option) any later version.
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	17	* MA 02110-1301, USA.
52c543f9 QJ	18	*/
52c543f9 QJ	19
d7927e19	20	#include <linux/module.h>
259bcaae	21	#include <linux/irq.h>
fced80c7	22	#include <linux/io.h>
a09e64fb	23	#include <mach/common.h>
d7927e19	24	#include <asm/mach/irq.h>
a2449091	25	#include <mach/hardware.h>
52c543f9	26
259bcaae JB	27	#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
	28	#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
	29	#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
	30	#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
	31	#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
	32	#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
	33	#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
	34	#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
	35	#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
479c901f	36	#define AVIC_NIPRIORITY(x) (AVIC_BASE + (0x20 + 4 * (7 - (x)))) /* int priority */
259bcaae JB	37	#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
	38	#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
	39	#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
	40	#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
	41	#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
	42	#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
	43	#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
	44	#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
	45	#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
	46	#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
	47
3f203016	48	int imx_irq_set_priority(unsigned char irq, unsigned char prio)
479c901f	49	{
3f203016	50	#ifdef CONFIG_MXC_IRQ_PRIOR
479c901f DA	51	unsigned int temp;
	52	unsigned int mask = 0x0F << irq % 8 * 4;
	53
3f203016 DA	54	if (irq >= MXC_INTERNAL_IRQS)
3f203016 DA	55	return -EINVAL;;
479c901f DA	56
	57	temp = __raw_readl(AVIC_NIPRIORITY(irq / 8));
	58	temp &= ~mask;
	59	temp \|= prio & mask;
	60
	61	__raw_writel(temp, AVIC_NIPRIORITY(irq / 8));
3f203016 DA	62
	63	return 0;
	64	#else
	65	return -ENOSYS;
	66	#endif
479c901f DA	67	}
479c901f DA	68	EXPORT_SYMBOL(imx_irq_set_priority);
479c901f	69
d7927e19 PZ	70	#ifdef CONFIG_FIQ
	71	int mxc_set_irq_fiq(unsigned int irq, unsigned int type)
	72	{
	73	unsigned int irqt;
	74
9d631b83	75	if (irq >= MXC_INTERNAL_IRQS)
d7927e19 PZ	76	return -EINVAL;
d7927e19 PZ	77
9d631b83	78	if (irq < MXC_INTERNAL_IRQS / 2) {
d7927e19 PZ	79	irqt = __raw_readl(AVIC_INTTYPEL) & ~(1 << irq);
	80	__raw_writel(irqt \| (!!type << irq), AVIC_INTTYPEL);
	81	} else {
9d631b83	82	irq -= MXC_INTERNAL_IRQS / 2;
d7927e19 PZ	83	irqt = __raw_readl(AVIC_INTTYPEH) & ~(1 << irq);
	84	__raw_writel(irqt \| (!!type << irq), AVIC_INTTYPEH);
	85	}
	86
	87	return 0;
	88	}
	89	EXPORT_SYMBOL(mxc_set_irq_fiq);
	90	#endif /* CONFIG_FIQ */
	91
2c130fd5	92	/* Disable interrupt number "irq" in the AVIC */
52c543f9 QJ	93	static void mxc_mask_irq(unsigned int irq)
	94	{
	95	__raw_writel(irq, AVIC_INTDISNUM);
	96	}
	97
2c130fd5	98	/* Enable interrupt number "irq" in the AVIC */
52c543f9 QJ	99	static void mxc_unmask_irq(unsigned int irq)
	100	{
	101	__raw_writel(irq, AVIC_INTENNUM);
	102	}
	103
	104	static struct irq_chip mxc_avic_chip = {
259bcaae	105	.ack = mxc_mask_irq,
52c543f9 QJ	106	.mask = mxc_mask_irq,
	107	.unmask = mxc_unmask_irq,
	108	};
	109
2c130fd5	110	/*
52c543f9 QJ	111	* This function initializes the AVIC hardware and disables all the
	112	* interrupts. It registers the interrupt enable and disable functions
	113	* to the kernel for each interrupt source.
	114	*/
	115	void __init mxc_init_irq(void)
	116	{
	117	int i;
52c543f9 QJ	118
	119	/* put the AVIC into the reset value with
	120	* all interrupts disabled
	121	*/
	122	__raw_writel(0, AVIC_INTCNTL);
	123	__raw_writel(0x1f, AVIC_NIMASK);
	124
	125	/* disable all interrupts */
	126	__raw_writel(0, AVIC_INTENABLEH);
	127	__raw_writel(0, AVIC_INTENABLEL);
	128
	129	/* all IRQ no FIQ */
	130	__raw_writel(0, AVIC_INTTYPEH);
	131	__raw_writel(0, AVIC_INTTYPEL);
9d631b83	132	for (i = 0; i < MXC_INTERNAL_IRQS; i++) {
52c543f9 QJ	133	set_irq_chip(i, &mxc_avic_chip);
	134	set_irq_handler(i, handle_level_irq);
	135	set_irq_flags(i, IRQF_VALID);
	136	}
	137
479c901f DA	138	/* Set default priority value (0) for all IRQ's */
	139	for (i = 0; i < 8; i++)
	140	__raw_writel(0, AVIC_NIPRIORITY(i));
52c543f9	141
07bd1a6c JB	142	/* init architectures chained interrupt handler */
	143	mxc_register_gpios();
	144
d7927e19 PZ	145	#ifdef CONFIG_FIQ
	146	/* Initialize FIQ */
	147	init_FIQ();
	148	#endif
	149
52c543f9 QJ	150	printk(KERN_INFO "MXC IRQ initialized\n");
52c543f9 QJ	151	}