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2ec1d359 AR |
1 | /* |
2 | * Generic GPIO driver for logic cells found in the Nomadik SoC | |
3 | * | |
4 | * Copyright (C) 2008,2009 STMicroelectronics | |
5 | * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> | |
6 | * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/init.h> | |
15 | #include <linux/device.h> | |
3e3c62ca | 16 | #include <linux/platform_device.h> |
2ec1d359 | 17 | #include <linux/io.h> |
af7dc228 RV |
18 | #include <linux/clk.h> |
19 | #include <linux/err.h> | |
2ec1d359 AR |
20 | #include <linux/gpio.h> |
21 | #include <linux/spinlock.h> | |
22 | #include <linux/interrupt.h> | |
23 | #include <linux/irq.h> | |
5a0e3ad6 | 24 | #include <linux/slab.h> |
2ec1d359 | 25 | |
378be066 | 26 | #include <plat/pincfg.h> |
2ec1d359 AR |
27 | #include <mach/hardware.h> |
28 | #include <mach/gpio.h> | |
29 | ||
30 | /* | |
31 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | |
32 | * AMBA device, managing 32 pins and alternate functions. The logic block | |
9c66ee6f | 33 | * is currently used in the Nomadik and ux500. |
2ec1d359 AR |
34 | * |
35 | * Symbols in this file are called "nmk_gpio" for "nomadik gpio" | |
36 | */ | |
37 | ||
01727e61 RV |
38 | #define NMK_GPIO_PER_CHIP 32 |
39 | ||
2ec1d359 AR |
40 | struct nmk_gpio_chip { |
41 | struct gpio_chip chip; | |
42 | void __iomem *addr; | |
af7dc228 | 43 | struct clk *clk; |
33b744b3 | 44 | unsigned int bank; |
2ec1d359 | 45 | unsigned int parent_irq; |
2c8bb0eb | 46 | int secondary_parent_irq; |
33b744b3 | 47 | u32 (*get_secondary_status)(unsigned int bank); |
01727e61 | 48 | void (*set_ioforce)(bool enable); |
c0fcb8db | 49 | spinlock_t lock; |
2ec1d359 AR |
50 | /* Keep track of configured edges */ |
51 | u32 edge_rising; | |
52 | u32 edge_falling; | |
b9df468d RV |
53 | u32 real_wake; |
54 | u32 rwimsc; | |
55 | u32 fwimsc; | |
56 | u32 slpm; | |
d1118f68 | 57 | u32 enabled; |
2ec1d359 AR |
58 | }; |
59 | ||
01727e61 RV |
60 | static struct nmk_gpio_chip * |
61 | nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; | |
62 | ||
63 | static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); | |
64 | ||
65 | #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) | |
66 | ||
6f9a974c RV |
67 | static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, |
68 | unsigned offset, int gpio_mode) | |
69 | { | |
70 | u32 bit = 1 << offset; | |
71 | u32 afunc, bfunc; | |
72 | ||
73 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; | |
74 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; | |
75 | if (gpio_mode & NMK_GPIO_ALT_A) | |
76 | afunc |= bit; | |
77 | if (gpio_mode & NMK_GPIO_ALT_B) | |
78 | bfunc |= bit; | |
79 | writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); | |
80 | writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); | |
81 | } | |
82 | ||
81a3c298 RV |
83 | static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, |
84 | unsigned offset, enum nmk_gpio_slpm mode) | |
85 | { | |
86 | u32 bit = 1 << offset; | |
87 | u32 slpm; | |
88 | ||
89 | slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); | |
90 | if (mode == NMK_GPIO_SLPM_NOCHANGE) | |
91 | slpm |= bit; | |
92 | else | |
93 | slpm &= ~bit; | |
94 | writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); | |
95 | } | |
96 | ||
5b327edf RV |
97 | static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, |
98 | unsigned offset, enum nmk_gpio_pull pull) | |
99 | { | |
100 | u32 bit = 1 << offset; | |
101 | u32 pdis; | |
102 | ||
103 | pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); | |
104 | if (pull == NMK_GPIO_PULL_NONE) | |
105 | pdis |= bit; | |
106 | else | |
107 | pdis &= ~bit; | |
108 | writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); | |
109 | ||
5317e4d1 | 110 | if (pull == NMK_GPIO_PULL_UP) |
5b327edf | 111 | writel(bit, nmk_chip->addr + NMK_GPIO_DATS); |
5317e4d1 | 112 | else if (pull == NMK_GPIO_PULL_DOWN) |
5b327edf RV |
113 | writel(bit, nmk_chip->addr + NMK_GPIO_DATC); |
114 | } | |
115 | ||
378be066 RV |
116 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
117 | unsigned offset) | |
118 | { | |
119 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
120 | } | |
121 | ||
6720db7c RV |
122 | static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, |
123 | unsigned offset, int val) | |
124 | { | |
125 | if (val) | |
126 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); | |
127 | else | |
128 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); | |
129 | } | |
130 | ||
131 | static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, | |
132 | unsigned offset, int val) | |
133 | { | |
134 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); | |
135 | __nmk_gpio_set_output(nmk_chip, offset, val); | |
136 | } | |
137 | ||
01727e61 RV |
138 | static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, |
139 | unsigned offset, int gpio_mode, | |
140 | bool glitch) | |
141 | { | |
3c4bee04 LW |
142 | u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC); |
143 | u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC); | |
01727e61 RV |
144 | |
145 | if (glitch && nmk_chip->set_ioforce) { | |
146 | u32 bit = BIT(offset); | |
147 | ||
01727e61 RV |
148 | /* Prevent spurious wakeups */ |
149 | writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
150 | writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
151 | ||
152 | nmk_chip->set_ioforce(true); | |
153 | } | |
154 | ||
155 | __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); | |
156 | ||
157 | if (glitch && nmk_chip->set_ioforce) { | |
158 | nmk_chip->set_ioforce(false); | |
159 | ||
160 | writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); | |
161 | writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); | |
162 | } | |
163 | } | |
164 | ||
378be066 | 165 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
01727e61 | 166 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
378be066 RV |
167 | { |
168 | static const char *afnames[] = { | |
169 | [NMK_GPIO_ALT_GPIO] = "GPIO", | |
170 | [NMK_GPIO_ALT_A] = "A", | |
171 | [NMK_GPIO_ALT_B] = "B", | |
172 | [NMK_GPIO_ALT_C] = "C" | |
173 | }; | |
174 | static const char *pullnames[] = { | |
175 | [NMK_GPIO_PULL_NONE] = "none", | |
176 | [NMK_GPIO_PULL_UP] = "up", | |
177 | [NMK_GPIO_PULL_DOWN] = "down", | |
178 | [3] /* illegal */ = "??" | |
179 | }; | |
180 | static const char *slpmnames[] = { | |
7e3f7e59 RV |
181 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", |
182 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | |
378be066 RV |
183 | }; |
184 | ||
185 | int pin = PIN_NUM(cfg); | |
186 | int pull = PIN_PULL(cfg); | |
187 | int af = PIN_ALT(cfg); | |
188 | int slpm = PIN_SLPM(cfg); | |
6720db7c RV |
189 | int output = PIN_DIR(cfg); |
190 | int val = PIN_VAL(cfg); | |
01727e61 | 191 | bool glitch = af == NMK_GPIO_ALT_C; |
378be066 | 192 | |
dacdc96c RV |
193 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", |
194 | pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], | |
6720db7c RV |
195 | output ? "output " : "input", |
196 | output ? (val ? "high" : "low") : ""); | |
197 | ||
dacdc96c RV |
198 | if (sleep) { |
199 | int slpm_pull = PIN_SLPM_PULL(cfg); | |
200 | int slpm_output = PIN_SLPM_DIR(cfg); | |
201 | int slpm_val = PIN_SLPM_VAL(cfg); | |
202 | ||
3546d15c RV |
203 | af = NMK_GPIO_ALT_GPIO; |
204 | ||
dacdc96c RV |
205 | /* |
206 | * The SLPM_* values are normal values + 1 to allow zero to | |
207 | * mean "same as normal". | |
208 | */ | |
209 | if (slpm_pull) | |
210 | pull = slpm_pull - 1; | |
211 | if (slpm_output) | |
212 | output = slpm_output - 1; | |
213 | if (slpm_val) | |
214 | val = slpm_val - 1; | |
215 | ||
216 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | |
217 | pin, | |
218 | slpm_pull ? pullnames[pull] : "same", | |
219 | slpm_output ? (output ? "output" : "input") : "same", | |
220 | slpm_val ? (val ? "high" : "low") : "same"); | |
221 | } | |
222 | ||
6720db7c RV |
223 | if (output) |
224 | __nmk_gpio_make_output(nmk_chip, offset, val); | |
225 | else { | |
226 | __nmk_gpio_make_input(nmk_chip, offset); | |
227 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | |
228 | } | |
378be066 | 229 | |
01727e61 RV |
230 | /* |
231 | * If we've backed up the SLPM registers (glitch workaround), modify | |
232 | * the backups since they will be restored. | |
233 | */ | |
234 | if (slpmregs) { | |
235 | if (slpm == NMK_GPIO_SLPM_NOCHANGE) | |
236 | slpmregs[nmk_chip->bank] |= BIT(offset); | |
237 | else | |
238 | slpmregs[nmk_chip->bank] &= ~BIT(offset); | |
239 | } else | |
240 | __nmk_gpio_set_slpm(nmk_chip, offset, slpm); | |
241 | ||
242 | __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); | |
243 | } | |
244 | ||
245 | /* | |
246 | * Safe sequence used to switch IOs between GPIO and Alternate-C mode: | |
247 | * - Save SLPM registers | |
248 | * - Set SLPM=0 for the IOs you want to switch and others to 1 | |
249 | * - Configure the GPIO registers for the IOs that are being switched | |
250 | * - Set IOFORCE=1 | |
251 | * - Modify the AFLSA/B registers for the IOs that are being switched | |
252 | * - Set IOFORCE=0 | |
253 | * - Restore SLPM registers | |
254 | * - Any spurious wake up event during switch sequence to be ignored and | |
255 | * cleared | |
256 | */ | |
257 | static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) | |
258 | { | |
259 | int i; | |
260 | ||
261 | for (i = 0; i < NUM_BANKS; i++) { | |
262 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
263 | unsigned int temp = slpm[i]; | |
264 | ||
265 | if (!chip) | |
266 | break; | |
267 | ||
268 | slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); | |
269 | writel(temp, chip->addr + NMK_GPIO_SLPC); | |
270 | } | |
271 | } | |
272 | ||
273 | static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) | |
274 | { | |
275 | int i; | |
276 | ||
277 | for (i = 0; i < NUM_BANKS; i++) { | |
278 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
279 | ||
280 | if (!chip) | |
281 | break; | |
282 | ||
283 | writel(slpm[i], chip->addr + NMK_GPIO_SLPC); | |
284 | } | |
285 | } | |
286 | ||
287 | static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |
288 | { | |
289 | static unsigned int slpm[NUM_BANKS]; | |
290 | unsigned long flags; | |
291 | bool glitch = false; | |
292 | int ret = 0; | |
293 | int i; | |
294 | ||
295 | for (i = 0; i < num; i++) { | |
296 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { | |
297 | glitch = true; | |
298 | break; | |
299 | } | |
300 | } | |
301 | ||
302 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | |
303 | ||
304 | if (glitch) { | |
305 | memset(slpm, 0xff, sizeof(slpm)); | |
306 | ||
307 | for (i = 0; i < num; i++) { | |
308 | int pin = PIN_NUM(cfgs[i]); | |
309 | int offset = pin % NMK_GPIO_PER_CHIP; | |
310 | ||
311 | if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) | |
312 | slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); | |
313 | } | |
314 | ||
315 | nmk_gpio_glitch_slpm_init(slpm); | |
316 | } | |
317 | ||
318 | for (i = 0; i < num; i++) { | |
319 | struct nmk_gpio_chip *nmk_chip; | |
320 | int pin = PIN_NUM(cfgs[i]); | |
321 | ||
6845664a | 322 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); |
01727e61 RV |
323 | if (!nmk_chip) { |
324 | ret = -EINVAL; | |
325 | break; | |
326 | } | |
327 | ||
328 | spin_lock(&nmk_chip->lock); | |
329 | __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base, | |
330 | cfgs[i], sleep, glitch ? slpm : NULL); | |
331 | spin_unlock(&nmk_chip->lock); | |
332 | } | |
333 | ||
334 | if (glitch) | |
335 | nmk_gpio_glitch_slpm_restore(slpm); | |
336 | ||
337 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
338 | ||
339 | return ret; | |
378be066 RV |
340 | } |
341 | ||
342 | /** | |
343 | * nmk_config_pin - configure a pin's mux attributes | |
344 | * @cfg: pin confguration | |
345 | * | |
346 | * Configures a pin's mode (alternate function or GPIO), its pull up status, | |
347 | * and its sleep mode based on the specified configuration. The @cfg is | |
348 | * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These | |
349 | * are constructed using, and can be further enhanced with, the macros in | |
350 | * plat/pincfg.h. | |
351 | * | |
352 | * If a pin's mode is set to GPIO, it is configured as an input to avoid | |
353 | * side-effects. The gpio can be manipulated later using standard GPIO API | |
354 | * calls. | |
355 | */ | |
dacdc96c | 356 | int nmk_config_pin(pin_cfg_t cfg, bool sleep) |
378be066 | 357 | { |
01727e61 | 358 | return __nmk_config_pins(&cfg, 1, sleep); |
378be066 RV |
359 | } |
360 | EXPORT_SYMBOL(nmk_config_pin); | |
361 | ||
362 | /** | |
363 | * nmk_config_pins - configure several pins at once | |
364 | * @cfgs: array of pin configurations | |
365 | * @num: number of elments in the array | |
366 | * | |
367 | * Configures several pins using nmk_config_pin(). Refer to that function for | |
368 | * further information. | |
369 | */ | |
370 | int nmk_config_pins(pin_cfg_t *cfgs, int num) | |
371 | { | |
01727e61 | 372 | return __nmk_config_pins(cfgs, num, false); |
378be066 RV |
373 | } |
374 | EXPORT_SYMBOL(nmk_config_pins); | |
375 | ||
dacdc96c RV |
376 | int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) |
377 | { | |
01727e61 | 378 | return __nmk_config_pins(cfgs, num, true); |
dacdc96c RV |
379 | } |
380 | EXPORT_SYMBOL(nmk_config_pins_sleep); | |
381 | ||
81a3c298 RV |
382 | /** |
383 | * nmk_gpio_set_slpm() - configure the sleep mode of a pin | |
384 | * @gpio: pin number | |
385 | * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, | |
386 | * | |
387 | * Sets the sleep mode of a pin. If @mode is NMK_GPIO_SLPM_INPUT, the pin is | |
388 | * changed to an input (with pullup/down enabled) in sleep and deep sleep. If | |
389 | * @mode is NMK_GPIO_SLPM_NOCHANGE, the pin remains in the state it was | |
390 | * configured even when in sleep and deep sleep. | |
7e3f7e59 RV |
391 | * |
392 | * On DB8500v2 onwards, this setting loses the previous meaning and instead | |
393 | * indicates if wakeup detection is enabled on the pin. Note that | |
394 | * enable_irq_wake() will automatically enable wakeup detection. | |
81a3c298 RV |
395 | */ |
396 | int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |
397 | { | |
398 | struct nmk_gpio_chip *nmk_chip; | |
399 | unsigned long flags; | |
400 | ||
6845664a | 401 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
81a3c298 RV |
402 | if (!nmk_chip) |
403 | return -EINVAL; | |
404 | ||
01727e61 RV |
405 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
406 | spin_lock(&nmk_chip->lock); | |
407 | ||
81a3c298 | 408 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); |
01727e61 RV |
409 | |
410 | spin_unlock(&nmk_chip->lock); | |
411 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
81a3c298 RV |
412 | |
413 | return 0; | |
414 | } | |
415 | ||
5b327edf RV |
416 | /** |
417 | * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio | |
418 | * @gpio: pin number | |
419 | * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE | |
420 | * | |
421 | * Enables/disables pull up/down on a specified pin. This only takes effect if | |
422 | * the pin is configured as an input (either explicitly or by the alternate | |
423 | * function). | |
424 | * | |
425 | * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is | |
426 | * configured as an input. Otherwise, due to the way the controller registers | |
427 | * work, this function will change the value output on the pin. | |
428 | */ | |
429 | int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |
430 | { | |
431 | struct nmk_gpio_chip *nmk_chip; | |
432 | unsigned long flags; | |
433 | ||
6845664a | 434 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
5b327edf RV |
435 | if (!nmk_chip) |
436 | return -EINVAL; | |
437 | ||
438 | spin_lock_irqsave(&nmk_chip->lock, flags); | |
439 | __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); | |
440 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | |
441 | ||
442 | return 0; | |
443 | } | |
444 | ||
2ec1d359 | 445 | /* Mode functions */ |
9c66ee6f JA |
446 | /** |
447 | * nmk_gpio_set_mode() - set the mux mode of a gpio pin | |
448 | * @gpio: pin number | |
449 | * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, | |
450 | * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C | |
451 | * | |
452 | * Sets the mode of the specified pin to one of the alternate functions or | |
453 | * plain GPIO. | |
454 | */ | |
2ec1d359 AR |
455 | int nmk_gpio_set_mode(int gpio, int gpio_mode) |
456 | { | |
457 | struct nmk_gpio_chip *nmk_chip; | |
458 | unsigned long flags; | |
2ec1d359 | 459 | |
6845664a | 460 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
2ec1d359 AR |
461 | if (!nmk_chip) |
462 | return -EINVAL; | |
463 | ||
2ec1d359 | 464 | spin_lock_irqsave(&nmk_chip->lock, flags); |
6f9a974c | 465 | __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); |
2ec1d359 AR |
466 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
467 | ||
468 | return 0; | |
469 | } | |
470 | EXPORT_SYMBOL(nmk_gpio_set_mode); | |
471 | ||
472 | int nmk_gpio_get_mode(int gpio) | |
473 | { | |
474 | struct nmk_gpio_chip *nmk_chip; | |
475 | u32 afunc, bfunc, bit; | |
476 | ||
6845664a | 477 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); |
2ec1d359 AR |
478 | if (!nmk_chip) |
479 | return -EINVAL; | |
480 | ||
481 | bit = 1 << (gpio - nmk_chip->chip.base); | |
482 | ||
483 | afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; | |
484 | bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; | |
485 | ||
486 | return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); | |
487 | } | |
488 | EXPORT_SYMBOL(nmk_gpio_get_mode); | |
489 | ||
490 | ||
491 | /* IRQ functions */ | |
492 | static inline int nmk_gpio_get_bitmask(int gpio) | |
493 | { | |
494 | return 1 << (gpio % 32); | |
495 | } | |
496 | ||
f272c00e | 497 | static void nmk_gpio_irq_ack(struct irq_data *d) |
2ec1d359 AR |
498 | { |
499 | int gpio; | |
500 | struct nmk_gpio_chip *nmk_chip; | |
501 | ||
f272c00e LB |
502 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
503 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
504 | if (!nmk_chip) |
505 | return; | |
506 | writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); | |
507 | } | |
508 | ||
4d4e20f7 RV |
509 | enum nmk_gpio_irq_type { |
510 | NORMAL, | |
511 | WAKE, | |
512 | }; | |
513 | ||
040e5ecd | 514 | static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, |
4d4e20f7 RV |
515 | int gpio, enum nmk_gpio_irq_type which, |
516 | bool enable) | |
2ec1d359 | 517 | { |
4d4e20f7 RV |
518 | u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC; |
519 | u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC; | |
040e5ecd RV |
520 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
521 | u32 reg; | |
2ec1d359 | 522 | |
040e5ecd | 523 | /* we must individually set/clear the two edges */ |
2ec1d359 | 524 | if (nmk_chip->edge_rising & bitmask) { |
4d4e20f7 | 525 | reg = readl(nmk_chip->addr + rimsc); |
040e5ecd RV |
526 | if (enable) |
527 | reg |= bitmask; | |
528 | else | |
529 | reg &= ~bitmask; | |
4d4e20f7 | 530 | writel(reg, nmk_chip->addr + rimsc); |
2ec1d359 AR |
531 | } |
532 | if (nmk_chip->edge_falling & bitmask) { | |
4d4e20f7 | 533 | reg = readl(nmk_chip->addr + fimsc); |
040e5ecd RV |
534 | if (enable) |
535 | reg |= bitmask; | |
536 | else | |
537 | reg &= ~bitmask; | |
4d4e20f7 | 538 | writel(reg, nmk_chip->addr + fimsc); |
2ec1d359 | 539 | } |
040e5ecd | 540 | } |
2ec1d359 | 541 | |
b9df468d RV |
542 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
543 | int gpio, bool on) | |
544 | { | |
b9df468d RV |
545 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
546 | } | |
547 | ||
548 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |
2ec1d359 AR |
549 | { |
550 | int gpio; | |
551 | struct nmk_gpio_chip *nmk_chip; | |
552 | unsigned long flags; | |
040e5ecd | 553 | u32 bitmask; |
2ec1d359 | 554 | |
f272c00e LB |
555 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
556 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
557 | bitmask = nmk_gpio_get_bitmask(gpio); |
558 | if (!nmk_chip) | |
4d4e20f7 | 559 | return -EINVAL; |
2ec1d359 | 560 | |
d1118f68 TG |
561 | if (enable) |
562 | nmk_chip->enabled |= bitmask; | |
563 | else | |
564 | nmk_chip->enabled &= ~bitmask; | |
565 | ||
b9df468d RV |
566 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
567 | spin_lock(&nmk_chip->lock); | |
568 | ||
569 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable); | |
570 | ||
571 | if (!(nmk_chip->real_wake & bitmask)) | |
572 | __nmk_gpio_set_wake(nmk_chip, gpio, enable); | |
573 | ||
574 | spin_unlock(&nmk_chip->lock); | |
575 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
4d4e20f7 RV |
576 | |
577 | return 0; | |
2ec1d359 AR |
578 | } |
579 | ||
f272c00e | 580 | static void nmk_gpio_irq_mask(struct irq_data *d) |
040e5ecd | 581 | { |
b9df468d | 582 | nmk_gpio_irq_maskunmask(d, false); |
4d4e20f7 | 583 | } |
040e5ecd | 584 | |
f272c00e | 585 | static void nmk_gpio_irq_unmask(struct irq_data *d) |
040e5ecd | 586 | { |
b9df468d | 587 | nmk_gpio_irq_maskunmask(d, true); |
4d4e20f7 RV |
588 | } |
589 | ||
f272c00e | 590 | static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) |
4d4e20f7 | 591 | { |
7e3f7e59 RV |
592 | struct nmk_gpio_chip *nmk_chip; |
593 | unsigned long flags; | |
b9df468d | 594 | u32 bitmask; |
7e3f7e59 RV |
595 | int gpio; |
596 | ||
f272c00e LB |
597 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
598 | nmk_chip = irq_data_get_irq_chip_data(d); | |
7e3f7e59 RV |
599 | if (!nmk_chip) |
600 | return -EINVAL; | |
b9df468d | 601 | bitmask = nmk_gpio_get_bitmask(gpio); |
7e3f7e59 | 602 | |
01727e61 RV |
603 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
604 | spin_lock(&nmk_chip->lock); | |
605 | ||
d1118f68 | 606 | if (!(nmk_chip->enabled & bitmask)) |
b9df468d RV |
607 | __nmk_gpio_set_wake(nmk_chip, gpio, on); |
608 | ||
609 | if (on) | |
610 | nmk_chip->real_wake |= bitmask; | |
611 | else | |
612 | nmk_chip->real_wake &= ~bitmask; | |
01727e61 RV |
613 | |
614 | spin_unlock(&nmk_chip->lock); | |
615 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | |
7e3f7e59 RV |
616 | |
617 | return 0; | |
040e5ecd RV |
618 | } |
619 | ||
f272c00e | 620 | static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
2ec1d359 | 621 | { |
d1118f68 | 622 | bool enabled, wake = irqd_is_wakeup_set(d); |
2ec1d359 AR |
623 | int gpio; |
624 | struct nmk_gpio_chip *nmk_chip; | |
625 | unsigned long flags; | |
626 | u32 bitmask; | |
627 | ||
f272c00e LB |
628 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); |
629 | nmk_chip = irq_data_get_irq_chip_data(d); | |
2ec1d359 AR |
630 | bitmask = nmk_gpio_get_bitmask(gpio); |
631 | if (!nmk_chip) | |
632 | return -EINVAL; | |
633 | ||
634 | if (type & IRQ_TYPE_LEVEL_HIGH) | |
635 | return -EINVAL; | |
636 | if (type & IRQ_TYPE_LEVEL_LOW) | |
637 | return -EINVAL; | |
638 | ||
d1118f68 TG |
639 | enabled = nmk_chip->enabled & bitmask; |
640 | ||
2ec1d359 AR |
641 | spin_lock_irqsave(&nmk_chip->lock, flags); |
642 | ||
7a852d80 | 643 | if (enabled) |
4d4e20f7 RV |
644 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); |
645 | ||
b9df468d | 646 | if (enabled || wake) |
4d4e20f7 | 647 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); |
7a852d80 | 648 | |
2ec1d359 AR |
649 | nmk_chip->edge_rising &= ~bitmask; |
650 | if (type & IRQ_TYPE_EDGE_RISING) | |
651 | nmk_chip->edge_rising |= bitmask; | |
2ec1d359 AR |
652 | |
653 | nmk_chip->edge_falling &= ~bitmask; | |
654 | if (type & IRQ_TYPE_EDGE_FALLING) | |
655 | nmk_chip->edge_falling |= bitmask; | |
2ec1d359 | 656 | |
7a852d80 | 657 | if (enabled) |
4d4e20f7 RV |
658 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); |
659 | ||
b9df468d | 660 | if (enabled || wake) |
4d4e20f7 | 661 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); |
2ec1d359 | 662 | |
7a852d80 | 663 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
2ec1d359 AR |
664 | |
665 | return 0; | |
666 | } | |
667 | ||
668 | static struct irq_chip nmk_gpio_irq_chip = { | |
669 | .name = "Nomadik-GPIO", | |
f272c00e LB |
670 | .irq_ack = nmk_gpio_irq_ack, |
671 | .irq_mask = nmk_gpio_irq_mask, | |
672 | .irq_unmask = nmk_gpio_irq_unmask, | |
673 | .irq_set_type = nmk_gpio_irq_set_type, | |
674 | .irq_set_wake = nmk_gpio_irq_set_wake, | |
2ec1d359 AR |
675 | }; |
676 | ||
33b744b3 RV |
677 | static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, |
678 | u32 status) | |
2ec1d359 AR |
679 | { |
680 | struct nmk_gpio_chip *nmk_chip; | |
6845664a | 681 | struct irq_chip *host_chip = irq_get_chip(irq); |
2ec1d359 AR |
682 | unsigned int first_irq; |
683 | ||
f272c00e LB |
684 | if (host_chip->irq_mask_ack) |
685 | host_chip->irq_mask_ack(&desc->irq_data); | |
aaedaa2b | 686 | else { |
f272c00e LB |
687 | host_chip->irq_mask(&desc->irq_data); |
688 | if (host_chip->irq_ack) | |
689 | host_chip->irq_ack(&desc->irq_data); | |
aaedaa2b RV |
690 | } |
691 | ||
6845664a | 692 | nmk_chip = irq_get_handler_data(irq); |
2ec1d359 | 693 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); |
33b744b3 RV |
694 | while (status) { |
695 | int bit = __ffs(status); | |
696 | ||
697 | generic_handle_irq(first_irq + bit); | |
698 | status &= ~BIT(bit); | |
2ec1d359 | 699 | } |
aaedaa2b | 700 | |
f272c00e | 701 | host_chip->irq_unmask(&desc->irq_data); |
2ec1d359 AR |
702 | } |
703 | ||
33b744b3 RV |
704 | static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
705 | { | |
6845664a | 706 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
707 | u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); |
708 | ||
709 | __nmk_gpio_irq_handler(irq, desc, status); | |
710 | } | |
711 | ||
712 | static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |
713 | struct irq_desc *desc) | |
714 | { | |
6845664a | 715 | struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); |
33b744b3 RV |
716 | u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); |
717 | ||
718 | __nmk_gpio_irq_handler(irq, desc, status); | |
719 | } | |
720 | ||
2ec1d359 AR |
721 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
722 | { | |
723 | unsigned int first_irq; | |
724 | int i; | |
725 | ||
726 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | |
e493e06f | 727 | for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { |
6845664a TG |
728 | irq_set_chip(i, &nmk_gpio_irq_chip); |
729 | irq_set_handler(i, handle_edge_irq); | |
2ec1d359 | 730 | set_irq_flags(i, IRQF_VALID); |
6845664a TG |
731 | irq_set_chip_data(i, nmk_chip); |
732 | irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); | |
2ec1d359 | 733 | } |
33b744b3 | 734 | |
6845664a TG |
735 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
736 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | |
33b744b3 RV |
737 | |
738 | if (nmk_chip->secondary_parent_irq >= 0) { | |
6845664a | 739 | irq_set_chained_handler(nmk_chip->secondary_parent_irq, |
33b744b3 | 740 | nmk_gpio_secondary_irq_handler); |
6845664a | 741 | irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); |
33b744b3 RV |
742 | } |
743 | ||
2ec1d359 AR |
744 | return 0; |
745 | } | |
746 | ||
747 | /* I/O Functions */ | |
748 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) | |
749 | { | |
750 | struct nmk_gpio_chip *nmk_chip = | |
751 | container_of(chip, struct nmk_gpio_chip, chip); | |
752 | ||
753 | writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); | |
754 | return 0; | |
755 | } | |
756 | ||
2ec1d359 AR |
757 | static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) |
758 | { | |
759 | struct nmk_gpio_chip *nmk_chip = | |
760 | container_of(chip, struct nmk_gpio_chip, chip); | |
761 | u32 bit = 1 << offset; | |
762 | ||
763 | return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; | |
764 | } | |
765 | ||
766 | static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, | |
767 | int val) | |
768 | { | |
769 | struct nmk_gpio_chip *nmk_chip = | |
770 | container_of(chip, struct nmk_gpio_chip, chip); | |
2ec1d359 | 771 | |
6720db7c | 772 | __nmk_gpio_set_output(nmk_chip, offset, val); |
2ec1d359 AR |
773 | } |
774 | ||
6647c6c0 RV |
775 | static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, |
776 | int val) | |
777 | { | |
778 | struct nmk_gpio_chip *nmk_chip = | |
779 | container_of(chip, struct nmk_gpio_chip, chip); | |
780 | ||
6720db7c | 781 | __nmk_gpio_make_output(nmk_chip, offset, val); |
6647c6c0 RV |
782 | |
783 | return 0; | |
784 | } | |
785 | ||
0d2aec9c RV |
786 | static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
787 | { | |
788 | struct nmk_gpio_chip *nmk_chip = | |
789 | container_of(chip, struct nmk_gpio_chip, chip); | |
790 | ||
791 | return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; | |
792 | } | |
793 | ||
d0b543c7 RV |
794 | #ifdef CONFIG_DEBUG_FS |
795 | ||
796 | #include <linux/seq_file.h> | |
797 | ||
798 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |
799 | { | |
800 | int mode; | |
801 | unsigned i; | |
802 | unsigned gpio = chip->base; | |
803 | int is_out; | |
804 | struct nmk_gpio_chip *nmk_chip = | |
805 | container_of(chip, struct nmk_gpio_chip, chip); | |
806 | const char *modes[] = { | |
807 | [NMK_GPIO_ALT_GPIO] = "gpio", | |
808 | [NMK_GPIO_ALT_A] = "altA", | |
809 | [NMK_GPIO_ALT_B] = "altB", | |
810 | [NMK_GPIO_ALT_C] = "altC", | |
811 | }; | |
812 | ||
813 | for (i = 0; i < chip->ngpio; i++, gpio++) { | |
814 | const char *label = gpiochip_is_requested(chip, i); | |
815 | bool pull; | |
816 | u32 bit = 1 << i; | |
817 | ||
818 | if (!label) | |
819 | continue; | |
820 | ||
821 | is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; | |
822 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | |
823 | mode = nmk_gpio_get_mode(gpio); | |
824 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | |
825 | gpio, label, | |
826 | is_out ? "out" : "in ", | |
827 | chip->get | |
828 | ? (chip->get(chip, i) ? "hi" : "lo") | |
829 | : "? ", | |
830 | (mode < 0) ? "unknown" : modes[mode], | |
831 | pull ? "pull" : "none"); | |
d0b543c7 RV |
832 | seq_printf(s, "\n"); |
833 | } | |
834 | } | |
835 | ||
836 | #else | |
837 | #define nmk_gpio_dbg_show NULL | |
838 | #endif | |
839 | ||
2ec1d359 AR |
840 | /* This structure is replicated for each GPIO block allocated at probe time */ |
841 | static struct gpio_chip nmk_gpio_template = { | |
842 | .direction_input = nmk_gpio_make_input, | |
843 | .get = nmk_gpio_get_input, | |
844 | .direction_output = nmk_gpio_make_output, | |
845 | .set = nmk_gpio_set_output, | |
0d2aec9c | 846 | .to_irq = nmk_gpio_to_irq, |
d0b543c7 | 847 | .dbg_show = nmk_gpio_dbg_show, |
2ec1d359 AR |
848 | .can_sleep = 0, |
849 | }; | |
850 | ||
b9df468d RV |
851 | /* |
852 | * Called from the suspend/resume path to only keep the real wakeup interrupts | |
853 | * (those that have had set_irq_wake() called on them) as wakeup interrupts, | |
854 | * and not the rest of the interrupts which we needed to have as wakeups for | |
855 | * cpuidle. | |
856 | * | |
857 | * PM ops are not used since this needs to be done at the end, after all the | |
858 | * other drivers are done with their suspend callbacks. | |
859 | */ | |
860 | void nmk_gpio_wakeups_suspend(void) | |
861 | { | |
862 | int i; | |
863 | ||
864 | for (i = 0; i < NUM_BANKS; i++) { | |
865 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
866 | ||
867 | if (!chip) | |
868 | break; | |
869 | ||
870 | chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC); | |
871 | chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC); | |
872 | ||
873 | writel(chip->rwimsc & chip->real_wake, | |
874 | chip->addr + NMK_GPIO_RWIMSC); | |
875 | writel(chip->fwimsc & chip->real_wake, | |
876 | chip->addr + NMK_GPIO_FWIMSC); | |
877 | ||
878 | if (cpu_is_u8500v2()) { | |
879 | chip->slpm = readl(chip->addr + NMK_GPIO_SLPC); | |
880 | ||
881 | /* 0 -> wakeup enable */ | |
882 | writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC); | |
883 | } | |
884 | } | |
885 | } | |
886 | ||
887 | void nmk_gpio_wakeups_resume(void) | |
888 | { | |
889 | int i; | |
890 | ||
891 | for (i = 0; i < NUM_BANKS; i++) { | |
892 | struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; | |
893 | ||
894 | if (!chip) | |
895 | break; | |
896 | ||
897 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); | |
898 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | |
899 | ||
900 | if (cpu_is_u8500v2()) | |
901 | writel(chip->slpm, chip->addr + NMK_GPIO_SLPC); | |
902 | } | |
903 | } | |
904 | ||
fd0d67d6 | 905 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
2ec1d359 | 906 | { |
3e3c62ca | 907 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
2ec1d359 AR |
908 | struct nmk_gpio_chip *nmk_chip; |
909 | struct gpio_chip *chip; | |
3e3c62ca | 910 | struct resource *res; |
af7dc228 | 911 | struct clk *clk; |
33b744b3 | 912 | int secondary_irq; |
3e3c62ca | 913 | int irq; |
2ec1d359 AR |
914 | int ret; |
915 | ||
3e3c62ca RV |
916 | if (!pdata) |
917 | return -ENODEV; | |
918 | ||
919 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | |
920 | if (!res) { | |
921 | ret = -ENOENT; | |
922 | goto out; | |
923 | } | |
924 | ||
925 | irq = platform_get_irq(dev, 0); | |
926 | if (irq < 0) { | |
927 | ret = irq; | |
928 | goto out; | |
929 | } | |
930 | ||
33b744b3 RV |
931 | secondary_irq = platform_get_irq(dev, 1); |
932 | if (secondary_irq >= 0 && !pdata->get_secondary_status) { | |
933 | ret = -EINVAL; | |
934 | goto out; | |
935 | } | |
936 | ||
3e3c62ca RV |
937 | if (request_mem_region(res->start, resource_size(res), |
938 | dev_name(&dev->dev)) == NULL) { | |
939 | ret = -EBUSY; | |
940 | goto out; | |
941 | } | |
2ec1d359 | 942 | |
af7dc228 RV |
943 | clk = clk_get(&dev->dev, NULL); |
944 | if (IS_ERR(clk)) { | |
945 | ret = PTR_ERR(clk); | |
946 | goto out_release; | |
947 | } | |
948 | ||
949 | clk_enable(clk); | |
950 | ||
2ec1d359 AR |
951 | nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); |
952 | if (!nmk_chip) { | |
953 | ret = -ENOMEM; | |
af7dc228 | 954 | goto out_clk; |
2ec1d359 AR |
955 | } |
956 | /* | |
957 | * The virt address in nmk_chip->addr is in the nomadik register space, | |
958 | * so we can simply convert the resource address, without remapping | |
959 | */ | |
33b744b3 | 960 | nmk_chip->bank = dev->id; |
af7dc228 | 961 | nmk_chip->clk = clk; |
3e3c62ca | 962 | nmk_chip->addr = io_p2v(res->start); |
2ec1d359 | 963 | nmk_chip->chip = nmk_gpio_template; |
3e3c62ca | 964 | nmk_chip->parent_irq = irq; |
33b744b3 RV |
965 | nmk_chip->secondary_parent_irq = secondary_irq; |
966 | nmk_chip->get_secondary_status = pdata->get_secondary_status; | |
01727e61 | 967 | nmk_chip->set_ioforce = pdata->set_ioforce; |
c0fcb8db | 968 | spin_lock_init(&nmk_chip->lock); |
2ec1d359 AR |
969 | |
970 | chip = &nmk_chip->chip; | |
971 | chip->base = pdata->first_gpio; | |
e493e06f | 972 | chip->ngpio = pdata->num_gpio; |
8d568ae5 | 973 | chip->label = pdata->name ?: dev_name(&dev->dev); |
2ec1d359 AR |
974 | chip->dev = &dev->dev; |
975 | chip->owner = THIS_MODULE; | |
976 | ||
977 | ret = gpiochip_add(&nmk_chip->chip); | |
978 | if (ret) | |
979 | goto out_free; | |
980 | ||
01727e61 RV |
981 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
982 | ||
983 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | |
3e3c62ca | 984 | platform_set_drvdata(dev, nmk_chip); |
2ec1d359 AR |
985 | |
986 | nmk_gpio_init_irq(nmk_chip); | |
987 | ||
988 | dev_info(&dev->dev, "Bits %i-%i at address %p\n", | |
989 | nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr); | |
990 | return 0; | |
991 | ||
3e3c62ca | 992 | out_free: |
2ec1d359 | 993 | kfree(nmk_chip); |
af7dc228 RV |
994 | out_clk: |
995 | clk_disable(clk); | |
996 | clk_put(clk); | |
3e3c62ca RV |
997 | out_release: |
998 | release_mem_region(res->start, resource_size(res)); | |
999 | out: | |
2ec1d359 AR |
1000 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
1001 | pdata->first_gpio, pdata->first_gpio+31); | |
1002 | return ret; | |
1003 | } | |
1004 | ||
3e3c62ca RV |
1005 | static struct platform_driver nmk_gpio_driver = { |
1006 | .driver = { | |
2ec1d359 AR |
1007 | .owner = THIS_MODULE, |
1008 | .name = "gpio", | |
5317e4d1 | 1009 | }, |
2ec1d359 | 1010 | .probe = nmk_gpio_probe, |
2ec1d359 AR |
1011 | }; |
1012 | ||
1013 | static int __init nmk_gpio_init(void) | |
1014 | { | |
3e3c62ca | 1015 | return platform_driver_register(&nmk_gpio_driver); |
2ec1d359 AR |
1016 | } |
1017 | ||
33f45ea9 | 1018 | core_initcall(nmk_gpio_init); |
2ec1d359 AR |
1019 | |
1020 | MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); | |
1021 | MODULE_DESCRIPTION("Nomadik GPIO Driver"); | |
1022 | MODULE_LICENSE("GPL"); | |
1023 | ||
1024 |