[mirror_ubuntu-bionic-kernel.git] / arch / arm / plat-nomadik / include / plat / ste_dma40.h

/*
 * Copyright (C) ST-Ericsson SA 2007-2010
 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
 * License terms: GNU General Public License (GPL) version 2
 */


#ifndef STE_DMA40_H
#define STE_DMA40_H

#include <linux/dmaengine.h>
#include <linux/workqueue.h>
#include <linux/interrupt.h>
#include <linux/dmaengine.h>

/* dev types for memcpy */
#define STEDMA40_DEV_DST_MEMORY (-1)
#define	STEDMA40_DEV_SRC_MEMORY (-1)

/*
 * Description of bitfields of channel_type variable is available in
 * the info structure.
 */

/* Priority */
#define STEDMA40_INFO_PRIO_TYPE_POS 2
#define STEDMA40_HIGH_PRIORITY_CHANNEL (0x1 << STEDMA40_INFO_PRIO_TYPE_POS)
#define STEDMA40_LOW_PRIORITY_CHANNEL (0x2 << STEDMA40_INFO_PRIO_TYPE_POS)

/* Mode  */
#define STEDMA40_INFO_CH_MODE_TYPE_POS 6
#define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS)
#define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS)
#define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS)

/* Mode options */
#define STEDMA40_INFO_CH_MODE_OPT_POS 8
#define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
#define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
#define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)
#define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
#define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
#define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)

/* Interrupt */
#define STEDMA40_INFO_TIM_POS 10
#define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS)
#define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS)

/* End of channel_type configuration */

#define STEDMA40_ESIZE_8_BIT  0x0
#define STEDMA40_ESIZE_16_BIT 0x1
#define STEDMA40_ESIZE_32_BIT 0x2
#define STEDMA40_ESIZE_64_BIT 0x3

/* The value 4 indicates that PEN-reg shall be set to 0 */
#define STEDMA40_PSIZE_PHY_1  0x4
#define STEDMA40_PSIZE_PHY_2  0x0
#define STEDMA40_PSIZE_PHY_4  0x1
#define STEDMA40_PSIZE_PHY_8  0x2
#define STEDMA40_PSIZE_PHY_16 0x3

/*
 * The number of elements differ in logical and
 * physical mode
 */
#define STEDMA40_PSIZE_LOG_1  STEDMA40_PSIZE_PHY_2
#define STEDMA40_PSIZE_LOG_4  STEDMA40_PSIZE_PHY_4
#define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8
#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16

/* Maximum number of possible physical channels */
#define STEDMA40_MAX_PHYS 32

enum stedma40_flow_ctrl {
	STEDMA40_NO_FLOW_CTRL,
	STEDMA40_FLOW_CTRL,
};

enum stedma40_endianess {
	STEDMA40_LITTLE_ENDIAN,
	STEDMA40_BIG_ENDIAN
};

enum stedma40_periph_data_width {
	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
};

enum stedma40_xfer_dir {
	STEDMA40_MEM_TO_MEM = 1,
	STEDMA40_MEM_TO_PERIPH,
	STEDMA40_PERIPH_TO_MEM,
	STEDMA40_PERIPH_TO_PERIPH
};


/**
 * struct stedma40_chan_cfg - dst/src channel configuration
 *
 * @endianess: Endianess of the src/dst hardware
 * @data_width: Data width of the src/dst hardware
 * @p_size: Burst size
 * @flow_ctrl: Flow control on/off.
 */
struct stedma40_half_channel_info {
	enum stedma40_endianess endianess;
	enum stedma40_periph_data_width data_width;
	int psize;
	enum stedma40_flow_ctrl flow_ctrl;
};

/**
 * struct stedma40_chan_cfg - Structure to be filled by client drivers.
 *
 * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
 * @channel_type: priority, mode, mode options and interrupt configuration.
 * @src_dev_type: Src device type
 * @dst_dev_type: Dst device type
 * @src_info: Parameters for dst half channel
 * @dst_info: Parameters for dst half channel
 *
 *
 * This structure has to be filled by the client drivers.
 * It is recommended to do all dma configurations for clients in the machine.
 *
 */
struct stedma40_chan_cfg {
	enum stedma40_xfer_dir			 dir;
	unsigned int				 channel_type;
	int					 src_dev_type;
	int					 dst_dev_type;
	struct stedma40_half_channel_info	 src_info;
	struct stedma40_half_channel_info	 dst_info;
};

/**
 * struct stedma40_platform_data - Configuration struct for the dma device.
 *
 * @dev_len: length of dev_tx and dev_rx
 * @dev_tx: mapping between destination event line and io address
 * @dev_rx: mapping between source event line and io address
 * @memcpy: list of memcpy event lines
 * @memcpy_len: length of memcpy
 * @memcpy_conf_phy: default configuration of physical channel memcpy
 * @memcpy_conf_log: default configuration of logical channel memcpy
 * @disabled_channels: A vector, ending with -1, that marks physical channels
 * that are for different reasons not available for the driver.
 */
struct stedma40_platform_data {
	u32				 dev_len;
	const dma_addr_t		*dev_tx;
	const dma_addr_t		*dev_rx;
	int				*memcpy;
	u32				 memcpy_len;
	struct stedma40_chan_cfg	*memcpy_conf_phy;
	struct stedma40_chan_cfg	*memcpy_conf_log;
	int				 disabled_channels[STEDMA40_MAX_PHYS];
};

/**
 * stedma40_filter() - Provides stedma40_chan_cfg to the
 * ste_dma40 dma driver via the dmaengine framework.
 * does some checking of what's provided.
 *
 * Never directly called by client. It used by dmaengine.
 * @chan: dmaengine handle.
 * @data: Must be of type: struct stedma40_chan_cfg and is
 * the configuration of the framework.
 *
 *
 */

bool stedma40_filter(struct dma_chan *chan, void *data);

/**
 * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
 * scattergatter lists.
 *
 * @chan: dmaengine handle
 * @sgl_dst: Destination scatter list
 * @sgl_src: Source scatter list
 * @sgl_len: The length of each scatterlist. Both lists must be of equal length
 * and each element must match the corresponding element in the other scatter
 * list.
 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
 */

struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan,
						   struct scatterlist *sgl_dst,
						   struct scatterlist *sgl_src,
						   unsigned int sgl_len,
						   unsigned long flags);

/**
 * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
 * (=device)
 *
 * @chan: dmaengine handle
 * @addr: source or destination physicall address.
 * @size: bytes to transfer
 * @direction: direction of transfer
 * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
 */

static inline struct
dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
					    dma_addr_t addr,
					    unsigned int size,
					    enum dma_data_direction direction,
					    unsigned long flags)
{
	struct scatterlist sg;
	sg_init_table(&sg, 1);
	sg.dma_address = addr;
	sg.length = size;

	return chan->device->device_prep_slave_sg(chan, &sg, 1,
						  direction, flags);
}

#endif
Commit	Line	Data
8d318a50	1	/*
767a9675	2	* Copyright (C) ST-Ericsson SA 2007-2010
661385f9	3	* Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
767a9675	4	* Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
8d318a50	5	* License terms: GNU General Public License (GPL) version 2
8d318a50 LW	6	*/
	7
	8
	9	#ifndef STE_DMA40_H
	10	#define STE_DMA40_H
	11
	12	#include <linux/dmaengine.h>
	13	#include <linux/workqueue.h>
	14	#include <linux/interrupt.h>
	15	#include <linux/dmaengine.h>
	16
	17	/* dev types for memcpy */
	18	#define STEDMA40_DEV_DST_MEMORY (-1)
	19	#define STEDMA40_DEV_SRC_MEMORY (-1)
	20
	21	/*
	22	* Description of bitfields of channel_type variable is available in
	23	* the info structure.
	24	*/
	25
	26	/* Priority */
	27	#define STEDMA40_INFO_PRIO_TYPE_POS 2
	28	#define STEDMA40_HIGH_PRIORITY_CHANNEL (0x1 << STEDMA40_INFO_PRIO_TYPE_POS)
	29	#define STEDMA40_LOW_PRIORITY_CHANNEL (0x2 << STEDMA40_INFO_PRIO_TYPE_POS)
	30
	31	/* Mode */
	32	#define STEDMA40_INFO_CH_MODE_TYPE_POS 6
	33	#define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS)
	34	#define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS)
	35	#define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS)
	36
	37	/* Mode options */
	38	#define STEDMA40_INFO_CH_MODE_OPT_POS 8
	39	#define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
	40	#define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
	41	#define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)
	42	#define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS)
	43	#define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS)
	44	#define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS)
	45
	46	/* Interrupt */
	47	#define STEDMA40_INFO_TIM_POS 10
	48	#define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS)
	49	#define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS)
	50
	51	/* End of channel_type configuration */
	52
	53	#define STEDMA40_ESIZE_8_BIT 0x0
	54	#define STEDMA40_ESIZE_16_BIT 0x1
	55	#define STEDMA40_ESIZE_32_BIT 0x2
	56	#define STEDMA40_ESIZE_64_BIT 0x3
	57
	58	/* The value 4 indicates that PEN-reg shall be set to 0 */
	59	#define STEDMA40_PSIZE_PHY_1 0x4
	60	#define STEDMA40_PSIZE_PHY_2 0x0
	61	#define STEDMA40_PSIZE_PHY_4 0x1
	62	#define STEDMA40_PSIZE_PHY_8 0x2
	63	#define STEDMA40_PSIZE_PHY_16 0x3
	64
	65	/*
	66	* The number of elements differ in logical and
	67	* physical mode
	68	*/
	69	#define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2
70	#define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4
71	#define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8
72	#define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
73
767a9675 JA	74	/* Maximum number of possible physical channels */
	75	#define STEDMA40_MAX_PHYS 32
	76
8d318a50 LW	77	enum stedma40_flow_ctrl {
	78	STEDMA40_NO_FLOW_CTRL,
	79	STEDMA40_FLOW_CTRL,
	80	};
	81
	82	enum stedma40_endianess {
	83	STEDMA40_LITTLE_ENDIAN,
	84	STEDMA40_BIG_ENDIAN
	85	};
	86
	87	enum stedma40_periph_data_width {
	88	STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT,
	89	STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT,
	90	STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT,
	91	STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT
	92	};
	93
8d318a50	94	enum stedma40_xfer_dir {
0747c7ba	95	STEDMA40_MEM_TO_MEM = 1,
8d318a50 LW	96	STEDMA40_MEM_TO_PERIPH,
	97	STEDMA40_PERIPH_TO_MEM,
	98	STEDMA40_PERIPH_TO_PERIPH
	99	};
	100
	101
3c0f2401 JA	102	/**
	103	* struct stedma40_chan_cfg - dst/src channel configuration
	104	*
	105	* @endianess: Endianess of the src/dst hardware
	106	* @data_width: Data width of the src/dst hardware
	107	* @p_size: Burst size
	108	* @flow_ctrl: Flow control on/off.
	109	*/
	110	struct stedma40_half_channel_info {
	111	enum stedma40_endianess endianess;
	112	enum stedma40_periph_data_width data_width;
	113	int psize;
	114	enum stedma40_flow_ctrl flow_ctrl;
	115	};
	116
8d318a50 LW	117	/**
	118	* struct stedma40_chan_cfg - Structure to be filled by client drivers.
	119	*
	120	* @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
	121	* @channel_type: priority, mode, mode options and interrupt configuration.
	122	* @src_dev_type: Src device type
	123	* @dst_dev_type: Dst device type
	124	* @src_info: Parameters for dst half channel
	125	* @dst_info: Parameters for dst half channel
8d318a50 LW	126	*
	127	*
	128	* This structure has to be filled by the client drivers.
	129	* It is recommended to do all dma configurations for clients in the machine.
	130	*
	131	*/
	132	struct stedma40_chan_cfg {
	133	enum stedma40_xfer_dir dir;
	134	unsigned int channel_type;
	135	int src_dev_type;
	136	int dst_dev_type;
	137	struct stedma40_half_channel_info src_info;
	138	struct stedma40_half_channel_info dst_info;
8d318a50 LW	139	};
	140
	141	/**
	142	* struct stedma40_platform_data - Configuration struct for the dma device.
	143	*
	144	* @dev_len: length of dev_tx and dev_rx
	145	* @dev_tx: mapping between destination event line and io address
	146	* @dev_rx: mapping between source event line and io address
	147	* @memcpy: list of memcpy event lines
	148	* @memcpy_len: length of memcpy
	149	* @memcpy_conf_phy: default configuration of physical channel memcpy
	150	* @memcpy_conf_log: default configuration of logical channel memcpy
59516725 JA	151	* @disabled_channels: A vector, ending with -1, that marks physical channels
59516725 JA	152	* that are for different reasons not available for the driver.
8d318a50 LW	153	*/
	154	struct stedma40_platform_data {
	155	u32 dev_len;
	156	const dma_addr_t *dev_tx;
	157	const dma_addr_t *dev_rx;
	158	int *memcpy;
	159	u32 memcpy_len;
	160	struct stedma40_chan_cfg *memcpy_conf_phy;
	161	struct stedma40_chan_cfg *memcpy_conf_log;
767a9675	162	int disabled_channels[STEDMA40_MAX_PHYS];
8d318a50 LW	163	};
8d318a50 LW	164
8d318a50 LW	165	/**
	166	* stedma40_filter() - Provides stedma40_chan_cfg to the
	167	* ste_dma40 dma driver via the dmaengine framework.
	168	* does some checking of what's provided.
	169	*
	170	* Never directly called by client. It used by dmaengine.
	171	* @chan: dmaengine handle.
	172	* @data: Must be of type: struct stedma40_chan_cfg and is
	173	* the configuration of the framework.
	174	*
	175	*
	176	*/
	177
	178	bool stedma40_filter(struct dma_chan chan, void data);
	179
	180	/**
	181	* stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from
	182	* scattergatter lists.
	183	*
	184	* @chan: dmaengine handle
	185	* @sgl_dst: Destination scatter list
	186	* @sgl_src: Source scatter list
	187	* @sgl_len: The length of each scatterlist. Both lists must be of equal length
	188	* and each element must match the corresponding element in the other scatter
	189	* list.
	190	* @flags: is actually enum dma_ctrl_flags. See dmaengine.h
	191	*/
	192
	193	struct dma_async_tx_descriptor stedma40_memcpy_sg(struct dma_chan chan,
	194	struct scatterlist *sgl_dst,
	195	struct scatterlist *sgl_src,
	196	unsigned int sgl_len,
	197	unsigned long flags);
	198
	199	/**
	200	* stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
	201	* (=device)
	202	*
	203	* @chan: dmaengine handle
	204	* @addr: source or destination physicall address.
	205	* @size: bytes to transfer
	206	* @direction: direction of transfer
	207	* @flags: is actually enum dma_ctrl_flags. See dmaengine.h
	208	*/
	209
	210	static inline struct
	211	dma_async_tx_descriptor stedma40_slave_mem(struct dma_chan chan,
	212	dma_addr_t addr,
	213	unsigned int size,
	214	enum dma_data_direction direction,
	215	unsigned long flags)
	216	{
	217	struct scatterlist sg;
	218	sg_init_table(&sg, 1);
	219	sg.dma_address = addr;
	220	sg.length = size;
	221
	222	return chan->device->device_prep_slave_sg(chan, &sg, 1,
	223	direction, flags);
	224	}
	225
	226	#endif