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8d318a50 | 1 | /* |
767a9675 | 2 | * Copyright (C) ST-Ericsson SA 2007-2010 |
661385f9 | 3 | * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson |
767a9675 | 4 | * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson |
8d318a50 | 5 | * License terms: GNU General Public License (GPL) version 2 |
8d318a50 LW |
6 | */ |
7 | ||
8 | ||
9 | #ifndef STE_DMA40_H | |
10 | #define STE_DMA40_H | |
11 | ||
12 | #include <linux/dmaengine.h> | |
13 | #include <linux/workqueue.h> | |
14 | #include <linux/interrupt.h> | |
15 | #include <linux/dmaengine.h> | |
16 | ||
17 | /* dev types for memcpy */ | |
18 | #define STEDMA40_DEV_DST_MEMORY (-1) | |
19 | #define STEDMA40_DEV_SRC_MEMORY (-1) | |
20 | ||
21 | /* | |
22 | * Description of bitfields of channel_type variable is available in | |
23 | * the info structure. | |
24 | */ | |
25 | ||
8d318a50 LW |
26 | /* Mode */ |
27 | #define STEDMA40_INFO_CH_MODE_TYPE_POS 6 | |
28 | #define STEDMA40_CHANNEL_IN_PHY_MODE (0x1 << STEDMA40_INFO_CH_MODE_TYPE_POS) | |
29 | #define STEDMA40_CHANNEL_IN_LOG_MODE (0x2 << STEDMA40_INFO_CH_MODE_TYPE_POS) | |
30 | #define STEDMA40_CHANNEL_IN_OPER_MODE (0x3 << STEDMA40_INFO_CH_MODE_TYPE_POS) | |
31 | ||
32 | /* Mode options */ | |
33 | #define STEDMA40_INFO_CH_MODE_OPT_POS 8 | |
34 | #define STEDMA40_PCHAN_BASIC_MODE (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS) | |
35 | #define STEDMA40_PCHAN_MODULO_MODE (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS) | |
36 | #define STEDMA40_PCHAN_DOUBLE_DST_MODE (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS) | |
37 | #define STEDMA40_LCHAN_SRC_PHY_DST_LOG (0x1 << STEDMA40_INFO_CH_MODE_OPT_POS) | |
38 | #define STEDMA40_LCHAN_SRC_LOG_DST_PHS (0x2 << STEDMA40_INFO_CH_MODE_OPT_POS) | |
39 | #define STEDMA40_LCHAN_SRC_LOG_DST_LOG (0x3 << STEDMA40_INFO_CH_MODE_OPT_POS) | |
40 | ||
41 | /* Interrupt */ | |
42 | #define STEDMA40_INFO_TIM_POS 10 | |
43 | #define STEDMA40_NO_TIM_FOR_LINK (0x0 << STEDMA40_INFO_TIM_POS) | |
44 | #define STEDMA40_TIM_FOR_LINK (0x1 << STEDMA40_INFO_TIM_POS) | |
45 | ||
46 | /* End of channel_type configuration */ | |
47 | ||
48 | #define STEDMA40_ESIZE_8_BIT 0x0 | |
49 | #define STEDMA40_ESIZE_16_BIT 0x1 | |
50 | #define STEDMA40_ESIZE_32_BIT 0x2 | |
51 | #define STEDMA40_ESIZE_64_BIT 0x3 | |
52 | ||
53 | /* The value 4 indicates that PEN-reg shall be set to 0 */ | |
54 | #define STEDMA40_PSIZE_PHY_1 0x4 | |
55 | #define STEDMA40_PSIZE_PHY_2 0x0 | |
56 | #define STEDMA40_PSIZE_PHY_4 0x1 | |
57 | #define STEDMA40_PSIZE_PHY_8 0x2 | |
58 | #define STEDMA40_PSIZE_PHY_16 0x3 | |
59 | ||
60 | /* | |
61 | * The number of elements differ in logical and | |
62 | * physical mode | |
63 | */ | |
64 | #define STEDMA40_PSIZE_LOG_1 STEDMA40_PSIZE_PHY_2 | |
65 | #define STEDMA40_PSIZE_LOG_4 STEDMA40_PSIZE_PHY_4 | |
66 | #define STEDMA40_PSIZE_LOG_8 STEDMA40_PSIZE_PHY_8 | |
67 | #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16 | |
68 | ||
767a9675 JA |
69 | /* Maximum number of possible physical channels */ |
70 | #define STEDMA40_MAX_PHYS 32 | |
71 | ||
8d318a50 LW |
72 | enum stedma40_flow_ctrl { |
73 | STEDMA40_NO_FLOW_CTRL, | |
74 | STEDMA40_FLOW_CTRL, | |
75 | }; | |
76 | ||
77 | enum stedma40_endianess { | |
78 | STEDMA40_LITTLE_ENDIAN, | |
79 | STEDMA40_BIG_ENDIAN | |
80 | }; | |
81 | ||
82 | enum stedma40_periph_data_width { | |
83 | STEDMA40_BYTE_WIDTH = STEDMA40_ESIZE_8_BIT, | |
84 | STEDMA40_HALFWORD_WIDTH = STEDMA40_ESIZE_16_BIT, | |
85 | STEDMA40_WORD_WIDTH = STEDMA40_ESIZE_32_BIT, | |
86 | STEDMA40_DOUBLEWORD_WIDTH = STEDMA40_ESIZE_64_BIT | |
87 | }; | |
88 | ||
8d318a50 | 89 | enum stedma40_xfer_dir { |
0747c7ba | 90 | STEDMA40_MEM_TO_MEM = 1, |
8d318a50 LW |
91 | STEDMA40_MEM_TO_PERIPH, |
92 | STEDMA40_PERIPH_TO_MEM, | |
93 | STEDMA40_PERIPH_TO_PERIPH | |
94 | }; | |
95 | ||
96 | ||
3c0f2401 JA |
97 | /** |
98 | * struct stedma40_chan_cfg - dst/src channel configuration | |
99 | * | |
100 | * @endianess: Endianess of the src/dst hardware | |
101 | * @data_width: Data width of the src/dst hardware | |
102 | * @p_size: Burst size | |
103 | * @flow_ctrl: Flow control on/off. | |
104 | */ | |
105 | struct stedma40_half_channel_info { | |
106 | enum stedma40_endianess endianess; | |
107 | enum stedma40_periph_data_width data_width; | |
108 | int psize; | |
109 | enum stedma40_flow_ctrl flow_ctrl; | |
110 | }; | |
111 | ||
8d318a50 LW |
112 | /** |
113 | * struct stedma40_chan_cfg - Structure to be filled by client drivers. | |
114 | * | |
115 | * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH | |
116 | * @channel_type: priority, mode, mode options and interrupt configuration. | |
730c1871 | 117 | * @high_priority: true if high-priority |
8d318a50 LW |
118 | * @src_dev_type: Src device type |
119 | * @dst_dev_type: Dst device type | |
120 | * @src_info: Parameters for dst half channel | |
121 | * @dst_info: Parameters for dst half channel | |
8d318a50 LW |
122 | * |
123 | * | |
124 | * This structure has to be filled by the client drivers. | |
125 | * It is recommended to do all dma configurations for clients in the machine. | |
126 | * | |
127 | */ | |
128 | struct stedma40_chan_cfg { | |
129 | enum stedma40_xfer_dir dir; | |
130 | unsigned int channel_type; | |
730c1871 | 131 | bool high_priority; |
8d318a50 LW |
132 | int src_dev_type; |
133 | int dst_dev_type; | |
134 | struct stedma40_half_channel_info src_info; | |
135 | struct stedma40_half_channel_info dst_info; | |
8d318a50 LW |
136 | }; |
137 | ||
138 | /** | |
139 | * struct stedma40_platform_data - Configuration struct for the dma device. | |
140 | * | |
141 | * @dev_len: length of dev_tx and dev_rx | |
142 | * @dev_tx: mapping between destination event line and io address | |
143 | * @dev_rx: mapping between source event line and io address | |
144 | * @memcpy: list of memcpy event lines | |
145 | * @memcpy_len: length of memcpy | |
146 | * @memcpy_conf_phy: default configuration of physical channel memcpy | |
147 | * @memcpy_conf_log: default configuration of logical channel memcpy | |
59516725 JA |
148 | * @disabled_channels: A vector, ending with -1, that marks physical channels |
149 | * that are for different reasons not available for the driver. | |
8d318a50 LW |
150 | */ |
151 | struct stedma40_platform_data { | |
152 | u32 dev_len; | |
153 | const dma_addr_t *dev_tx; | |
154 | const dma_addr_t *dev_rx; | |
155 | int *memcpy; | |
156 | u32 memcpy_len; | |
157 | struct stedma40_chan_cfg *memcpy_conf_phy; | |
158 | struct stedma40_chan_cfg *memcpy_conf_log; | |
767a9675 | 159 | int disabled_channels[STEDMA40_MAX_PHYS]; |
8d318a50 LW |
160 | }; |
161 | ||
9646b798 LW |
162 | #ifdef CONFIG_STE_DMA40 |
163 | ||
8d318a50 LW |
164 | /** |
165 | * stedma40_filter() - Provides stedma40_chan_cfg to the | |
166 | * ste_dma40 dma driver via the dmaengine framework. | |
167 | * does some checking of what's provided. | |
168 | * | |
169 | * Never directly called by client. It used by dmaengine. | |
170 | * @chan: dmaengine handle. | |
171 | * @data: Must be of type: struct stedma40_chan_cfg and is | |
172 | * the configuration of the framework. | |
173 | * | |
174 | * | |
175 | */ | |
176 | ||
177 | bool stedma40_filter(struct dma_chan *chan, void *data); | |
178 | ||
179 | /** | |
180 | * stedma40_memcpy_sg() - extension of the dma framework, memcpy to/from | |
181 | * scattergatter lists. | |
182 | * | |
183 | * @chan: dmaengine handle | |
184 | * @sgl_dst: Destination scatter list | |
185 | * @sgl_src: Source scatter list | |
186 | * @sgl_len: The length of each scatterlist. Both lists must be of equal length | |
187 | * and each element must match the corresponding element in the other scatter | |
188 | * list. | |
189 | * @flags: is actually enum dma_ctrl_flags. See dmaengine.h | |
190 | */ | |
191 | ||
192 | struct dma_async_tx_descriptor *stedma40_memcpy_sg(struct dma_chan *chan, | |
193 | struct scatterlist *sgl_dst, | |
194 | struct scatterlist *sgl_src, | |
195 | unsigned int sgl_len, | |
196 | unsigned long flags); | |
197 | ||
198 | /** | |
199 | * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave | |
200 | * (=device) | |
201 | * | |
202 | * @chan: dmaengine handle | |
203 | * @addr: source or destination physicall address. | |
204 | * @size: bytes to transfer | |
205 | * @direction: direction of transfer | |
206 | * @flags: is actually enum dma_ctrl_flags. See dmaengine.h | |
207 | */ | |
208 | ||
209 | static inline struct | |
210 | dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, | |
211 | dma_addr_t addr, | |
212 | unsigned int size, | |
213 | enum dma_data_direction direction, | |
214 | unsigned long flags) | |
215 | { | |
216 | struct scatterlist sg; | |
217 | sg_init_table(&sg, 1); | |
218 | sg.dma_address = addr; | |
219 | sg.length = size; | |
220 | ||
221 | return chan->device->device_prep_slave_sg(chan, &sg, 1, | |
222 | direction, flags); | |
223 | } | |
224 | ||
9646b798 LW |
225 | #else |
226 | static inline bool stedma40_filter(struct dma_chan *chan, void *data) | |
227 | { | |
228 | return false; | |
229 | } | |
230 | ||
231 | static inline struct | |
232 | dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan, | |
233 | dma_addr_t addr, | |
234 | unsigned int size, | |
235 | enum dma_data_direction direction, | |
236 | unsigned long flags) | |
237 | { | |
238 | return NULL; | |
239 | } | |
240 | #endif | |
241 | ||
8d318a50 | 242 | #endif |