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28ad94ec | 1 | /* |
a0719f52 | 2 | * linux/arch/arm/plat-nomadik/timer.c |
28ad94ec AR |
3 | * |
4 | * Copyright (C) 2008 STMicroelectronics | |
b102c01f | 5 | * Copyright (C) 2010 Alessandro Rubini |
8fbb97a2 | 6 | * Copyright (C) 2010 Linus Walleij for ST-Ericsson |
28ad94ec AR |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2, as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/clockchips.h> | |
ba327b1e | 17 | #include <linux/clk.h> |
28ad94ec | 18 | #include <linux/jiffies.h> |
ba327b1e | 19 | #include <linux/err.h> |
28ad94ec | 20 | #include <asm/mach/time.h> |
ec05aa13 | 21 | #include <asm/sched_clock.h> |
28ad94ec | 22 | |
05387a9f JA |
23 | /* |
24 | * The MTU device hosts four different counters, with 4 set of | |
25 | * registers. These are register names. | |
26 | */ | |
27 | ||
28 | #define MTU_IMSC 0x00 /* Interrupt mask set/clear */ | |
29 | #define MTU_RIS 0x04 /* Raw interrupt status */ | |
30 | #define MTU_MIS 0x08 /* Masked interrupt status */ | |
31 | #define MTU_ICR 0x0C /* Interrupt clear register */ | |
32 | ||
33 | /* per-timer registers take 0..3 as argument */ | |
34 | #define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */ | |
35 | #define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */ | |
36 | #define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */ | |
37 | #define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */ | |
38 | ||
39 | /* bits for the control register */ | |
40 | #define MTU_CRn_ENA 0x80 | |
41 | #define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */ | |
42 | #define MTU_CRn_PRESCALE_MASK 0x0c | |
43 | #define MTU_CRn_PRESCALE_1 0x00 | |
44 | #define MTU_CRn_PRESCALE_16 0x04 | |
45 | #define MTU_CRn_PRESCALE_256 0x08 | |
46 | #define MTU_CRn_32BITS 0x02 | |
47 | #define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/ | |
48 | ||
49 | /* Other registers are usual amba/primecell registers, currently not used */ | |
50 | #define MTU_ITCR 0xff0 | |
51 | #define MTU_ITOP 0xff4 | |
52 | ||
53 | #define MTU_PERIPH_ID0 0xfe0 | |
54 | #define MTU_PERIPH_ID1 0xfe4 | |
55 | #define MTU_PERIPH_ID2 0xfe8 | |
56 | #define MTU_PERIPH_ID3 0xfeC | |
57 | ||
58 | #define MTU_PCELL0 0xff0 | |
59 | #define MTU_PCELL1 0xff4 | |
60 | #define MTU_PCELL2 0xff8 | |
61 | #define MTU_PCELL3 0xffC | |
28ad94ec | 62 | |
b9576623 | 63 | static void __iomem *mtu_base; |
2f73a068 JA |
64 | static bool clkevt_periodic; |
65 | static u32 clk_prescale; | |
66 | static u32 nmdk_cycle; /* write-once */ | |
67 | ||
cba13830 | 68 | #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK |
2a847513 LW |
69 | /* |
70 | * Override the global weak sched_clock symbol with this | |
71 | * local implementation which uses the clocksource to get some | |
8fbb97a2 | 72 | * better resolution when scheduling the kernel. |
2a847513 | 73 | */ |
2f0778af | 74 | static u32 notrace nomadik_read_sched_clock(void) |
2a847513 | 75 | { |
8fbb97a2 LW |
76 | if (unlikely(!mtu_base)) |
77 | return 0; | |
78 | ||
2f0778af | 79 | return -readl(mtu_base + MTU_VAL(0)); |
2a847513 | 80 | } |
cba13830 | 81 | #endif |
2f73a068 | 82 | |
b102c01f | 83 | /* Clockevent device: use one-shot mode */ |
2f73a068 JA |
84 | static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev) |
85 | { | |
86 | writel(1 << 1, mtu_base + MTU_IMSC); | |
87 | writel(evt, mtu_base + MTU_LR(1)); | |
88 | /* Load highest value, enable device, enable interrupts */ | |
89 | writel(MTU_CRn_ONESHOT | clk_prescale | | |
90 | MTU_CRn_32BITS | MTU_CRn_ENA, | |
91 | mtu_base + MTU_CR(1)); | |
92 | ||
93 | return 0; | |
94 | } | |
95 | ||
05387a9f | 96 | void nmdk_clkevt_reset(void) |
2f73a068 JA |
97 | { |
98 | if (clkevt_periodic) { | |
2f73a068 JA |
99 | /* Timer: configure load and background-load, and fire it up */ |
100 | writel(nmdk_cycle, mtu_base + MTU_LR(1)); | |
101 | writel(nmdk_cycle, mtu_base + MTU_BGLR(1)); | |
102 | ||
103 | writel(MTU_CRn_PERIODIC | clk_prescale | | |
104 | MTU_CRn_32BITS | MTU_CRn_ENA, | |
105 | mtu_base + MTU_CR(1)); | |
106 | writel(1 << 1, mtu_base + MTU_IMSC); | |
107 | } else { | |
108 | /* Generate an interrupt to start the clockevent again */ | |
109 | (void) nmdk_clkevt_next(nmdk_cycle, NULL); | |
110 | } | |
111 | } | |
112 | ||
28ad94ec AR |
113 | static void nmdk_clkevt_mode(enum clock_event_mode mode, |
114 | struct clock_event_device *dev) | |
115 | { | |
28ad94ec AR |
116 | switch (mode) { |
117 | case CLOCK_EVT_MODE_PERIODIC: | |
2f73a068 JA |
118 | clkevt_periodic = true; |
119 | nmdk_clkevt_reset(); | |
28ad94ec AR |
120 | break; |
121 | case CLOCK_EVT_MODE_ONESHOT: | |
2f73a068 | 122 | clkevt_periodic = false; |
b102c01f | 123 | break; |
28ad94ec AR |
124 | case CLOCK_EVT_MODE_SHUTDOWN: |
125 | case CLOCK_EVT_MODE_UNUSED: | |
b102c01f | 126 | writel(0, mtu_base + MTU_IMSC); |
2917947a | 127 | /* disable timer */ |
2f73a068 | 128 | writel(0, mtu_base + MTU_CR(1)); |
2917947a LW |
129 | /* load some high default value */ |
130 | writel(0xffffffff, mtu_base + MTU_LR(1)); | |
28ad94ec AR |
131 | break; |
132 | case CLOCK_EVT_MODE_RESUME: | |
133 | break; | |
134 | } | |
135 | } | |
136 | ||
137 | static struct clock_event_device nmdk_clkevt = { | |
b102c01f | 138 | .name = "mtu_1", |
2f73a068 | 139 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, |
b102c01f | 140 | .rating = 200, |
28ad94ec | 141 | .set_mode = nmdk_clkevt_mode, |
b102c01f | 142 | .set_next_event = nmdk_clkevt_next, |
28ad94ec AR |
143 | }; |
144 | ||
145 | /* | |
b102c01f | 146 | * IRQ Handler for timer 1 of the MTU block. |
28ad94ec AR |
147 | */ |
148 | static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id) | |
149 | { | |
b102c01f | 150 | struct clock_event_device *evdev = dev_id; |
28ad94ec | 151 | |
b102c01f AR |
152 | writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */ |
153 | evdev->event_handler(evdev); | |
28ad94ec AR |
154 | return IRQ_HANDLED; |
155 | } | |
156 | ||
28ad94ec AR |
157 | static struct irqaction nmdk_timer_irq = { |
158 | .name = "Nomadik Timer Tick", | |
159 | .flags = IRQF_DISABLED | IRQF_TIMER, | |
160 | .handler = nmdk_timer_interrupt, | |
b102c01f | 161 | .dev_id = &nmdk_clkevt, |
28ad94ec AR |
162 | }; |
163 | ||
05387a9f | 164 | void nmdk_clksrc_reset(void) |
2f73a068 JA |
165 | { |
166 | /* Disable */ | |
167 | writel(0, mtu_base + MTU_CR(0)); | |
168 | ||
169 | /* ClockSource: configure load and background-load, and fire it up */ | |
170 | writel(nmdk_cycle, mtu_base + MTU_LR(0)); | |
171 | writel(nmdk_cycle, mtu_base + MTU_BGLR(0)); | |
172 | ||
173 | writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA, | |
174 | mtu_base + MTU_CR(0)); | |
175 | } | |
176 | ||
b9576623 | 177 | void __init nmdk_timer_init(void __iomem *base) |
28ad94ec | 178 | { |
28ad94ec | 179 | unsigned long rate; |
ba327b1e | 180 | struct clk *clk0; |
ba327b1e | 181 | |
b9576623 | 182 | mtu_base = base; |
ba327b1e LW |
183 | clk0 = clk_get_sys("mtu0", NULL); |
184 | BUG_ON(IS_ERR(clk0)); | |
d3e8b756 LW |
185 | BUG_ON(clk_prepare(clk0) < 0); |
186 | BUG_ON(clk_enable(clk0) < 0); | |
b102c01f AR |
187 | |
188 | /* | |
a0719f52 LW |
189 | * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz |
190 | * for ux500. | |
191 | * Use a divide-by-16 counter if the tick rate is more than 32MHz. | |
192 | * At 32 MHz, the timer (with 32 bit counter) can be programmed | |
193 | * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer | |
194 | * with 16 gives too low timer resolution. | |
b102c01f | 195 | */ |
ba327b1e | 196 | rate = clk_get_rate(clk0); |
a0719f52 | 197 | if (rate > 32000000) { |
b102c01f | 198 | rate /= 16; |
2f73a068 | 199 | clk_prescale = MTU_CRn_PRESCALE_16; |
b102c01f | 200 | } else { |
2f73a068 | 201 | clk_prescale = MTU_CRn_PRESCALE_1; |
b102c01f | 202 | } |
28ad94ec | 203 | |
2f73a068 JA |
204 | nmdk_cycle = (rate + HZ/2) / HZ; |
205 | ||
206 | ||
b102c01f | 207 | /* Timer 0 is the free running clocksource */ |
2f73a068 | 208 | nmdk_clksrc_reset(); |
28ad94ec | 209 | |
bfe45e0b RK |
210 | if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0", |
211 | rate, 200, 32, clocksource_mmio_readl_down)) | |
b102c01f | 212 | pr_err("timer: failed to initialize clock source %s\n", |
bfe45e0b | 213 | "mtu_0"); |
2f0778af | 214 | |
cba13830 | 215 | #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK |
2f0778af | 216 | setup_sched_clock(nomadik_read_sched_clock, 32, rate); |
cba13830 | 217 | #endif |
2f0778af | 218 | |
a3b86a6d | 219 | /* Timer 1 is used for events, register irq and clockevents */ |
28ad94ec | 220 | setup_irq(IRQ_MTU0, &nmdk_timer_irq); |
a3b86a6d LW |
221 | nmdk_clkevt.cpumask = cpumask_of(0); |
222 | clockevents_config_and_register(&nmdk_clkevt, rate, 2, 0xffffffffU); | |
28ad94ec | 223 | } |