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5e1c5ff4 TL |
1 | /* |
2 | * linux/arch/arm/plat-omap/common.c | |
3 | * | |
4 | * Code common to all OMAP machines. | |
44169075 SS |
5 | * The file is created by Tony Lindgren <tony@atomide.com> |
6 | * | |
7 | * Copyright (C) 2009 Texas Instruments | |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
5e1c5ff4 TL |
9 | * |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License version 2 as | |
12 | * published by the Free Software Foundation. | |
13 | */ | |
5e1c5ff4 TL |
14 | #include <linux/module.h> |
15 | #include <linux/kernel.h> | |
16 | #include <linux/init.h> | |
17 | #include <linux/delay.h> | |
5e1c5ff4 TL |
18 | #include <linux/console.h> |
19 | #include <linux/serial.h> | |
20 | #include <linux/tty.h> | |
21 | #include <linux/serial_8250.h> | |
22 | #include <linux/serial_reg.h> | |
f8ce2547 | 23 | #include <linux/clk.h> |
fced80c7 | 24 | #include <linux/io.h> |
5e1c5ff4 | 25 | |
a09e64fb | 26 | #include <mach/hardware.h> |
5e1c5ff4 TL |
27 | #include <asm/system.h> |
28 | #include <asm/pgtable.h> | |
29 | #include <asm/mach/map.h> | |
92105bb7 | 30 | #include <asm/setup.h> |
5e1c5ff4 | 31 | |
ce491cf8 TL |
32 | #include <plat/common.h> |
33 | #include <plat/board.h> | |
34 | #include <plat/control.h> | |
35 | #include <plat/mux.h> | |
36 | #include <plat/fpga.h> | |
5e1c5ff4 | 37 | |
ce491cf8 | 38 | #include <plat/clock.h> |
5e1c5ff4 | 39 | |
44595982 PW |
40 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
41 | # include "../mach-omap2/sdrc.h" | |
42 | #endif | |
43 | ||
5e1c5ff4 TL |
44 | #define NO_LENGTH_CHECK 0xffffffff |
45 | ||
92105bb7 TL |
46 | unsigned char omap_bootloader_tag[512]; |
47 | int omap_bootloader_tag_len; | |
5e1c5ff4 TL |
48 | |
49 | struct omap_board_config_kernel *omap_board_config; | |
92105bb7 | 50 | int omap_board_config_size; |
5e1c5ff4 | 51 | |
e4e7a13a TL |
52 | /* used by omap-smp.c and board-4430sdp.c */ |
53 | void __iomem *gic_cpu_base_addr; | |
54 | ||
5e1c5ff4 TL |
55 | static const void *get_config(u16 tag, size_t len, int skip, size_t *len_out) |
56 | { | |
57 | struct omap_board_config_kernel *kinfo = NULL; | |
58 | int i; | |
59 | ||
5e1c5ff4 TL |
60 | /* Try to find the config from the board-specific structures |
61 | * in the kernel. */ | |
62 | for (i = 0; i < omap_board_config_size; i++) { | |
63 | if (omap_board_config[i].tag == tag) { | |
c40fae95 TL |
64 | if (skip == 0) { |
65 | kinfo = &omap_board_config[i]; | |
66 | break; | |
67 | } else { | |
68 | skip--; | |
69 | } | |
5e1c5ff4 TL |
70 | } |
71 | } | |
72 | if (kinfo == NULL) | |
73 | return NULL; | |
74 | return kinfo->data; | |
75 | } | |
76 | ||
77 | const void *__omap_get_config(u16 tag, size_t len, int nr) | |
78 | { | |
79 | return get_config(tag, len, nr, NULL); | |
80 | } | |
81 | EXPORT_SYMBOL(__omap_get_config); | |
82 | ||
83 | const void *omap_get_var_config(u16 tag, size_t *len) | |
84 | { | |
85 | return get_config(tag, NO_LENGTH_CHECK, 0, len); | |
86 | } | |
87 | EXPORT_SYMBOL(omap_get_var_config); | |
88 | ||
075192ae KH |
89 | /* |
90 | * 32KHz clocksource ... always available, on pretty most chips except | |
91 | * OMAP 730 and 1510. Other timers could be used as clocksources, with | |
92 | * higher resolution in free-running counter modes (e.g. 12 MHz xtal), | |
93 | * but systems won't necessarily want to spend resources that way. | |
94 | */ | |
95 | ||
a4ab0d83 | 96 | #define OMAP16XX_TIMER_32K_SYNCHRONIZED 0xfffbc410 |
075192ae | 97 | |
a4ab0d83 | 98 | #if !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) |
075192ae KH |
99 | |
100 | #include <linux/clocksource.h> | |
101 | ||
a4ab0d83 TL |
102 | #ifdef CONFIG_ARCH_OMAP16XX |
103 | static cycle_t omap16xx_32k_read(struct clocksource *cs) | |
104 | { | |
105 | return omap_readl(OMAP16XX_TIMER_32K_SYNCHRONIZED); | |
106 | } | |
107 | #else | |
108 | #define omap16xx_32k_read NULL | |
109 | #endif | |
110 | ||
111 | #ifdef CONFIG_ARCH_OMAP2420 | |
112 | static cycle_t omap2420_32k_read(struct clocksource *cs) | |
113 | { | |
114 | return omap_readl(OMAP2420_32KSYNCT_BASE + 0x10); | |
115 | } | |
116 | #else | |
117 | #define omap2420_32k_read NULL | |
118 | #endif | |
119 | ||
120 | #ifdef CONFIG_ARCH_OMAP2430 | |
121 | static cycle_t omap2430_32k_read(struct clocksource *cs) | |
122 | { | |
123 | return omap_readl(OMAP2430_32KSYNCT_BASE + 0x10); | |
124 | } | |
125 | #else | |
126 | #define omap2430_32k_read NULL | |
127 | #endif | |
128 | ||
129 | #ifdef CONFIG_ARCH_OMAP34XX | |
130 | static cycle_t omap34xx_32k_read(struct clocksource *cs) | |
075192ae | 131 | { |
a4ab0d83 TL |
132 | return omap_readl(OMAP3430_32KSYNCT_BASE + 0x10); |
133 | } | |
134 | #else | |
135 | #define omap34xx_32k_read NULL | |
136 | #endif | |
137 | ||
44169075 SS |
138 | #ifdef CONFIG_ARCH_OMAP4 |
139 | static cycle_t omap44xx_32k_read(struct clocksource *cs) | |
140 | { | |
141 | return omap_readl(OMAP4430_32KSYNCT_BASE + 0x10); | |
142 | } | |
143 | #else | |
144 | #define omap44xx_32k_read NULL | |
145 | #endif | |
146 | ||
a4ab0d83 TL |
147 | /* |
148 | * Kernel assumes that sched_clock can be called early but may not have | |
149 | * things ready yet. | |
150 | */ | |
151 | static cycle_t omap_32k_read_dummy(struct clocksource *cs) | |
152 | { | |
153 | return 0; | |
075192ae KH |
154 | } |
155 | ||
156 | static struct clocksource clocksource_32k = { | |
157 | .name = "32k_counter", | |
158 | .rating = 250, | |
a4ab0d83 | 159 | .read = omap_32k_read_dummy, |
075192ae KH |
160 | .mask = CLOCKSOURCE_MASK(32), |
161 | .shift = 10, | |
162 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, | |
163 | }; | |
164 | ||
f258b0c6 KH |
165 | /* |
166 | * Returns current time from boot in nsecs. It's OK for this to wrap | |
167 | * around for now, as it's just a relative time stamp. | |
168 | */ | |
169 | unsigned long long sched_clock(void) | |
170 | { | |
0a544198 MS |
171 | return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k), |
172 | clocksource_32k.mult, clocksource_32k.shift); | |
f258b0c6 KH |
173 | } |
174 | ||
d92cfcbe KH |
175 | /** |
176 | * read_persistent_clock - Return time from a persistent clock. | |
177 | * | |
178 | * Reads the time from a source which isn't disabled during PM, the | |
179 | * 32k sync timer. Convert the cycles elapsed since last read into | |
180 | * nsecs and adds to a monotonically increasing timespec. | |
181 | */ | |
182 | static struct timespec persistent_ts; | |
183 | static cycles_t cycles, last_cycles; | |
184 | void read_persistent_clock(struct timespec *ts) | |
185 | { | |
186 | unsigned long long nsecs; | |
187 | cycles_t delta; | |
188 | struct timespec *tsp = &persistent_ts; | |
189 | ||
190 | last_cycles = cycles; | |
191 | cycles = clocksource_32k.read(&clocksource_32k); | |
192 | delta = cycles - last_cycles; | |
193 | ||
194 | nsecs = clocksource_cyc2ns(delta, | |
195 | clocksource_32k.mult, clocksource_32k.shift); | |
196 | ||
197 | timespec_add_ns(tsp, nsecs); | |
198 | *ts = *tsp; | |
199 | } | |
200 | ||
075192ae KH |
201 | static int __init omap_init_clocksource_32k(void) |
202 | { | |
203 | static char err[] __initdata = KERN_ERR | |
204 | "%s: can't register clocksource!\n"; | |
205 | ||
44595982 PW |
206 | if (cpu_is_omap16xx() || cpu_class_is_omap2()) { |
207 | struct clk *sync_32k_ick; | |
208 | ||
a4ab0d83 TL |
209 | if (cpu_is_omap16xx()) |
210 | clocksource_32k.read = omap16xx_32k_read; | |
211 | else if (cpu_is_omap2420()) | |
212 | clocksource_32k.read = omap2420_32k_read; | |
213 | else if (cpu_is_omap2430()) | |
214 | clocksource_32k.read = omap2430_32k_read; | |
215 | else if (cpu_is_omap34xx()) | |
216 | clocksource_32k.read = omap34xx_32k_read; | |
44169075 SS |
217 | else if (cpu_is_omap44xx()) |
218 | clocksource_32k.read = omap44xx_32k_read; | |
a4ab0d83 TL |
219 | else |
220 | return -ENODEV; | |
221 | ||
44595982 PW |
222 | sync_32k_ick = clk_get(NULL, "omap_32ksync_ick"); |
223 | if (sync_32k_ick) | |
224 | clk_enable(sync_32k_ick); | |
225 | ||
075192ae KH |
226 | clocksource_32k.mult = clocksource_hz2mult(32768, |
227 | clocksource_32k.shift); | |
228 | ||
229 | if (clocksource_register(&clocksource_32k)) | |
230 | printk(err, clocksource_32k.name); | |
231 | } | |
232 | return 0; | |
233 | } | |
234 | arch_initcall(omap_init_clocksource_32k); | |
235 | ||
a4ab0d83 | 236 | #endif /* !(defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP15XX)) */ |
44595982 PW |
237 | |
238 | /* Global address base setup code */ | |
239 | ||
a58caad1 TL |
240 | #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) |
241 | ||
8f9ccfee | 242 | static void __init __omap2_set_globals(struct omap_globals *omap2_globals) |
a58caad1 | 243 | { |
0e564848 | 244 | omap2_set_globals_tap(omap2_globals); |
f2ab9977 | 245 | omap2_set_globals_sdrc(omap2_globals); |
a58caad1 TL |
246 | omap2_set_globals_control(omap2_globals); |
247 | omap2_set_globals_prcm(omap2_globals); | |
248 | } | |
249 | ||
250 | #endif | |
251 | ||
44595982 | 252 | #if defined(CONFIG_ARCH_OMAP2420) |
a58caad1 TL |
253 | |
254 | static struct omap_globals omap242x_globals = { | |
0e564848 | 255 | .class = OMAP242X_CLASS, |
233fd64e SS |
256 | .tap = OMAP2_L4_IO_ADDRESS(0x48014000), |
257 | .sdrc = OMAP2_L3_IO_ADDRESS(OMAP2420_SDRC_BASE), | |
258 | .sms = OMAP2_L3_IO_ADDRESS(OMAP2420_SMS_BASE), | |
259 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP2420_CTRL_BASE), | |
260 | .prm = OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE), | |
261 | .cm = OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE), | |
a58caad1 TL |
262 | }; |
263 | ||
44595982 PW |
264 | void __init omap2_set_globals_242x(void) |
265 | { | |
8f9ccfee | 266 | __omap2_set_globals(&omap242x_globals); |
44595982 PW |
267 | } |
268 | #endif | |
269 | ||
270 | #if defined(CONFIG_ARCH_OMAP2430) | |
a58caad1 TL |
271 | |
272 | static struct omap_globals omap243x_globals = { | |
0e564848 | 273 | .class = OMAP243X_CLASS, |
233fd64e SS |
274 | .tap = OMAP2_L4_IO_ADDRESS(0x4900a000), |
275 | .sdrc = OMAP2_L3_IO_ADDRESS(OMAP243X_SDRC_BASE), | |
276 | .sms = OMAP2_L3_IO_ADDRESS(OMAP243X_SMS_BASE), | |
277 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE), | |
278 | .prm = OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE), | |
279 | .cm = OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE), | |
a58caad1 TL |
280 | }; |
281 | ||
44595982 PW |
282 | void __init omap2_set_globals_243x(void) |
283 | { | |
8f9ccfee | 284 | __omap2_set_globals(&omap243x_globals); |
44595982 PW |
285 | } |
286 | #endif | |
287 | ||
288 | #if defined(CONFIG_ARCH_OMAP3430) | |
a58caad1 TL |
289 | |
290 | static struct omap_globals omap343x_globals = { | |
0e564848 | 291 | .class = OMAP343X_CLASS, |
233fd64e SS |
292 | .tap = OMAP2_L4_IO_ADDRESS(0x4830A000), |
293 | .sdrc = OMAP2_L3_IO_ADDRESS(OMAP343X_SDRC_BASE), | |
294 | .sms = OMAP2_L3_IO_ADDRESS(OMAP343X_SMS_BASE), | |
295 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE), | |
296 | .prm = OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE), | |
297 | .cm = OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE), | |
a58caad1 TL |
298 | }; |
299 | ||
44595982 PW |
300 | void __init omap2_set_globals_343x(void) |
301 | { | |
8f9ccfee | 302 | __omap2_set_globals(&omap343x_globals); |
44595982 PW |
303 | } |
304 | #endif | |
305 | ||
44169075 SS |
306 | #if defined(CONFIG_ARCH_OMAP4) |
307 | static struct omap_globals omap4_globals = { | |
308 | .class = OMAP443X_CLASS, | |
b570e0ec | 309 | .tap = OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE), |
233fd64e SS |
310 | .ctrl = OMAP2_L4_IO_ADDRESS(OMAP443X_CTRL_BASE), |
311 | .prm = OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE), | |
312 | .cm = OMAP2_L4_IO_ADDRESS(OMAP4430_CM_BASE), | |
9ef89150 | 313 | .cm2 = OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE), |
44169075 SS |
314 | }; |
315 | ||
316 | void __init omap2_set_globals_443x(void) | |
317 | { | |
318 | omap2_set_globals_tap(&omap4_globals); | |
319 | omap2_set_globals_control(&omap4_globals); | |
9ef89150 | 320 | omap2_set_globals_prcm(&omap4_globals); |
44169075 SS |
321 | } |
322 | #endif | |
323 |