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d2912cb1 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
aa218daf PW |
2 | /* |
3 | * OMAP 32ksynctimer/counter_32k-related code | |
4 | * | |
5 | * Copyright (C) 2009 Texas Instruments | |
6 | * Copyright (C) 2010 Nokia Corporation | |
7 | * Tony Lindgren <tony@atomide.com> | |
8 | * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> | |
9 | * | |
aa218daf PW |
10 | * NOTE: This timer is not the same timer as the old OMAP1 MPU timer. |
11 | */ | |
12 | #include <linux/kernel.h> | |
13 | #include <linux/init.h> | |
14 | #include <linux/clk.h> | |
cb9675f3 | 15 | #include <linux/err.h> |
aa218daf | 16 | #include <linux/io.h> |
354a183f | 17 | #include <linux/clocksource.h> |
38ff87f7 | 18 | #include <linux/sched_clock.h> |
aa218daf | 19 | |
bd0493ea | 20 | #include <asm/mach/time.h> |
aa218daf | 21 | |
6ccc432f PW |
22 | #include <plat/counter-32k.h> |
23 | ||
1fe97c8f | 24 | /* OMAP2_32KSYNCNT_CR_OFF: offset of 32ksync counter register */ |
b009366f S |
25 | #define OMAP2_32KSYNCNT_REV_OFF 0x0 |
26 | #define OMAP2_32KSYNCNT_REV_SCHEME (0x3 << 30) | |
27 | #define OMAP2_32KSYNCNT_CR_OFF_LOW 0x10 | |
28 | #define OMAP2_32KSYNCNT_CR_OFF_HIGH 0x30 | |
1fe97c8f | 29 | |
aa218daf PW |
30 | /* |
31 | * 32KHz clocksource ... always available, on pretty most chips except | |
32 | * OMAP 730 and 1510. Other timers could be used as clocksources, with | |
33 | * higher resolution in free-running counter modes (e.g. 12 MHz xtal), | |
34 | * but systems won't necessarily want to spend resources that way. | |
35 | */ | |
1fe97c8f | 36 | static void __iomem *sync32k_cnt_reg; |
aa218daf | 37 | |
8f0678f7 | 38 | static u64 notrace omap_32k_read_sched_clock(void) |
aa218daf | 39 | { |
f6f3b50f | 40 | return sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; |
aa218daf PW |
41 | } |
42 | ||
43 | /** | |
a451570c | 44 | * omap_read_persistent_clock64 - Return time from a persistent clock. |
aa218daf PW |
45 | * |
46 | * Reads the time from a source which isn't disabled during PM, the | |
47 | * 32k sync timer. Convert the cycles elapsed since last read into | |
a451570c | 48 | * nsecs and adds to a monotonically increasing timespec64. |
aa218daf | 49 | */ |
a451570c | 50 | static struct timespec64 persistent_ts; |
9d7d6e36 | 51 | static cycles_t cycles; |
354a183f | 52 | static unsigned int persistent_mult, persistent_shift; |
9d7d6e36 | 53 | |
a451570c | 54 | static void omap_read_persistent_clock64(struct timespec64 *ts) |
aa218daf PW |
55 | { |
56 | unsigned long long nsecs; | |
9d7d6e36 | 57 | cycles_t last_cycles; |
aa218daf PW |
58 | |
59 | last_cycles = cycles; | |
f6f3b50f | 60 | cycles = sync32k_cnt_reg ? readl_relaxed(sync32k_cnt_reg) : 0; |
aa218daf | 61 | |
9d7d6e36 CC |
62 | nsecs = clocksource_cyc2ns(cycles - last_cycles, |
63 | persistent_mult, persistent_shift); | |
64 | ||
a451570c | 65 | timespec64_add_ns(&persistent_ts, nsecs); |
9d7d6e36 CC |
66 | |
67 | *ts = persistent_ts; | |
a451570c XP |
68 | } |
69 | ||
1fe97c8f VH |
70 | /** |
71 | * omap_init_clocksource_32k - setup and register counter 32k as a | |
72 | * kernel clocksource | |
73 | * @pbase: base addr of counter_32k module | |
74 | * @size: size of counter_32k to map | |
75 | * | |
76 | * Returns 0 upon success or negative error code upon failure. | |
77 | * | |
78 | */ | |
79 | int __init omap_init_clocksource_32k(void __iomem *vbase) | |
aa218daf | 80 | { |
1fe97c8f VH |
81 | int ret; |
82 | ||
83 | /* | |
b009366f S |
84 | * 32k sync Counter IP register offsets vary between the |
85 | * highlander version and the legacy ones. | |
86 | * The 'SCHEME' bits(30-31) of the revision register is used | |
87 | * to identify the version. | |
1fe97c8f | 88 | */ |
f6f3b50f | 89 | if (readl_relaxed(vbase + OMAP2_32KSYNCNT_REV_OFF) & |
b009366f S |
90 | OMAP2_32KSYNCNT_REV_SCHEME) |
91 | sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_HIGH; | |
92 | else | |
93 | sync32k_cnt_reg = vbase + OMAP2_32KSYNCNT_CR_OFF_LOW; | |
1fe97c8f VH |
94 | |
95 | /* | |
96 | * 120000 rough estimate from the calculations in | |
fba9e072 | 97 | * __clocksource_update_freq_scale. |
1fe97c8f VH |
98 | */ |
99 | clocks_calc_mult_shift(&persistent_mult, &persistent_shift, | |
100 | 32768, NSEC_PER_SEC, 120000); | |
101 | ||
102 | ret = clocksource_mmio_init(sync32k_cnt_reg, "32k_counter", 32768, | |
103 | 250, 32, clocksource_mmio_readl_up); | |
104 | if (ret) { | |
105 | pr_err("32k_counter: can't register clocksource\n"); | |
106 | return ret; | |
aa218daf | 107 | } |
1fe97c8f | 108 | |
8f0678f7 | 109 | sched_clock_register(omap_32k_read_sched_clock, 32, 32768); |
227e3958 | 110 | register_persistent_clock(omap_read_persistent_clock64); |
1fe97c8f VH |
111 | pr_info("OMAP clocksource: 32k_counter at 32768 Hz\n"); |
112 | ||
aa218daf PW |
113 | return 0; |
114 | } |